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Patent # Description
US-7,287,326 Methods of forming a contact pin assembly
A compliant contact pin assembly method for making is provided. The compliant contact pin assembly includes a contact pin formed from a portion of a substrate...
US-7,287,108 Capacitive multidrop bus compensation
The signal integrity of a high speed heavily loaded multidrop memory bus is often degraded due the numerous impedance mismatches. The impedance mismatches causes...
US-7,286,428 Offset compensated sensing for magnetic random access memory
An offset compensated memory element voltage supply including a differential amplifier with a compensation circuit, and a transistor with a gate connected to the...
US-7,286,417 Low power dissipation voltage generator
A voltage generator circuit is described for providing a regulated voltage, such as a negative word line voltage in a semiconductor memory. The generator uses a...
US-7,286,378 Serial transistor-cell array architecture
A memory device having memory cells in which a single access transistor controls the grounding of at least four storage elements, such as resistive storage...
US-7,286,180 CMOS image sensor with a low-power architecture
A system of reducing power consumption in and active pixels sensor. The sensor is broken into different blocks, and each of the blocks is individually optimized....
US-7,285,986 High speed, low power CMOS logic gate
A logic gate with a differential evaluation stage, precharge circuitry for precharging outputs of the gate, latch circuitry for latching the outputs and an...
US-7,285,979 Apparatus and method for independent control of on-die termination for output buffers of a memory device
An apparatus and method providing independent control of on-die termination (ODT) of output buffers. The ODTs for the buffer circuits of an input/output (I/O)...
US-7,285,971 Integrated circuit (IC) test assembly including phase change material for stabilizing temperature during stress...
A testing apparatus and method for testing integrated circuits is disclosed wherein a device under test is continuously maintained at a desired set point...
US-7,285,970 Load board socket adapter and interface method
A load board adapter which is removably attachable to a load board and provides removable and replaceable sockets for individual integrated circuit packages to...
US-7,285,850 Support elements for semiconductor devices with peripherally located bond pads
A support structure for a semiconductor device with peripherally disposed contacts includes a support substrate and at least one conductive column protruding...
US-7,285,839 Coating of copper and silver air bridge structures to improve electromigration resistance and other applications
An improved electrical interconnect for an integrated circuit and methods for providing the same are disclosed. The electrical interconnect includes an air...
US-7,285,821 Trench corner effect bidirectional flash memory cell
A non-volatile memory cell structure that is capable of holding two data bits. The structure includes a trench in a substrate with two sides of the trench being...
US-7,285,814 Dynamic random access memory circuitry and integrated circuitry
A method of forming a conductive contact to a conductive structure includes forming a conductive structure received within and projecting outwardly from a first...
US-7,285,812 Vertical transistors
Vertical transistors for memory cells, such as 4F2 memory cells, are disclosed. The memory cells use digit line connections formed within the isolation trench to...
US-7,285,811 MRAM device for preventing electrical shorts during fabrication
The present invention provides an MRAM cell which minimizes the occurrence of electrical shorts during fabrication. A first conductor is provided in a trench in...
US-7,285,798 CMOS inverter constructions
Thin film transistor based three-dimensional CMOS inverters utilizing a common gate bridged between a PFET device and an NFET device. One or both of the NFET and...
US-7,285,796 Raised photodiode sensor to increase fill factor and quantum efficiency in scaled pixels
An image pixel cell with a doped, hydrogenated amorphous silicon photosensor, raised above the surface of a substrate is provided. Methods of forming the raised...
US-7,285,502 Methods for forming porous insulator structures on semiconductor devices
A method for forming a porous insulative structure on a semiconductor device structure includes forming a layer of unconsolidated electrically insulative, or...
US-7,285,468 Methods of forming semiconductor constructions
The invention includes a semiconductor construction having a pair of channel regions that have sub-regions doped with indium and surrounded by boron. A pair of...
US-7,285,442 Stackable ceramic FBGA for high thermal applications
An apparatus package for high-temperature thermal applications for ball grid array semiconductor devices and a method of packaging ball grid array semiconductor...
US-7,285,365 Image enhancement for multiple exposure beams
An aspect of the present invention includes a method for patterning a workpiece covered at least partly with a layer sensitive to electromagnetic radiation by...
US-7,285,196 Methods and apparatus for making integrated-circuit wiring from copper, silver, gold, and other metals
In recent years, copper wiring has emerged as a promising substitute for the aluminum wiring in integrated circuits, because copper offers lower electrical...
US-7,285,037 Systems including differential pressure application apparatus
A differential pressure application apparatus is configured to apply different amounts of pressure to different locations of a substrate, such as a semiconductor...
US-7,284,315 Method of forming a magnetic tunnel junction
A method of forming a magnetic tunnel junction memory element and the resulting structure are disclosed. A magnetic tunnel junction memory element comprising a...
US-7,284,169 System and method for testing write strobe timing margins in memory devices
Write strobe preamble/postamble test circuitry includes a test signal generator generating first and second digital signals. Also included are a pair of phase...
US-7,283,663 Interpolation of edge portions of a digital image
A method and apparatus for interpolating color image information are provided. One or more image data values for a portion of a digital image in a vicinity of a...
US-7,283,418 Memory device and method having multiple address, data and command buses
A dynamic random access memory ("DRAM") device includes a pair of internal address buses that are selectively coupled to an external address bus by an address...
US-7,283,394 Trench corner effect bidirectional flash memory cell
A non-volatile memory cell structure that is capable of holding two data bits. The structure includes a trench in a substrate with two sides of the trench being...
US-7,283,205 Optimized optical lithography illumination source for use during the manufacture of a semiconductor device
A method and structure for optimizing an optical lithography illumination source may include a shaped diffractive optical element (DOE) interposed between the...
US-7,283,164 Method for detecting and correcting defective pixels in a digital image sensor
A bad pixel correction (BPC) algorithm that can be implemented on the image sensor chip is provided for detecting and correcting defective pixels in a digital...
US-7,283,080 High density row RAM for column parallel CMOS image sensors
A readout circuit of an imager that enables analog-to-digital converters (ADCs) to be shared between columns of the imager is provided. Groups of ADCs share a...
US-7,283,035 Radio frequency data communications device with selectively removable antenna portion and method
An adjustable radio frequency data communications device has a monolithic semiconductor integrated circuit with integrated circuitry, interrogation receiving...
US-7,282,996 Electronic amplifier with signal gain dependent bias
An apparatus having an electronic amplifier with signal gain dependent bias. The electronic apparatus includes the amplifier and a bias state control circuit....
US-7,282,972 Bias generator with feedback control
A bias generator for initializing a voltage controlled delay line by providing the voltage controlled delay line with a control signal having an initial voltage...
US-7,282,948 MOS linear region impedance curvature correction
A system and method to correct or cancel MOS linear region impedance curvature employing an analog solution to trim out the MOS linear region impedance curvature...
US-7,282,947 Memory module and method having improved signal routing topology
A registered memory module includes several memory devices coupled to a register through a plurality of transmission lines forming a symmetrical tree topology....
US-7,282,939 Circuit having a long device configured for testing
An integrated device includes a redundant bond pad for accessing internal circuitry in the event that the main bond pad for that circuitry is difficult to access...
US-7,282,932 Compliant contact pin assembly, card system and methods thereof
A compliant contact pin assembly, a contactor card, a testing system and methods for making and testing are provided. A compliant contact pin assembly includes a...
US-7,282,806 Semiconductor devices at least partially covered by a composite coating including particles dispersed through...
Devices include at least one semiconductor die including at least one surface that is at least partially covered by a photopolymer material. The photopolymer...
US-7,282,805 Bond pad rerouting element and stacked semiconductor device assemblies including the rerouting element
A rerouting element for a semiconductor device includes a dielectric film that carries conductive vias, conductive elements, and contact pads. The conductive...
US-7,282,793 Multiple die stack apparatus employing T-shaped interposer elements
Multiple integrated circuit devices in a stacked configuration that use a spacing element for allowing increased device density and increased thermal conduction...
US-7,282,792 Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice
An inventive electronic device, such as a multi-chip module (MCM), a Single In-line Memory Module (SIMM), or a Dual In-line Memory Module (DIMM), includes a...
US-7,282,789 Back-to-back semiconductor device assemblies
A back-to-back semiconductor device assembly includes two vertically mountable semiconductor devices, the backs of which are secured to one another. The bond...
US-7,282,784 Methods of manufacture of a via structure comprising a plurality of conductive elements and methods of forming...
A method of forming a multiconductor via includes forming at least one seed layer in at least one through-hole of a substrate, selectively patterning the seed...
US-7,282,783 Resistance variable memory device and method of fabrication
Methods and apparatus for providing a resistance variable memory device with agglomeration prevention and thermal stability. According to one embodiment, a...
US-7,282,762 4F.sup.2 EEPROM NROM memory arrays with vertical devices
NROM EEPROM memory devices and arrays are described that facilitate the use of vertical NROM memory cells and select gates in NOR or NAND high density memory...
US-7,282,756 Structurally-stabilized capacitors and method of making of same
Structurally-stable, tall capacitors having unique three-dimensional architectures for semiconductor devices are disclosed. The capacitors include...
US-7,282,685 Multi-point correlated sampling for image sensors
An improved passive pixel sensor (PPS) circuit comprising a correlated sampling circuit and method that integrates pixel charge leakage onto an integrating...
US-7,282,666 Method and apparatus to increase throughput of processing using pulsed radiation sources
A material processing system and method is disclosed for processing materials such as amorphous silicon in an annealing processes and lithography processes on a...
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