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Patent # Description
US-7,285,839 Coating of copper and silver air bridge structures to improve electromigration resistance and other applications
An improved electrical interconnect for an integrated circuit and methods for providing the same are disclosed. The electrical interconnect includes an air...
US-7,285,821 Trench corner effect bidirectional flash memory cell
A non-volatile memory cell structure that is capable of holding two data bits. The structure includes a trench in a substrate with two sides of the trench being...
US-7,285,814 Dynamic random access memory circuitry and integrated circuitry
A method of forming a conductive contact to a conductive structure includes forming a conductive structure received within and projecting outwardly from a first...
US-7,285,812 Vertical transistors
Vertical transistors for memory cells, such as 4F2 memory cells, are disclosed. The memory cells use digit line connections formed within the isolation trench to...
US-7,285,811 MRAM device for preventing electrical shorts during fabrication
The present invention provides an MRAM cell which minimizes the occurrence of electrical shorts during fabrication. A first conductor is provided in a trench in...
US-7,285,798 CMOS inverter constructions
Thin film transistor based three-dimensional CMOS inverters utilizing a common gate bridged between a PFET device and an NFET device. One or both of the NFET and...
US-7,285,796 Raised photodiode sensor to increase fill factor and quantum efficiency in scaled pixels
An image pixel cell with a doped, hydrogenated amorphous silicon photosensor, raised above the surface of a substrate is provided. Methods of forming the raised...
US-7,285,502 Methods for forming porous insulator structures on semiconductor devices
A method for forming a porous insulative structure on a semiconductor device structure includes forming a layer of unconsolidated electrically insulative, or...
US-7,285,468 Methods of forming semiconductor constructions
The invention includes a semiconductor construction having a pair of channel regions that have sub-regions doped with indium and surrounded by boron. A pair of...
US-7,285,442 Stackable ceramic FBGA for high thermal applications
An apparatus package for high-temperature thermal applications for ball grid array semiconductor devices and a method of packaging ball grid array semiconductor...
US-7,285,365 Image enhancement for multiple exposure beams
An aspect of the present invention includes a method for patterning a workpiece covered at least partly with a layer sensitive to electromagnetic radiation by...
US-7,285,196 Methods and apparatus for making integrated-circuit wiring from copper, silver, gold, and other metals
In recent years, copper wiring has emerged as a promising substitute for the aluminum wiring in integrated circuits, because copper offers lower electrical...
US-7,285,037 Systems including differential pressure application apparatus
A differential pressure application apparatus is configured to apply different amounts of pressure to different locations of a substrate, such as a semiconductor...
US-7,284,315 Method of forming a magnetic tunnel junction
A method of forming a magnetic tunnel junction memory element and the resulting structure are disclosed. A magnetic tunnel junction memory element comprising a...
US-7,284,169 System and method for testing write strobe timing margins in memory devices
Write strobe preamble/postamble test circuitry includes a test signal generator generating first and second digital signals. Also included are a pair of phase...
US-7,283,663 Interpolation of edge portions of a digital image
A method and apparatus for interpolating color image information are provided. One or more image data values for a portion of a digital image in a vicinity of a...
US-7,283,418 Memory device and method having multiple address, data and command buses
A dynamic random access memory ("DRAM") device includes a pair of internal address buses that are selectively coupled to an external address bus by an address...
US-7,283,394 Trench corner effect bidirectional flash memory cell
A non-volatile memory cell structure that is capable of holding two data bits. The structure includes a trench in a substrate with two sides of the trench being...
US-7,283,205 Optimized optical lithography illumination source for use during the manufacture of a semiconductor device
A method and structure for optimizing an optical lithography illumination source may include a shaped diffractive optical element (DOE) interposed between the...
US-7,283,164 Method for detecting and correcting defective pixels in a digital image sensor
A bad pixel correction (BPC) algorithm that can be implemented on the image sensor chip is provided for detecting and correcting defective pixels in a digital...
US-7,283,080 High density row RAM for column parallel CMOS image sensors
A readout circuit of an imager that enables analog-to-digital converters (ADCs) to be shared between columns of the imager is provided. Groups of ADCs share a...
US-7,283,035 Radio frequency data communications device with selectively removable antenna portion and method
An adjustable radio frequency data communications device has a monolithic semiconductor integrated circuit with integrated circuitry, interrogation receiving...
US-7,282,996 Electronic amplifier with signal gain dependent bias
An apparatus having an electronic amplifier with signal gain dependent bias. The electronic apparatus includes the amplifier and a bias state control circuit....
US-7,282,972 Bias generator with feedback control
A bias generator for initializing a voltage controlled delay line by providing the voltage controlled delay line with a control signal having an initial voltage...
US-7,282,948 MOS linear region impedance curvature correction
A system and method to correct or cancel MOS linear region impedance curvature employing an analog solution to trim out the MOS linear region impedance curvature...
US-7,282,947 Memory module and method having improved signal routing topology
A registered memory module includes several memory devices coupled to a register through a plurality of transmission lines forming a symmetrical tree topology....
US-7,282,939 Circuit having a long device configured for testing
An integrated device includes a redundant bond pad for accessing internal circuitry in the event that the main bond pad for that circuitry is difficult to access...
US-7,282,932 Compliant contact pin assembly, card system and methods thereof
A compliant contact pin assembly, a contactor card, a testing system and methods for making and testing are provided. A compliant contact pin assembly includes a...
US-7,282,806 Semiconductor devices at least partially covered by a composite coating including particles dispersed through...
Devices include at least one semiconductor die including at least one surface that is at least partially covered by a photopolymer material. The photopolymer...
US-7,282,805 Bond pad rerouting element and stacked semiconductor device assemblies including the rerouting element
A rerouting element for a semiconductor device includes a dielectric film that carries conductive vias, conductive elements, and contact pads. The conductive...
US-7,282,793 Multiple die stack apparatus employing T-shaped interposer elements
Multiple integrated circuit devices in a stacked configuration that use a spacing element for allowing increased device density and increased thermal conduction...
US-7,282,792 Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice
An inventive electronic device, such as a multi-chip module (MCM), a Single In-line Memory Module (SIMM), or a Dual In-line Memory Module (DIMM), includes a...
US-7,282,789 Back-to-back semiconductor device assemblies
A back-to-back semiconductor device assembly includes two vertically mountable semiconductor devices, the backs of which are secured to one another. The bond...
US-7,282,784 Methods of manufacture of a via structure comprising a plurality of conductive elements and methods of forming...
A method of forming a multiconductor via includes forming at least one seed layer in at least one through-hole of a substrate, selectively patterning the seed...
US-7,282,783 Resistance variable memory device and method of fabrication
Methods and apparatus for providing a resistance variable memory device with agglomeration prevention and thermal stability. According to one embodiment, a...
US-7,282,762 4F.sup.2 EEPROM NROM memory arrays with vertical devices
NROM EEPROM memory devices and arrays are described that facilitate the use of vertical NROM memory cells and select gates in NOR or NAND high density memory...
US-7,282,756 Structurally-stabilized capacitors and method of making of same
Structurally-stable, tall capacitors having unique three-dimensional architectures for semiconductor devices are disclosed. The capacitors include...
US-7,282,685 Multi-point correlated sampling for image sensors
An improved passive pixel sensor (PPS) circuit comprising a correlated sampling circuit and method that integrates pixel charge leakage onto an integrating...
US-7,282,666 Method and apparatus to increase throughput of processing using pulsed radiation sources
A material processing system and method is disclosed for processing materials such as amorphous silicon in an annealing processes and lithography processes on a...
US-7,282,457 Apparatus for stabilizing high pressure oxidation of a semiconductor device
A method and apparatus for preventing N.sub.2O from becoming super critical during a high pressure oxidation stage within a high pressure oxidation furnace is...
US-7,282,447 Method for an integrated circuit contact
A process is provided for forming vertical contacts in the manufacture of integrated circuits and devices. The process eliminates the need for precise mask...
US-7,282,443 Methods of forming metal silicide
The invention includes methods of forming metal silicide having bulk resistance of less than 30 micro-ohms-centimeter. The metal of the metal silicide can be...
US-7,282,440 Integrated circuit contact
A process is provided for forming vertical contacts in the manufacture of integrated circuits and devices so manufactured. The process eliminates the need for...
US-7,282,439 Anti-reflective coating doped with carbon for use in integrated circuit technology and method of formation
The invention pertains to films comprising silicon, oxygen and carbon and the use of the films in integrated circuit technology, such as capacitor constructions,...
US-7,282,433 Interconnect structures with bond-pads and methods of forming bump sites on bond-pads
Microelectronic workpieces that have bump sites over bond-pads and methods of fabricating such bump sites. One embodiment of such a workpiece, for example,...
US-7,282,409 Isolation structure for a memory cell using Al.sub.2O.sub.3 dielectric
The invention provides, in one exemplary embodiment, an isolation gate formed over a substrate for biasing the substrate and providing isolation between adjacent...
US-7,282,408 Surface treatment of an oxide layer to enhance adhesion of a ruthenium metal layer
A method for forming a ruthenium metal layer on a dielectric layer comprises forming a silicon dioxide layer, then treating the silicon dioxide with a...
US-7,282,401 Method and apparatus for a self-aligned recessed access device (RAD) transistor gate
A method used in fabrication of a recessed access device transistor gate has increased tolerance for mask misalignment. One embodiment of the invention comprises...
US-7,282,400 Method and apparatus on (110) surfaces of silicon structures with conduction in the <110> direction
Improved methods and structures are provided that are lateral to surfaces with a (110) crystal plane orientation such that an electrical current of such...
US-7,282,397 Methods for designing bond pad rerouting elements for use in stacked semiconductor device assemblies and for...
A rerouting element for a semiconductor device includes a substantially planar member that carries at least one contact location, at least one conductive, at...
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