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Patent # Description
US-7,372,484 Method and apparatus for reducing effects of dark current and defective pixels in an imaging device
A method and apparatus for identifying and compensating for the effects of defective pixels in high resolution digital cameras having image processing apparatus....
US-7,372,358 Portable computer supporting paging instructions
A portable computer is described that contains a circuit for receiving pages and performing security functions based on the received page. Once a page has been...
US-7,372,310 Digital frequency-multiplying DLLs
Digital delay-locked loops (DLLs) and methods are provided for signal frequency multiplication. Analog delay elements of typical frequency-multiplying DLLs are...
US-7,372,138 Routing element for use in multi-chip modules, multi-chip modules including the routing element and methods
A routing element for use in a semiconductor device assembly includes a substrate that carries conductive traces that provide either additional electrical paths...
US-7,372,131 Routing element for use in semiconductor device assemblies
A routing element for use in a semiconductor device assembly includes a substrate that carries conductive traces that provide either additional electrical paths...
US-7,372,129 Two die semiconductor assembly and system including same
A semiconductor die assembly includes a substantially planar lead frame including a die paddle and a plurality of lead fingers, a first semiconductor die secured...
US-7,372,098 Low power flash memory devices
A buried bipolar junction is provided in a floating gate transistor flash memory device. During a write operation electrons are injected into a surface depletion...
US-7,372,097 Programmable array logic or memory with p-channel devices and asymmetrical tunnel barriers
Structures and methods for programmable array type logic and/or memory with p-channel devices and asymmetrical low tunnel barrier intergate insulators are...
US-7,372,096 Programmable array logic or memory with p-channel devices and asymmetrical tunnel barriers
Structures and methods for programmable array type logic and/or memory with p-channel devices and asymmetrical low tunnel barrier intergate insulators are...
US-7,372,094 Semiconductor constructions
The invention includes a method of depositing a noble metal. A substrate is provided. The substrate has a first region and a second region. The first and second...
US-7,372,092 Memory cell, device, and system
A memory cell, device, and system include a memory cell having a shared digitline, a storage capacitor, and a plurality of access transistors configured to...
US-7,372,091 Selective epitaxy vertical integrated circuit components
Integrated circuit components are described that are formed using selective epitaxy such that the integrated circuit components, such as transistors, are...
US-7,371,697 Ion-assisted oxidation methods and the resulting structures
Oxidation methods and resulting structures including providing an oxide layer on a substrate and then re-oxidizing the oxide layer by vertical ion bombardment of...
US-7,371,676 Method for fabricating semiconductor components with through wire interconnects
A method for fabricating a semiconductor component with a through wire interconnect includes the step of providing a substrate having a circuit side, a back...
US-7,371,647 Methods of forming transistors
The invention encompasses a method of forming a structure over a semiconductor substrate. A silicon dioxide containing layer is formed across at least some of...
US-7,371,642 Multi-state NROM device
An array of NROM flash memory cells configured to store at least two bits per four F.sup.2. Split vertical channels are generated along each side of adjacent...
US-7,371,627 Memory array with ultra-thin etched pillar surround gate access transistors and buried data/bit lines
A memory array with data/bit lines extending generally in a first direction formed in an upper surface of a substrate and access transistors extending generally...
US-7,371,612 Method of fabrication of stacked semiconductor devices
A method for increasing integrated circuit density is disclosed comprising stacking an upper wafer and a lower wafer, each of which having fabricated circuitry...
US-7,371,608 Method of fabricating a stacked die having a recess in a die BGA package
Semiconductor devices and stacked die assemblies, and methods of fabricating the devices and assemblies for increasing semiconductor device density are provided.
US-7,371,587 Method for reducing diffusion through ferromagnetic materials
A method and apparatus are disclosed for inhibiting diffusion of mobile atoms from an antiferromagnetic layer toward a tunnel oxide layer and through a...
US-7,371,509 Resist pattern and reflow technology
A reflow stabilizing solution for treating photoresist patterns and a reflow technology are disclosed. The reflow stabilizing solution comprises a polymer and is...
US-7,371,333 Methods of etching nickel silicide and cobalt silicide and methods of forming conductive lines
The invention includes methods of etching nickel silicide and cobalt silicide, and methods of forming conductive lines. In one implementation, a substrate...
US-7,371,263 Plasmaless dry contact cleaning method using interhalogen compounds
A method of removing an oxide layer from an article. The article may be located in a reaction chamber into which an interhalogen compound reactive with the oxide...
US-7,370,659 Photolithographic stepper and/or scanner machines including cleaning devices and methods of cleaning...
Stepper and/or scanner machines including cleaning devices and methods for cleaning stepper and/or scanner machines are disclosed herein. In one embodiment, a...
US-7,370,306 Method and apparatus for designing a pattern on a semiconductor surface
A method of forming a pattern of elements is shown. In one embodiment, the method is used to create a reticle. In another embodiment, the method is used to...
US-7,370,226 System and method for communicating a software-generated pulse waveform between two servers in a network
A method of monitoring a status condition of a first server with a second server in a server network, and also providing synchronization and messaging between...
US-7,370,225 System and method for communicating a software-generated pulse waveform between two servers in a network
A method of monitoring a status condition of a first server with a second server in a server network, and also providing synchronization and messaging between...
US-7,370,150 System and method for managing a cache memory
A processing system optimized for data string manipulations includes data string execution circuitry associated with a bus interface unit or memory controller....
US-7,370,134 System and method for memory hub-based expansion bus
A system memory includes a memory hub controller, a memory module accessible by the memory hub controller, and an expansion module having a processor circuit...
US-7,370,122 Distributed configuration storage
Systems and methods for providing distributed configuration storage are presented. The configuration storage is divided into distributed configuration target...
US-7,369,962 Method and device for data integrity checking
The present invention relates to high speed datapaths, sometimes including mixed digital and analog voltage signals. In particular, it relates to error checking...
US-7,369,623 Apparatuses to simultaneously distribute clock signals and data on integrated circuits, interposers, and...
A technique is described for simultaneously and synchronously transmitting digital data and a clock signal in a digital integrated circuit, circuit board, or...
US-7,369,447 Random cache read
A non-volatile memory is described that utilizes a cache read mode of operation, where a next page of memory is being read/sensed from the memory array by the...
US-7,369,436 Vertical NAND flash memory device
Memory devices, arrays, and strings are included that facilitate the use of vertical floating gate memory cells in NAND architecture memory strings, arrays, and...
US-7,369,435 Write once read only memory employing floating gates
Structures and methods for write once read only memory employing floating gates are provided. The write once read only memory cell includes a floating gate...
US-7,369,434 Flash memory with multi-bit read
A memory device is described that uses extra data bits stored in a multi-level cell (MLC) to provide error information. An example embodiment provides a memory...
US-7,369,379 Methods, circuits, and applications using a resistor and a Schottky diode
A combination of a current limiting resistor and a clamping Schottky diode prevent substantial forward biasing of a pn junction associated with a pad in a...
US-7,369,291 SLM addressing methods and apparatuses
A spatial light modulator may include a plurality of deflectable modulating elements. Each of the deflectable modulating elements may further include a support...
US-7,369,217 Method and device for immersion lithography
The present invention relates to an immersion lithographic system for patterning a work piece arranged at an image plane and covered at least partly with a layer...
US-7,369,168 Circuit for an active pixel sensor
A pixel circuit includes a silicon substrate having a photodiode that converts light intensity into a voltage signal and two metal layers disposed on the...
US-7,369,167 Photo diode ID for CMOS imagers
A CMOS image pixel array formed on a chip is used for storing programmed information within the pixel array. Manufacturing lot and other data is written to the...
US-7,369,138 Full-scene anti-aliasing method and system
A method and system for performing full-scene anti-aliasing for an image through a technique of rotating and unrotating rasterization of a scene and rendering a...
US-7,369,072 Method and apparatus for calibrating imaging device circuits
A method of operating an imaging device, an imaging device, a camera system including an imaging device, and a processing system including an imaging device for...
US-7,368,965 Clock capture in clock synchronization circuitry
Clock capturing synchronization circuitry first generates a synchronized clock signal from a reference clock signal, then captures the synchronized clock signal,...
US-7,368,812 Interposers for chip-scale packages and intermediates thereof
A carrier substrate, or interposer, for use in a chip-scale package includes a material, such as a semiconductive material, that has a coefficient of thermal...
US-7,368,810 Invertible microfeature device packages
Invertible microfeature device packages and associated methods for manufacture and use are disclosed. A package in accordance with one embodiment includes a...
US-7,368,800 Methods of forming trench isolation in the fabrication of integrated circuitry, methods of fabricating memory...
The invention includes methods of forming trench isolation in the fabrication of integrated circuitry, methods of fabricating integrated circuitry including...
US-7,368,796 Metal gate engineering for surface P-channel devices
A semiconductor device, such as a CMOS device, having gates with a high work function in PMOS regions and low work functions in NMOS regions and a method of...
US-7,368,790 Strained Si/SiGe/SOI islands and processes of making same
A process of making a strained silicon-on-insulator structure is disclosed. A recess is formed in a substrate to laterally isolate an active area. An...
US-7,368,701 Optical channels for multi-level metal optical imagers and method for manufacturing same
The manufacture of multi-level optical imagers and the resulting imagers are described. Multiple levels of metallization are prepared, each level having a via....
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