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Patent # Description
US-7,283,663 Interpolation of edge portions of a digital image
A method and apparatus for interpolating color image information are provided. One or more image data values for a portion of a digital image in a vicinity of a...
US-7,283,418 Memory device and method having multiple address, data and command buses
A dynamic random access memory ("DRAM") device includes a pair of internal address buses that are selectively coupled to an external address bus by an address...
US-7,283,394 Trench corner effect bidirectional flash memory cell
A non-volatile memory cell structure that is capable of holding two data bits. The structure includes a trench in a substrate with two sides of the trench being...
US-7,283,205 Optimized optical lithography illumination source for use during the manufacture of a semiconductor device
A method and structure for optimizing an optical lithography illumination source may include a shaped diffractive optical element (DOE) interposed between the...
US-7,283,164 Method for detecting and correcting defective pixels in a digital image sensor
A bad pixel correction (BPC) algorithm that can be implemented on the image sensor chip is provided for detecting and correcting defective pixels in a digital...
US-7,283,080 High density row RAM for column parallel CMOS image sensors
A readout circuit of an imager that enables analog-to-digital converters (ADCs) to be shared between columns of the imager is provided. Groups of ADCs share a...
US-7,283,035 Radio frequency data communications device with selectively removable antenna portion and method
An adjustable radio frequency data communications device has a monolithic semiconductor integrated circuit with integrated circuitry, interrogation receiving...
US-7,282,996 Electronic amplifier with signal gain dependent bias
An apparatus having an electronic amplifier with signal gain dependent bias. The electronic apparatus includes the amplifier and a bias state control circuit....
US-7,282,972 Bias generator with feedback control
A bias generator for initializing a voltage controlled delay line by providing the voltage controlled delay line with a control signal having an initial voltage...
US-7,282,948 MOS linear region impedance curvature correction
A system and method to correct or cancel MOS linear region impedance curvature employing an analog solution to trim out the MOS linear region impedance curvature...
US-7,282,947 Memory module and method having improved signal routing topology
A registered memory module includes several memory devices coupled to a register through a plurality of transmission lines forming a symmetrical tree topology....
US-7,282,939 Circuit having a long device configured for testing
An integrated device includes a redundant bond pad for accessing internal circuitry in the event that the main bond pad for that circuitry is difficult to access...
US-7,282,932 Compliant contact pin assembly, card system and methods thereof
A compliant contact pin assembly, a contactor card, a testing system and methods for making and testing are provided. A compliant contact pin assembly includes a...
US-7,282,806 Semiconductor devices at least partially covered by a composite coating including particles dispersed through...
Devices include at least one semiconductor die including at least one surface that is at least partially covered by a photopolymer material. The photopolymer...
US-7,282,805 Bond pad rerouting element and stacked semiconductor device assemblies including the rerouting element
A rerouting element for a semiconductor device includes a dielectric film that carries conductive vias, conductive elements, and contact pads. The conductive...
US-7,282,793 Multiple die stack apparatus employing T-shaped interposer elements
Multiple integrated circuit devices in a stacked configuration that use a spacing element for allowing increased device density and increased thermal conduction...
US-7,282,792 Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice
An inventive electronic device, such as a multi-chip module (MCM), a Single In-line Memory Module (SIMM), or a Dual In-line Memory Module (DIMM), includes a...
US-7,282,789 Back-to-back semiconductor device assemblies
A back-to-back semiconductor device assembly includes two vertically mountable semiconductor devices, the backs of which are secured to one another. The bond...
US-7,282,784 Methods of manufacture of a via structure comprising a plurality of conductive elements and methods of forming...
A method of forming a multiconductor via includes forming at least one seed layer in at least one through-hole of a substrate, selectively patterning the seed...
US-7,282,783 Resistance variable memory device and method of fabrication
Methods and apparatus for providing a resistance variable memory device with agglomeration prevention and thermal stability. According to one embodiment, a...
US-7,282,762 4F.sup.2 EEPROM NROM memory arrays with vertical devices
NROM EEPROM memory devices and arrays are described that facilitate the use of vertical NROM memory cells and select gates in NOR or NAND high density memory...
US-7,282,756 Structurally-stabilized capacitors and method of making of same
Structurally-stable, tall capacitors having unique three-dimensional architectures for semiconductor devices are disclosed. The capacitors include...
US-7,282,685 Multi-point correlated sampling for image sensors
An improved passive pixel sensor (PPS) circuit comprising a correlated sampling circuit and method that integrates pixel charge leakage onto an integrating...
US-7,282,666 Method and apparatus to increase throughput of processing using pulsed radiation sources
A material processing system and method is disclosed for processing materials such as amorphous silicon in an annealing processes and lithography processes on a...
US-7,282,457 Apparatus for stabilizing high pressure oxidation of a semiconductor device
A method and apparatus for preventing N.sub.2O from becoming super critical during a high pressure oxidation stage within a high pressure oxidation furnace is...
US-7,282,447 Method for an integrated circuit contact
A process is provided for forming vertical contacts in the manufacture of integrated circuits and devices. The process eliminates the need for precise mask...
US-7,282,443 Methods of forming metal silicide
The invention includes methods of forming metal silicide having bulk resistance of less than 30 micro-ohms-centimeter. The metal of the metal silicide can be...
US-7,282,440 Integrated circuit contact
A process is provided for forming vertical contacts in the manufacture of integrated circuits and devices so manufactured. The process eliminates the need for...
US-7,282,439 Anti-reflective coating doped with carbon for use in integrated circuit technology and method of formation
The invention pertains to films comprising silicon, oxygen and carbon and the use of the films in integrated circuit technology, such as capacitor constructions,...
US-7,282,433 Interconnect structures with bond-pads and methods of forming bump sites on bond-pads
Microelectronic workpieces that have bump sites over bond-pads and methods of fabricating such bump sites. One embodiment of such a workpiece, for example,...
US-7,282,409 Isolation structure for a memory cell using Al.sub.2O.sub.3 dielectric
The invention provides, in one exemplary embodiment, an isolation gate formed over a substrate for biasing the substrate and providing isolation between adjacent...
US-7,282,408 Surface treatment of an oxide layer to enhance adhesion of a ruthenium metal layer
A method for forming a ruthenium metal layer on a dielectric layer comprises forming a silicon dioxide layer, then treating the silicon dioxide with a...
US-7,282,401 Method and apparatus for a self-aligned recessed access device (RAD) transistor gate
A method used in fabrication of a recessed access device transistor gate has increased tolerance for mask misalignment. One embodiment of the invention comprises...
US-7,282,400 Method and apparatus on (110) surfaces of silicon structures with conduction in the <110> direction
Improved methods and structures are provided that are lateral to surfaces with a (110) crystal plane orientation such that an electrical current of such...
US-7,282,397 Methods for designing bond pad rerouting elements for use in stacked semiconductor device assemblies and for...
A rerouting element for a semiconductor device includes a substantially planar member that carries at least one contact location, at least one conductive, at...
US-7,282,392 Method of fabricating a stacked die in die BGA package
Semiconductor devices and stacked die assemblies, and methods of fabricating the devices and assemblies for increasing semiconductor device density are provided.
US-7,282,390 Stacked die-in-die BGA package with die having a recess
Semiconductor devices and stacked die assemblies, and methods of fabricating the devices and assemblies are provided. In an embodiment of the methods, a second...
US-7,282,387 Electro- and electroless plating of metal in the manufacture of PCRAM devices
Non-volatile, resistance variable memory devices, integrated circuit elements, and methods of forming such devices are provided. According to one embodiment of a...
US-7,282,239 Systems and methods for depositing material onto microfeature workpieces in reaction chambers
In one embodiment, the system includes a gas supply assembly having a first gas source, a first gas conduit coupled to the first gas source, a first valve...
US-7,282,131 Methods of electrochemically treating semiconductor substrates
The invention includes methods of electrochemically treating semiconductor substrates. The invention includes a method of electroplating a substance. A substrate...
US-7,281,952 Edge connector including internal layer contact, printed circuit board and electronic module incorporating same
An edge connector, system, printed circuit board and electronic module are described, which include an edge connector comprised of a substrate, including a first...
US-7,280,729 Semiconductor constructions and light-directing conduits
The invention includes optical signal conduits having rare earth elements incorporated therein. The optical signal conduits can, for example, contain rare earth...
US-7,280,549 High speed ring/bus
A data communication bus and method of operation thereof, including a plurality of nodes connected to a respective plurality of media segments. A typical node...
US-7,280,420 Data compression read mode for memory testing
Memory devices having a normal mode of operation and a test mode of operation are useful in quality programs. The test mode of operation includes a data...
US-7,280,417 System and method for capturing data signals using a data strobe signal
A signal capture system and method is used to capture a data signal using a data strobe signal having a preamble of strobe signal transitions. The system...
US-7,280,410 System and method for mode register control of data bus operating mode and impedance
A DRAM device includes a mode register that is programmed to select one of two modes for operating data bus terminals in the device. A timing circuit generates...
US-7,280,403 Flash memory device with improved programming performance
A selected word line that is coupled to a cell to be programmed is biased during a program operation. The unselected word lines are biased with a negative...
US-7,280,398 System and memory for sequential multi-plane page memory operations
A system and method for performing memory operations in a multi-plane flash memory. Commands and addresses are sequentially provided to the memory for memory...
US-7,280,395 Methods for neutralizing holes in tunnel oxides of floating-gate memory cells and devices
Methods for neutralizing holes in tunnel oxides of floating-gate memory cells and devices using a decrease in magnitude of a source voltage of a first polarity...
US-7,280,386 Method and system for controlling refresh to avoid memory cell data losses
A DRAM includes a register storing subsets of row addresses corresponding to rows containing at least one memory cell that is unable to store a data bit during a...
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