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Patent # Description
US-7,279,395 Suppression of dark current in a photosensor for imaging
A pixel cell having a halogen-rich region localized between an oxide isolation region and a photosensor. The halogen-rich region prevents leakage from the...
US-7,279,379 Methods of forming memory arrays; and methods of forming contacts to bitlines
The invention includes memory arrays, and methods which can be utilized for forming memory arrays. A patterned etch stop can be used during memory array...
US-7,279,377 Method and structure for shallow trench isolation during integrated circuit device manufacture
A method suitable for use during fabrication of a semiconductor device such as a dynamic random access memory or a flash programmable read-only memory comprises...
US-7,279,366 Method for assembling semiconductor die packages with standard ball grid array footprint
Apparatus and methods for forming semiconductor assemblies. An interposer includes a perimeter wall surrounding at least a portion of an upper surface thereof to...
US-7,279,353 Passivation planarization
A pixel cell is formed by locating a first passivation layer over the final layer of metal lines. Subsequently, the uneven, non-uniform passivation layer is...
US-7,279,118 Compositions of matter and barrier layer compositions
In one aspect, the invention encompasses a semiconductor processing method wherein a conductive copper-containing material is formed over a semiconductive...
US-7,279,041 Atomic layer deposition methods and atomic layer deposition tools
An atomic layer deposition method includes positioning a plurality of semiconductor wafers into an atomic layer deposition chamber. Deposition precursor is...
US-7,278,905 Apparatus and method for conditioning polishing surface, and polishing apparatus and method of operation
A chemical-mechanical polishing apparatus is provided with a downstream device for conditioning a web-shaped polishing pad. The device may be used to condition a...
US-7,278,129 Healing algorithm
An aspect of the present invention includes a method for reshaping sub-objects in at least one object in pattern design data to be presented to a mask writer or...
US-7,278,060 System and method for on-board diagnostics of memory modules
A memory hub includes an on-board diagnostic engine through which diagnostic testing and evaluation of the memory system can be performed. The memory hub...
US-7,278,045 Apparatus and method for generating a delayed clock signal
An apparatus and method for generating a delayed clock signal is provided. The clock signal generator includes a synchronizing circuit for generating an output...
US-7,278,038 Operational voltage control circuit and method
A method and apparatus for providing a preferred operating voltage to a memory device as specified by a stored configuration parameter. The apparatus includes a...
US-7,278,004 Burst write in a non-volatile memory device
A synchronous flash memory has been described that includes an array of non-volatile memory cells. The memory device has a package configuration that is...
US-7,277,996 Modified persistent auto precharge command protocol system and method for memory devices
A method of operating a memory device includes placing the memory device in a persistent auto precharge mode of operation, applying a disable command to the...
US-7,277,981 Scratch control memory array in a flash memory device
A memory device has a scratch control array of non-volatile memory cells that is separate from the primary array of memory cells. The scratch control array...
US-7,277,980 Non-contiguous address erasable blocks and command in flash memory
A non-volatile memory device includes a memory array having erasable blocks or memory cells. The array has pages that are not one continuous array row. As such,...
US-7,277,978 Runtime flash device detection and configuration for flash data management software
A memory device driver is described that can support multiple differing memory devices, in particular, differing Flash memory devices, by being internally...
US-7,277,965 Apparatus and methods for the automated creation of distributed configuration storage
Systems and methods for providing distributed configuration storage are presented. The configuration storage is divided into distributed configuration target...
US-7,277,357 Method and apparatus for reducing oscillation in synchronous circuits
Control signal oscillation filtering circuits, delay-locked loops, clock synchronization methods and devices and system incorporating control signal oscillation...
US-7,277,355 Method and apparatus for generating temperature-compensated read and verify operations in flash memories
Methods and an apparatuses for generating a word-line voltage are disclosed. A word-line voltage generator includes a first current source, an adjustable current...
US-7,277,352 DRAM power bus control
A dynamic random access memory (DRAM) is provided that has separate array and peripheral power busing to isolate array noise from peripheral circuits such as...
US-7,277,349 Circuit and method for reading an antifuse
An antifuse circuit and antifuse reading method for determining whether an antifuse is programmed or un-programmed. An antifuse circuit includes a sensing...
US-7,277,345 Method and system for controlling refresh to avoid memory cell data losses
A DRAM includes a register storing subsets of row addresses corresponding to rows containing at least one memory cell that is unable to store a data bit during a...
US-7,277,333 Power savings in active standby mode
Apparatus for reducing the power consumed by a memory device selectively activates a power saving mode in which operation of a delay compensation circuit may be...
US-7,277,328 Methods for neutralizing holes in tunnel oxides in tunnel oxides of floating-gate memory cells and devices
Methods for neutralizing holes in tunnel oxides of floating-gate memory cells and devices using a decrease in magnitude of a source voltage of a first polarity...
US-7,277,327 Methods for erasing flash memory
Methods for erasing flash memory using a decrease in magnitude of a source voltage of a first polarity to increase the magnitude of a control gate voltage of a...
US-7,277,326 Methods for erasing flash memory
Methods for erasing flash memory using a decrease in magnitude of a source voltage of a first polarity to increase the magnitude of a control gate voltage of a...
US-7,277,321 Method for programming and erasing an NROM cell
A nitride read only memory (NROM) cell can be programmed by applying a ramp voltage to the gate input, a constant voltage to one of the two source/drain regions,...
US-7,277,313 Resistance variable memory element with threshold device and method of forming the same
A memory device having a memory portion connected in series with a threshold device between. The memory portion stores at least one bit of data based on at least...
US-7,277,311 Flash cell fuse circuit
Fuse circuits based on a single flash cell or floating-gate memory cell are adapted for use in memory devices, particularly in low-voltage, flash memory...
US-7,277,310 Open digit line array architecture for a memory array
A system and method for sensing a data state stored by a memory cell that includes coupling a first digit line and a second digit line to a precharge voltage and...
US-7,277,011 Removable memory media with integral indicator light
A flash memory module includes an integral indicator light. The module alternatively includes a plurality electrical contacts which electrically interface to a...
US-7,276,955 Circuit and method for stable fuse detection
A fuse state detection circuit is comprised of a first fuse element, a second fuse element, and an output for carrying an output signal, the output signal...
US-7,276,951 Delay line circuit
Delay circuitry is described that includes clock mixing circuitry to provide a selectable propagation time. Output signals from the mixing circuitry are...
US-7,276,949 Multiphase clock generation
A first-phase clock signal is generated in response to a first input clock signal. A second-phase clock signal is generated one clock cycle of the first input...
US-7,276,947 Delay circuit with reset-based forward path static delay
A delay locked loop circuit and method of operating the same. The delay locked loop circuit comprises a forward delay path having a variable delay portion and a...
US-7,276,946 Measure-controlled delay circuits with reduced phase error
Measure-controlled delay (MCD) circuits include a measure circuit and sample circuit for synchronizing an output clock to an input clock. In response to...
US-7,276,945 Low power and low timing jitter phase-lock loop and method
A phase-lock loop generates an output clock signal from an input clock signal. The output clock signal is coupled through a clock tree and is fed back to a phase...
US-7,276,928 System and method for testing devices utilizing capacitively coupled signaling
An apparatus and method for testing a semiconductor device in an AC test regime. The test apparatus includes a test plate capacitively couple to the signal...
US-7,276,927 Device and method for isolating a short-circuited integrated circuit (IC) from other ICs on a semiconductor wafer
A circuit for isolating a short-circuited integrated circuit (IC) formed on the surface of a semiconductor wafer from other ICs formed on the wafer that are...
US-7,276,926 Method for isolating a short-circuited integrated circuit (IC) from other ICs on a semiconductor wafer
A circuit for isolating a short-circuited integrated circuit (IC) formed on the surface of a semiconductor wafer from other ICs formed on the wafer that are...
US-7,276,802 Semiconductor integrated circuit package having electrically disconnected solder balls for mounting
Integrated circuit packages that connect solder balls between solder ball pads of a die and substrate pads of a printed circuit board (PCB). The solder balls are...
US-7,276,795 Small grain size, conformal aluminum interconnects and method for their formation
A first layer of titanium nitride (TiN) is formed on a semiconductor structure, such as an interconnect via. Then, a second layer of TiN is formed on the first...
US-7,276,790 Methods of forming a multi-chip module having discrete spacers
An assembly method that includes providing a first semiconductor device and positioning a second semiconductor device at least partially over the first...
US-7,276,788 Hydrophobic foamed insulators for high density circuits
A conductive system and a method of forming an insulator for use in the conductive system is disclosed. The conductive system comprises a foamed polymer layer on...
US-7,276,765 Buried transistors for silicon on insulator technology
A buried transistor particularly suitable for SOI technology, where the transistor is fabricated within a trench in a substrate and the resulting transistor...
US-7,276,762 NROM flash memory devices on ultrathin silicon
An NROM flash memory cell is implemented in an ultra-thin silicon-on-insulator structure. In a planar device, the channel between the source/drain areas is...
US-7,276,760 Low power memory subsystem with progressive non-volatility
The memory system is comprised of a plurality of memory arrays that are coupled to a processor. The memory arrays are comprised of non-volatile memory cells that...
US-7,276,756 Memory cell arrays
The invention includes a method of forming an array of memory cells. A series of capacitor constructions is formed, with the individual capacitor constructions...
US-7,276,754 Annular gate and technique for fabricating an annular gate
A memory structure having a vertically oriented access transistor with an annular gate region and a method for fabricating the structure. More specifically, a...
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