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Patent # Description
US-7,297,917 Readout technique for increasing or maintaining dynamic range in image sensors
The apparatus and method provide a readout technique and circuit for increasing or maintaining dynamic range of an image sensor. The readout technique and...
US-7,297,915 Compensation methods and systems for imaging detectors
Imaging arrays typically include thousands or millions of photodetectors that convert sensed light into corresponding electric signals, which are ultimately...
US-7,297,639 Methods for etching doped oxides in the manufacture of microfeature devices
Methods for selectively etching doped oxides in the manufacture of microfeature devices are disclosed herein. An embodiment of one such method for etching...
US-7,297,637 Use of pulsed grounding source in a plasma reactor
A method for grounding a semiconductor substrate pedestal during a portion of a high voltage power bias oscillation cycle to reduce or eliminate the detrimental...
US-7,297,623 Etch stop layer in poly-metal structures
In accordance with one embodiment of the present invention, a method of interfacing a poly-metal structure and a semiconductor substrate is provided where an...
US-7,297,617 Method for controlling diffusion in semiconductor regions
A method and device for reducing a dopant diffusion rate in a doped semiconductor region is provided. The methods and devices include selecting a plurality of...
US-7,297,563 Method of making contact pin card system
A compliant contact pin contactor card method for making is provided. The compliant contact pin assembly includes a contact pin formed from a portion of a...
US-7,297,412 Fabrication of stacked microelectronic devices
Manufacture of stacked microelectronic devices is facilitated by producing subassemblies wherein adhesive pads are applied to the back surfaces of a plurality of...
US-7,296,346 Plating buss and a method of use thereof
The present invention relates generally to a plating buss design and method for minimizing short circuit problems in PCB panel singulation. More particularly,...
US-7,295,462 Method and apparatus processing variable resistance memory cell write operation
A circuit and method for writing to a variable resistance memory cell. The circuit includes a variable resistance memory cell, a switchable current blocking...
US-7,295,081 Time delay oscillator for integrated circuits
One aspect relates to an oscillator, and various oscillator embodiments comprise an amplifier and line driver with an input and an output and a transmission line...
US-7,294,921 System-on-a-chip with multi-layered metallized through-hole interconnection
The present invention is directed to a high-performance system on a chip which uses multi-layer wiring/insulation through-hole interconnections to provide short...
US-7,294,911 Ultrathin leadframe BGA circuit package
A circuit package is formed using a leadframe. The leadframe is formed or etched to align a plurality of bond pad structures above a reference plane while...
US-7,294,903 Transistor assemblies
Semiconductor processing methods of forming transistors, semiconductor processing methods of forming dynamic random access memory circuitry, and related...
US-7,294,897 Packaged microelectronic imagers and methods of packaging microelectronic imagers
Microelectronic imagers, methods for packaging microelectronic imagers, and methods for forming electrically conductive through-wafer interconnects in...
US-7,294,893 Titanium silicide boride gate electrode
A method for use in the fabrication of a gate electrode includes providing a gate oxide layer and forming a titanium boride layer on the oxide layer. An...
US-7,294,790 Apparatus for measuring parasitic capacitance and inductance of I/O leads on an electrical component using a...
Apparatus is provided for measuring the potential for mutual coupling in an integrated circuit package of any type or configuration using a network analyzer in...
US-7,294,578 Use of a plasma source to form a layer during the formation of a semiconductor device
A method used to form a semiconductor device having a capacitor comprises placing a semiconductor wafer assembly into a chamber of a plasma source, the wafer...
US-7,294,570 Contact integration method
A method of making a contact plug and a metallization line structure is disclosed in which a substrate is provided with at least one contact hole within an...
US-7,294,567 Semiconductor contact device and method
The invention provides an advanced metallization technique for fabricating a memory cell array on a substrate. The array is fabricated by forming discrete and...
US-7,294,556 Method of forming trench isolation in the fabrication of integrated circuitry
This invention includes methods of forming a phosphorus doped silicon dioxide comprising layers, and methods of forming trench isolation in the fabrication of...
US-7,294,549 Vertical floating gate transistor
A floating gate transistor has been described that includes source and drain regions that are fabricated on different horizontal planes. A floating gate and a...
US-7,294,545 Selective polysilicon stud growth
A memory cell having a bit line contact is provided. The memory cell may be a 6F.sup.2 memory cell. The bit line contact may have a contact hole bounded by...
US-7,294,527 Method of forming a memory cell
The invention relates to the fabrication of a resistance variable material cell or programmable metallization cell. The processes described herein can form a...
US-7,294,049 Method and apparatus for removing material from microfeature workpieces
Methods and apparatus for removing materials from microfeature workpieces. One embodiment of a subpad in accordance with the invention comprises a matrix having...
US-7,294,040 Method and apparatus for supporting a microelectronic substrate relative to a planarization pad
A method and apparatus for planarizing a microelectronic substrate. In one embodiment, one surface of the microelectronic substrate is engaged with a planarizing...
US-7,293,526 Plasma reaction chamber liner consisting essentially of osmium
The invention encompasses a method of enhancing selectivity of etching silicon dioxide relative to one or more organic substances. A material comprising one or...
US-7,292,497 Multi-bank memory
A multi-bank memory device includes rows and columns of memory cores. Each row includes memory cores from one bank interleaved with memory cores from another...
US-7,292,491 Method and apparatus for controlling refresh operations in a dynamic memory device
A method and apparatus are provided for controlling refresh operations of a dynamic memory device. The temperature of the dynamic memory device is detected. The...
US-7,292,489 Circuits and methods of temperature compensation for refresh oscillator
A memory device has refresh cycles to refresh memory cells of the memory device. The time interval between one refresh cycle to the next refresh cycle is a...
US-7,292,487 Independent polling for multi-page programming
A method of testing, polling and trimming memory pages in different memory banks simultaneously is presented, using a cache memory located in each one of the...
US-7,292,476 Programming method for NAND EEPROM
A NAND architecture non-volatile memory device and programming process is described that programs the various cells of strings of non-volatile memory cells by...
US-7,291,920 Semiconductor structures
In one aspect, the invention includes a method of forming a roughened layer of platinum, comprising: a) providing a substrate within a reaction chamber; b)...
US-7,291,917 Integrated circuitry
Methods of forming contact openings, making electrical interconnections, and related integrated circuitry are described. Integrated circuitry formed through one...
US-7,291,900 Lead frame-based semiconductor device packages incorporating at least one land grid array package
A lead frame-based semiconductor device package including at least one land grid array package. At least one semiconductor die is mounted to an interposer...
US-7,291,895 Integrated circuitry
A silicon nitride comprising layer formed over a semiconductor substrate includes Al, Ga or a mixture thereof. A silicon dioxide comprising layer is formed...
US-7,291,880 Transistor assembly
Semiconductor processing methods of forming transistors, semiconductor processing methods of forming dynamic random access memory circuitry, and related...
US-7,291,822 Amplification with feedback capacitance for photodetector signals
Signals from an imager pixel photodetector are received by an amplifier having capacitive feedback, such as a capacitive transimpedance amplifier (CTIA). The...
US-7,291,563 Method of etching a substrate; method of forming a feature on a substrate; and method of depositing a layer...
The invention includes methods of etching substrates, methods of forming features on substrates, and methods of depositing a layer comprising silicon, carbon and...
US-7,291,555 Methods of forming a reaction product and methods of forming a conductive metal silicide by reaction of metal...
A method of forming a reaction product includes providing a semiconductor substrate comprising a first material. A second material is formed over the first...
US-7,291,543 Thin flip-chip method
Methods for thinning a bumped semiconductor wafer, as well as methods for producing flip-chips of very thin profiles, are disclosed. According to the methods of...
US-7,291,519 Methods of forming transistor constructions
The invention includes a non-volatile memory cell comprising a field effect transistor construction having a body region within a crystalline material. The body...
US-7,291,425 Radiation patterning tools, and methods of forming radiation patterning tools
The invention includes, for example, a radiation patterning tool which can be utilized to form relatively circular contacts in situations in which an array of...
US-7,290,242 Pattern generation on a semiconductor surface
A method of forming a pattern of elements is shown. In one embodiment, the method is used to create a reticle. In another embodiment, the method is used to...
US-7,289,384 Method for writing to multiple banks of a memory device
In a multi-bank memory system such as a synchronous dynamic random access memory (SDRAM), a method of writing data to the banks is provided. This method allows...
US-7,289,378 Reconstruction of signal timing in integrated circuits
Improved integrated circuits, memory devices, circuitry, and data methods are described that facilitate the adjustment and reconstruction of signal timing of...
US-7,289,363 Memory cell repair using fuse programming method in a flash memory device
A method for repairing cells of a flash memory array includes using a fuse memory array circuit. The fuse memory cells are initially programmed. The locations of...
US-7,289,349 Resistance variable memory element with threshold device and method of forming the same
A memory device having a memory portion connected in series with a threshold device between. The memory portion stores at least one bit of data based on at least...
US-7,289,347 System and method for optically interconnecting memory devices
A memory device includes a semiconductor substrate in which memory circuitry has been fabricated. An address converter and a control signal converter are coupled...
US-7,288,954 Compliant contact pin test assembly and methods thereof
A compliant contact pin assembly and a contactor card and methods for testing therewith are provided. The compliant contact pin assembly includes a contact pin...
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