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Patent # Description
US-7,280,382 Apparatus and methods for optically-coupled memory systems
Optically-coupled memory systems are disclosed. In one embodiment, a system memory includes a carrier substrate, and a controller attached to the carrier...
US-7,280,381 Apparatus and methods for optically-coupled memory systems
Optically-coupled memory systems are disclosed. In one embodiment, a system memory includes a carrier substrate, and a controller attached to the carrier...
US-7,280,280 Micro-lenses for CMOS imagers and method for manufacturing micro-lenses
A micro-lens and a method for forming the micro-lens is provided. A micro-lens includes a substrate and lens material located within the substrate, the substrate...
US-7,280,279 Apparatus and method for manufacturing tilted microlenses
Asymmetrical structures and methods are used to adjust the orientation of a microlens for a pixel array. The asymmetrical structures affect volume and surface...
US-7,280,278 Apparatus and method for manufacturing positive or negative microlenses
A variety of structures and methods used to adjust the shape, radius and/or height of a microlens for a pixel array. The structures affect volume and surface...
US-7,280,162 Apparatus for assisting video compression in a computer system
One embodiment of the present invention provides an apparatus that facilitates compression of video data in a computer system by performing the time-consuming...
US-7,280,143 CMOS image sensor with active reset and 4-transistor pixels
A CMOS image sensor implementing a low noise active reset operation uses control circuitry outside a pixel sensor array and transistors in a pixel sensor as...
US-7,280,139 Double sampling active pixel sensor with double sampling temperature sensor
A system which operates to determine temperature of an image sensor using the same signal chain that is used to detect the image sensor actual outputs. A...
US-7,279,918 Methods for wafer level burn-in
A method, circuit and system for determining burn-in reliability from wafer level burn-in are disclosed. The method includes recording the number of failures in...
US-7,279,915 Test method for electronic modules using movable test contactors
A pass through test system for testing an electronic module includes an interface board, and test contactors movably mounted to the interface board for...
US-7,279,797 Module assembly and method for stacked BGA packages
Ball grid array packages that can be stacked to form highly dense components and the method for stacking ball grid arrays. The ball grid array packages comprise...
US-7,279,792 Semiconductor device and method of manufacturing same
According to this invention, a semiconductor device has an upper surface on which an external connection electrode is formed and a lower surface which opposes...
US-7,279,788 Device for establishing non-permanent electrical connection between an integrated circuit device lead element...
A spring contact for establishing electrical contact between a lead element of an IC device and a substrate. The spring contact generally comprises a contact...
US-7,279,781 Two-stage transfer molding device to encapsulate MMC module
A semiconductor card includes a printed circuit substrate upon which is mounted a card circuit including one or more semiconductor components such as dice or...
US-7,279,780 Quad flat no-lead (QFN) grid array package, method of making and memory module and computer system including same
A quad flat no-lead (QFN) grid array semiconductor package and method for making the same are provided. The package includes a semiconductor die and a lead frame...
US-7,279,772 Edge intensive antifuse and method for making the same
An antifuse including a bottom plate having a plurality of longitudinal members arranged substantially parallel to a first axis, a dielectric layer formed on the...
US-7,279,770 Isolation techniques for reducing dark current in CMOS image sensors
A structure for isolating areas in a semiconductor device is provided. The structure includes a trench having first and second portions formed in a substrate....
US-7,279,766 Photodiode sensor and photosensor for use in an imaging device
A multiple-trench photosensor for use in a CMOS imager having an improved charge capacity. The multi-trench photosensor may be either a photogate or photodiode...
US-7,279,764 Silicon-based resonant cavity photodiode for image sensors
An imager with pixels having a resonant-cavity photodiode. The resonant cavity photodiode increases absorption of light having long wavelengths. A trench is...
US-7,279,762 Magnetoresistive memory device assemblies, and methods of forming magnetoresistive memory device assemblies
The invention includes a construction comprising an MRAM device between a pair of conductive lines. Each of the conductive lines can generate a magnetic field...
US-7,279,740 Band-engineered multi-gated non-volatile memory device with enhanced attributes
Non-volatile memory devices and arrays are described that facilitate the use of band-gap engineered gate stacks with asymmetric tunnel barriers in floating gate...
US-7,279,732 Enhanced atomic layer deposition
A method of enhanced atomic layer deposition is described. In an embodiment, the enhancement is the use of plasma. Plasma begins prior to flowing a second...
US-7,279,725 Vertical diode structures
A method of making a vertical diode structure is provided, the vertical diode structure having associated therewith a diode opening extending through an...
US-7,279,710 Structure and method of fabricating a transistor having a trench gate
An integrated circuit transistor is fabricated with a trench gate having nonconductive sidewalls. The transistor is surrounded by an isolation trench filled with...
US-7,279,672 Image sensor having pinned floating diffusion diode
The present invention provides an image sensor having a pinned floating diffusion region in addition to a pinned photodiode. The pinned floating diffusion region...
US-7,279,670 Superposed multi-junction color APS
A CMOS image sensor obtains color through the use of two or three superposed layers. Each pixel in the image sensor includes a plurality of superposed...
US-7,279,668 Sequential read-out method and system that employs a single amplifier for multiple columns
Sequential read-out method and system for reading out an array of photocells are disclosed. The array includes a plurality of photocells that are arranged in...
US-7,279,435 Apparatus for stabilizing high pressure oxidation of a semiconductor device
A method and apparatus for preventing N.sub.2O from becoming super critical during a high pressure oxidation stage within a high pressure oxidation furnace are...
US-7,279,419 Formation of self-aligned contact plugs
Methods of forming a contact structure for semiconductor assemblies are described. One method provides process steps to create an inner dielectric isolation...
US-7,279,414 Method of forming interconnect structure with interlayer dielectric
The present invention relates to the formation of an ILD layer while preventing or reducing oxidation of the upper surface of a metallic interconnect. Avoidance...
US-7,279,407 Selective nickel plating of aluminum, copper, and tungsten structures
A method of selectively plating nickel on an intermediate semiconductor device structure. The method comprises providing an intermediate semiconductor device...
US-7,279,398 Microfeature workpiece processing apparatus and methods for controlling deposition of materials on microfeature...
The present disclosure provides methods and apparatus useful in depositing materials on batches of microfeature workpieces. One implementation provides a method...
US-7,279,396 Methods of forming trench isolation regions with nitride liner
The invention includes methods of forming trench isolation regions. In one implementation, a masking material is formed over a semiconductor substrate. The...
US-7,279,395 Suppression of dark current in a photosensor for imaging
A pixel cell having a halogen-rich region localized between an oxide isolation region and a photosensor. The halogen-rich region prevents leakage from the...
US-7,279,379 Methods of forming memory arrays; and methods of forming contacts to bitlines
The invention includes memory arrays, and methods which can be utilized for forming memory arrays. A patterned etch stop can be used during memory array...
US-7,279,377 Method and structure for shallow trench isolation during integrated circuit device manufacture
A method suitable for use during fabrication of a semiconductor device such as a dynamic random access memory or a flash programmable read-only memory comprises...
US-7,279,366 Method for assembling semiconductor die packages with standard ball grid array footprint
Apparatus and methods for forming semiconductor assemblies. An interposer includes a perimeter wall surrounding at least a portion of an upper surface thereof to...
US-7,279,353 Passivation planarization
A pixel cell is formed by locating a first passivation layer over the final layer of metal lines. Subsequently, the uneven, non-uniform passivation layer is...
US-7,279,118 Compositions of matter and barrier layer compositions
In one aspect, the invention encompasses a semiconductor processing method wherein a conductive copper-containing material is formed over a semiconductive...
US-7,279,041 Atomic layer deposition methods and atomic layer deposition tools
An atomic layer deposition method includes positioning a plurality of semiconductor wafers into an atomic layer deposition chamber. Deposition precursor is...
US-7,278,905 Apparatus and method for conditioning polishing surface, and polishing apparatus and method of operation
A chemical-mechanical polishing apparatus is provided with a downstream device for conditioning a web-shaped polishing pad. The device may be used to condition a...
US-7,278,129 Healing algorithm
An aspect of the present invention includes a method for reshaping sub-objects in at least one object in pattern design data to be presented to a mask writer or...
US-7,278,060 System and method for on-board diagnostics of memory modules
A memory hub includes an on-board diagnostic engine through which diagnostic testing and evaluation of the memory system can be performed. The memory hub...
US-7,278,045 Apparatus and method for generating a delayed clock signal
An apparatus and method for generating a delayed clock signal is provided. The clock signal generator includes a synchronizing circuit for generating an output...
US-7,278,038 Operational voltage control circuit and method
A method and apparatus for providing a preferred operating voltage to a memory device as specified by a stored configuration parameter. The apparatus includes a...
US-7,278,004 Burst write in a non-volatile memory device
A synchronous flash memory has been described that includes an array of non-volatile memory cells. The memory device has a package configuration that is...
US-7,277,996 Modified persistent auto precharge command protocol system and method for memory devices
A method of operating a memory device includes placing the memory device in a persistent auto precharge mode of operation, applying a disable command to the...
US-7,277,981 Scratch control memory array in a flash memory device
A memory device has a scratch control array of non-volatile memory cells that is separate from the primary array of memory cells. The scratch control array...
US-7,277,980 Non-contiguous address erasable blocks and command in flash memory
A non-volatile memory device includes a memory array having erasable blocks or memory cells. The array has pages that are not one continuous array row. As such,...
US-7,277,978 Runtime flash device detection and configuration for flash data management software
A memory device driver is described that can support multiple differing memory devices, in particular, differing Flash memory devices, by being internally...
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