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Patent # Description
US-7,276,802 Semiconductor integrated circuit package having electrically disconnected solder balls for mounting
Integrated circuit packages that connect solder balls between solder ball pads of a die and substrate pads of a printed circuit board (PCB). The solder balls are...
US-7,276,795 Small grain size, conformal aluminum interconnects and method for their formation
A first layer of titanium nitride (TiN) is formed on a semiconductor structure, such as an interconnect via. Then, a second layer of TiN is formed on the first...
US-7,276,790 Methods of forming a multi-chip module having discrete spacers
An assembly method that includes providing a first semiconductor device and positioning a second semiconductor device at least partially over the first...
US-7,276,788 Hydrophobic foamed insulators for high density circuits
A conductive system and a method of forming an insulator for use in the conductive system is disclosed. The conductive system comprises a foamed polymer layer on...
US-7,276,765 Buried transistors for silicon on insulator technology
A buried transistor particularly suitable for SOI technology, where the transistor is fabricated within a trench in a substrate and the resulting transistor...
US-7,276,762 NROM flash memory devices on ultrathin silicon
An NROM flash memory cell is implemented in an ultra-thin silicon-on-insulator structure. In a planar device, the channel between the source/drain areas is...
US-7,276,760 Low power memory subsystem with progressive non-volatility
The memory system is comprised of a plurality of memory arrays that are coupled to a processor. The memory arrays are comprised of non-volatile memory cells that...
US-7,276,756 Memory cell arrays
The invention includes a method of forming an array of memory cells. A series of capacitor constructions is formed, with the individual capacitor constructions...
US-7,276,754 Annular gate and technique for fabricating an annular gate
A memory structure having a vertically oriented access transistor with an annular gate region and a method for fabricating the structure. More specifically, a...
US-7,276,752 Methods of forming integrated circuits, and DRAM circuitry memory cells
This invention includes methods of forming integrated circuits, and includes DRAM circuitry memory cells. In one implementation, a method of forming an...
US-7,276,733 Select lines for NAND memory devices
A NAND memory array has a select line coupled to each of a plurality of NAND strings of memory cells of the memory array. The select line has a select gate at...
US-7,276,729 Electronic systems having doped aluminum oxide dielectrics
Doped aluminum oxide layers having a porous aluminum oxide layer and methods of their fabrication. The porous aluminum oxide layer may be formed by evaporation...
US-7,276,722 Non-volatile memory structure
A non-volatile memory cell utilizes a programmable conductor random access memory (PCRAM) structure instead of a polysilicon layer for a floating gate. Instead...
US-7,276,672 Method for sorting integrated circuit devices
A method for sorting integrated circuit (IC) devices of the type having a substantially unique identification (ID) code, such as a fuse ID, including...
US-7,276,455 Methods of etching an aluminum oxide comprising substrate, and methods of forming a capacitor
This invention methods of etching an aluminum oxide comprising substrate, and methods of forming capacitors. In one implementation, a method of etching an...
US-7,276,449 Gas assisted method for applying resist stripper and gas-resist stripper combinations
A method for moving resist stripper across the surface of a semiconductor substrate includes applying a wet chemical resist stripper, such as an organic or...
US-7,276,448 Method for an integrated circuit contact
A process is provided for forming vertical contacts in the manufacture of integrated circuits and devices. The process eliminates the need for precise mask...
US-7,276,446 Planarizing solutions, planarizing machines and methods for mechanical or chemical-mechanical planarization of...
Planarizing solutions, planarizing machines and methods for planarizing microelectronic-device substrate assemblies using mechanical and/or chemical-mechanical...
US-7,276,442 Method for forming a metallization layer
A method for depositing metal on a semiconductor device having a substrate, an exposed first surface, and an exposed second surface is provided. Metal ions are...
US-7,276,433 Methods of forming integrated circuitry, methods of forming memory circuitry, and methods of forming field...
The invention includes methods of forming integrated circuitry, methods of forming memory circuitry, and methods of forming field effect transistors. In one...
US-7,276,426 Methods of forming semiconductor constructions
The invention includes a method of forming a semiconductor construction. A semiconductor substrate is placed within a reaction chamber. The substrate comprises a...
US-7,276,418 Memory cell and method for forming the same
A semiconductor memory cell structure having 4F.sup.2 dimensions and method for forming the same. The memory cell is formed on a surface of a substrate and...
US-7,276,416 Method of forming a vertical transistor
The invention includes methods of forming epitaxial silicon-comprising material and methods of forming vertical transistors. In one implementation, a method of...
US-7,276,414 NAND memory arrays and methods
NAND memory arrays and methods are provided. A plurality of first gate stacks is formed on a first dielectric layer that is formed on a substrate of a NAND...
US-7,276,413 NROM flash memory devices on ultrathin silicon
An NROM flash memory cell is implemented in an ultra-thin silicon-on-insulator structure. In a planar device, the channel between the source/drain areas is...
US-7,276,409 Method of forming a capacitor
A carbon containing masking layer is patterned to include a plurality of container openings therein having minimum feature dimensions of less than or equal to...
US-7,276,397 Integrated circuit package separator methods
An integrated circuit package separator method for separating integrated circuit packages from a board having a plurality of integrated circuits. The method...
US-7,276,393 Microelectronic imaging units and methods of manufacturing microelectronic imaging units
Methods for manufacturing microelectronic imaging units and microelectronic imaging units that are formed using such methods are disclosed herein. In one...
US-7,276,387 Castellation wafer level packaging of integrated circuit chips
Systems and methods for packaging integrated circuit chips in castellation wafer level packaging are provided. The active circuit areas of the chips are coupled...
US-7,276,315 Methods for generating or designing sidelobe inhibitors for radiation patterning tools
Design methods and a computer-readable medium having computer-executable instructions thereon for sidelobe suppression in a radiation-patterning tool or mask....
US-7,275,925 Apparatus for stereolithographic processing of components and assemblies
An apparatus for providing gross location, planarization, and mechanical restraint to one or more electronic components such as semiconductor dice to be...
US-7,275,676 Apparatus for locating conductive spheres utilizing screen and hopper of solder balls
Apparatus for placing conductive spheres on prefluxed bond pads of a substrate using a stencil plate with a pattern of through-holes positioned over the bond...
US-7,275,190 Memory block quality identification in a memory device
If a memory block in a flash memory device is found to have a defect, a memory block quality indication is generated in response to the type of memory defect....
US-7,275,172 Apparatus and method for generating a delayed clock signal
An apparatus and method for generating a delayed clock signal is provided. The clock signal generator includes a synchronizing circuit for generating an output...
US-7,275,130 Method and system for dynamically operating memory in a power-saving error correcting mode
A scrubbing controller used with a DRAM stores data in an error correcting code format. The system then uses a memory control state machine and associated timer...
US-7,274,838 Method for fabricating an optical integrated circuit
The present technique relates to a method for fabricating an optical integrated circuit amplifier with another type of optical integrated circuit. In optical...
US-7,274,611 Method and architecture to calibrate read operations in synchronous flash memory
Architecture to calibrate read operations in non-volatile memory devices. In one embodiment, a synchronous flash memory is disclosed. The synchronous flash...
US-7,274,609 High speed redundant data sensing method and apparatus
An apparatus and method for coupling a normal bit line pair and a second bit line pair onto a desired bit line pair are described. This method comprises driving...
US-7,274,607 Bitline exclusion in verification operation
Methods and apparatuses for disabling a bad bitline for verification operations, and for determining whether a programming operation have failed, include setting...
US-7,274,606 Low power chip select (CS) latency option
A system and method to reduce standby currents in input buffers in an electronic device (e.g., a memory device) is disclosed. The input buffers may be activated...
US-7,274,605 Per-bit set-up and hold time adjustment for double-data rate synchronous DRAM
A synchronous double-data-rate semiconductor memory device is adapted to receive write data on both the rising and falling edges of a data strobe signal derived...
US-7,274,604 Memory device having terminals for transferring multiple types of data
A memory device includes a number of terminals for transferring input data and output data to and from a memory array. The memory device includes an auxiliary...
US-7,274,600 NAND flash memory with read and verification threshold uniformity
A plurality of cells in a flash memory device are coupled together in a series configuration, as in a NAND flash memory. A position of a first accessed cell is...
US-7,274,596 Reduction of adjacent floating gate data pattern sensitivity
The method for programming non-volatile memory cells erases the memory cells to be programmed. The memory cells are then programmed to a reduced floating gate...
US-7,274,591 Write current shunting compensation
A magnetic random access memory (MRAM) is compensated for write current shunting by varying the bit size of each MRAM cell with position along the write line....
US-7,274,582 High speed data bus
The invention comprises data processing systems and components thereof. Such systems may include a memory controller, a plurality of memory devices, a data bus...
US-7,274,397 Image sensor with active reset and randomly addressable pixels
An imaging array having one or more columns of pixels is disclosed. Each pixel includes a photodiode including first and second terminals, a local reset circuit...
US-7,274,396 Image sensors with isolated flushed pixel reset
Techniques for use with image sensors include transferring a signal level from an active sensor pixel to a readout circuit, performing a flushed reset of the...
US-7,274,319 Ramp generators for imager analog-to-digital converters
An imager with an analog-to-digital converter having at least one ramp generator that precisely and efficiently produces the desired ramp voltages required by...
US-7,274,239 Method and apparatus to set a tuning range for an analog delay
An apparatus and method for an analog fine delay line, a hybrid delay line, and a delay locked loop (DLL) is described. In the DLL, a coarse phase detector...
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