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Patent # Description
US-7,279,762 Magnetoresistive memory device assemblies, and methods of forming magnetoresistive memory device assemblies
The invention includes a construction comprising an MRAM device between a pair of conductive lines. Each of the conductive lines can generate a magnetic field...
US-7,279,740 Band-engineered multi-gated non-volatile memory device with enhanced attributes
Non-volatile memory devices and arrays are described that facilitate the use of band-gap engineered gate stacks with asymmetric tunnel barriers in floating gate...
US-7,279,732 Enhanced atomic layer deposition
A method of enhanced atomic layer deposition is described. In an embodiment, the enhancement is the use of plasma. Plasma begins prior to flowing a second...
US-7,279,725 Vertical diode structures
A method of making a vertical diode structure is provided, the vertical diode structure having associated therewith a diode opening extending through an...
US-7,279,710 Structure and method of fabricating a transistor having a trench gate
An integrated circuit transistor is fabricated with a trench gate having nonconductive sidewalls. The transistor is surrounded by an isolation trench filled with...
US-7,279,672 Image sensor having pinned floating diffusion diode
The present invention provides an image sensor having a pinned floating diffusion region in addition to a pinned photodiode. The pinned floating diffusion region...
US-7,279,670 Superposed multi-junction color APS
A CMOS image sensor obtains color through the use of two or three superposed layers. Each pixel in the image sensor includes a plurality of superposed...
US-7,279,668 Sequential read-out method and system that employs a single amplifier for multiple columns
Sequential read-out method and system for reading out an array of photocells are disclosed. The array includes a plurality of photocells that are arranged in...
US-7,279,435 Apparatus for stabilizing high pressure oxidation of a semiconductor device
A method and apparatus for preventing N.sub.2O from becoming super critical during a high pressure oxidation stage within a high pressure oxidation furnace are...
US-7,279,419 Formation of self-aligned contact plugs
Methods of forming a contact structure for semiconductor assemblies are described. One method provides process steps to create an inner dielectric isolation...
US-7,279,414 Method of forming interconnect structure with interlayer dielectric
The present invention relates to the formation of an ILD layer while preventing or reducing oxidation of the upper surface of a metallic interconnect. Avoidance...
US-7,279,407 Selective nickel plating of aluminum, copper, and tungsten structures
A method of selectively plating nickel on an intermediate semiconductor device structure. The method comprises providing an intermediate semiconductor device...
US-7,279,398 Microfeature workpiece processing apparatus and methods for controlling deposition of materials on microfeature...
The present disclosure provides methods and apparatus useful in depositing materials on batches of microfeature workpieces. One implementation provides a method...
US-7,279,396 Methods of forming trench isolation regions with nitride liner
The invention includes methods of forming trench isolation regions. In one implementation, a masking material is formed over a semiconductor substrate. The...
US-7,279,395 Suppression of dark current in a photosensor for imaging
A pixel cell having a halogen-rich region localized between an oxide isolation region and a photosensor. The halogen-rich region prevents leakage from the...
US-7,279,379 Methods of forming memory arrays; and methods of forming contacts to bitlines
The invention includes memory arrays, and methods which can be utilized for forming memory arrays. A patterned etch stop can be used during memory array...
US-7,279,377 Method and structure for shallow trench isolation during integrated circuit device manufacture
A method suitable for use during fabrication of a semiconductor device such as a dynamic random access memory or a flash programmable read-only memory comprises...
US-7,279,366 Method for assembling semiconductor die packages with standard ball grid array footprint
Apparatus and methods for forming semiconductor assemblies. An interposer includes a perimeter wall surrounding at least a portion of an upper surface thereof to...
US-7,279,353 Passivation planarization
A pixel cell is formed by locating a first passivation layer over the final layer of metal lines. Subsequently, the uneven, non-uniform passivation layer is...
US-7,279,118 Compositions of matter and barrier layer compositions
In one aspect, the invention encompasses a semiconductor processing method wherein a conductive copper-containing material is formed over a semiconductive...
US-7,279,041 Atomic layer deposition methods and atomic layer deposition tools
An atomic layer deposition method includes positioning a plurality of semiconductor wafers into an atomic layer deposition chamber. Deposition precursor is...
US-7,278,905 Apparatus and method for conditioning polishing surface, and polishing apparatus and method of operation
A chemical-mechanical polishing apparatus is provided with a downstream device for conditioning a web-shaped polishing pad. The device may be used to condition a...
US-7,278,129 Healing algorithm
An aspect of the present invention includes a method for reshaping sub-objects in at least one object in pattern design data to be presented to a mask writer or...
US-7,278,060 System and method for on-board diagnostics of memory modules
A memory hub includes an on-board diagnostic engine through which diagnostic testing and evaluation of the memory system can be performed. The memory hub...
US-7,278,045 Apparatus and method for generating a delayed clock signal
An apparatus and method for generating a delayed clock signal is provided. The clock signal generator includes a synchronizing circuit for generating an output...
US-7,278,038 Operational voltage control circuit and method
A method and apparatus for providing a preferred operating voltage to a memory device as specified by a stored configuration parameter. The apparatus includes a...
US-7,278,004 Burst write in a non-volatile memory device
A synchronous flash memory has been described that includes an array of non-volatile memory cells. The memory device has a package configuration that is...
US-7,277,996 Modified persistent auto precharge command protocol system and method for memory devices
A method of operating a memory device includes placing the memory device in a persistent auto precharge mode of operation, applying a disable command to the...
US-7,277,981 Scratch control memory array in a flash memory device
A memory device has a scratch control array of non-volatile memory cells that is separate from the primary array of memory cells. The scratch control array...
US-7,277,980 Non-contiguous address erasable blocks and command in flash memory
A non-volatile memory device includes a memory array having erasable blocks or memory cells. The array has pages that are not one continuous array row. As such,...
US-7,277,978 Runtime flash device detection and configuration for flash data management software
A memory device driver is described that can support multiple differing memory devices, in particular, differing Flash memory devices, by being internally...
US-7,277,965 Apparatus and methods for the automated creation of distributed configuration storage
Systems and methods for providing distributed configuration storage are presented. The configuration storage is divided into distributed configuration target...
US-7,277,357 Method and apparatus for reducing oscillation in synchronous circuits
Control signal oscillation filtering circuits, delay-locked loops, clock synchronization methods and devices and system incorporating control signal oscillation...
US-7,277,355 Method and apparatus for generating temperature-compensated read and verify operations in flash memories
Methods and an apparatuses for generating a word-line voltage are disclosed. A word-line voltage generator includes a first current source, an adjustable current...
US-7,277,352 DRAM power bus control
A dynamic random access memory (DRAM) is provided that has separate array and peripheral power busing to isolate array noise from peripheral circuits such as...
US-7,277,349 Circuit and method for reading an antifuse
An antifuse circuit and antifuse reading method for determining whether an antifuse is programmed or un-programmed. An antifuse circuit includes a sensing...
US-7,277,345 Method and system for controlling refresh to avoid memory cell data losses
A DRAM includes a register storing subsets of row addresses corresponding to rows containing at least one memory cell that is unable to store a data bit during a...
US-7,277,333 Power savings in active standby mode
Apparatus for reducing the power consumed by a memory device selectively activates a power saving mode in which operation of a delay compensation circuit may be...
US-7,277,328 Methods for neutralizing holes in tunnel oxides in tunnel oxides of floating-gate memory cells and devices
Methods for neutralizing holes in tunnel oxides of floating-gate memory cells and devices using a decrease in magnitude of a source voltage of a first polarity...
US-7,277,327 Methods for erasing flash memory
Methods for erasing flash memory using a decrease in magnitude of a source voltage of a first polarity to increase the magnitude of a control gate voltage of a...
US-7,277,326 Methods for erasing flash memory
Methods for erasing flash memory using a decrease in magnitude of a source voltage of a first polarity to increase the magnitude of a control gate voltage of a...
US-7,277,321 Method for programming and erasing an NROM cell
A nitride read only memory (NROM) cell can be programmed by applying a ramp voltage to the gate input, a constant voltage to one of the two source/drain regions,...
US-7,277,313 Resistance variable memory element with threshold device and method of forming the same
A memory device having a memory portion connected in series with a threshold device between. The memory portion stores at least one bit of data based on at least...
US-7,277,311 Flash cell fuse circuit
Fuse circuits based on a single flash cell or floating-gate memory cell are adapted for use in memory devices, particularly in low-voltage, flash memory...
US-7,277,310 Open digit line array architecture for a memory array
A system and method for sensing a data state stored by a memory cell that includes coupling a first digit line and a second digit line to a precharge voltage and...
US-7,277,011 Removable memory media with integral indicator light
A flash memory module includes an integral indicator light. The module alternatively includes a plurality electrical contacts which electrically interface to a...
US-7,276,955 Circuit and method for stable fuse detection
A fuse state detection circuit is comprised of a first fuse element, a second fuse element, and an output for carrying an output signal, the output signal...
US-7,276,951 Delay line circuit
Delay circuitry is described that includes clock mixing circuitry to provide a selectable propagation time. Output signals from the mixing circuitry are...
US-7,276,949 Multiphase clock generation
A first-phase clock signal is generated in response to a first input clock signal. A second-phase clock signal is generated one clock cycle of the first input...
US-7,276,947 Delay circuit with reset-based forward path static delay
A delay locked loop circuit and method of operating the same. The delay locked loop circuit comprises a forward delay path having a variable delay portion and a...
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