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NROM memory cell, memory array, related devices and methods
An array of memory cells configured to store at least one bit per one F.sup.2 includes substantially vertical structures providing an electronic memory function...
Programming memory devices
A target memory cell of a memory device is programmed by applying a programming voltage to a word line that includes the target memory cell, determining whether...
Method and apparatus for accessing a memory array
A memory device including first and second memory elements is provided. The first and second memory elements each have first and second electrodes. The first...
Memory stacking system and method
A method of forming a stacked memory module from a plurality of memory devices is provided. Each of the plurality of memory devices is modified to include a...
Static content addressable memory cell
A static content addressable memory (CAM) cell. The CAM cell includes a latch having complementary data nodes capacitively coupled to ground, first and second...
Microlens array sheet and manufacturing method thereof
A microlens array sheet and a manufacturing method thereof. The microlens array sheet comprises: a transparent substrate; bases formed on the transparent...
In-situ spectrograph and method of measuring light wavelength
characteristics for photolithography
An in-situ spectrograph having a spectrometer module positioned at a reticle plane or at a wafer plane of a photolithography projection system is disclosed. The...
Low supply voltage bias circuit, semiconductor device, wafer and system
including same, and method of...
A bias generator and a method of generating a bias reference are disclosed. A reference transistor is connected in a diode configuration. An n-channel transistor...
Method and apparatus for reducing duty cycle distortion of an output
A method and apparatus for reducing the duty cycle distortion of a periodic signal in high speed devices. More specifically, there is provided a device having a...
Systems and methods for sensing obstructions associated with electrical
testing of microfeature workpieces
Systems and methods for sensing obstructions associated with electrical testing of microfeature workpieces are disclosed. An apparatus in accordance with one...
Apparatus for improving stability and lock time for synchronous circuits
Delay-locked loops, signal locking methods and devices and system incorporating delay-locked loops are described. A delay-locked loop includes a forward delay...
Preventing junction leakage in field emission devices
An apparatus for stabilizing the threshold voltage in an active matrix field emission device is disclosed. The apparatus includes the formation of...
Field emission display with smooth aluminum film
This invention provides a conductive aluminum film and method of forming the same, wherein a non-conductive impurity is incorporated into the aluminum film. In...
Bipolar transistors with low-resistance emitter contacts
Many integrated circuits include a type of transistor known as a bipolar junction transistor, which has an emitter contact formed of polysilicon. Unfortunately,...
Memory cell with trench-isolated transistor including first and second
An isolation trench in a semiconductor includes a first isolation trench portion having a first depth and having a first sidewall intersecting a surface of the...
One-transistor composite-gate memory
One-transistor memory devices facilitate nonvolatile data storage through the manipulation of oxygen vacancies within a trapping layer of a field-effect...
Semiconductor substrate having first and second pairs of word lines
The invention includes methods of forming memory circuitry. In one implementation, a semiconductor substrate includes a pair of word lines having a bit node...
The invention includes a method of forming a rugged semiconductor-containing surface. A first semiconductor layer is formed over a substrate, and a second...
Chemical vapor deposition of titanium from titanium tetrachloride and
A process for depositing titanium metal layers via chemical vapor deposition is disclosed. The process provides deposited titanium layers having a high degree of...
Method and structure for reducing contact aspect ratios
An intermediate metal plug is used to raise the platform to which contact is to be made. In the illustrated process, a partial bit line plug is formed adjacent a...
Semiconductor integrated circuit package having electrically disconnected
solder balls for mounting
Integrated circuit packages that connect solder balls between solder ball pads of a die and substrate pads of a printed circuit board (PCB). The solder balls are...
Methods for securing components of semiconductor device assemblies to each
other with adhesive materials that...
A method for securing a semiconductor device component to another element is provided. An adhesive material includes a pressure-sensitive component and a curable...
Methods of filling openings with oxide, and methods of forming trenched
The invention includes methods in which oxide is formed within openings in a three-step process. A first step is deposition of oxide under a pressure of greater...
Methods for increasing photo-alignment margins
Methods and structures are provided for increasing alignment margins when contacting pitch multiplied interconnect lines with other conductive features in memory...
Method of forming a contact using a sacrificial structure
A method of forming a double-sided capacitor using at least one sacrificial structure, such as a sacrificial liner or a sacrificial plug. A sacrificial liner is...
Methods of forming semiconductor constructions comprising cerium oxide and
The invention includes semiconductor constructions comprising dielectric materials which contain cerium oxide and titanium oxide. The dielectric materials can...
Methods of forming pluralities of capacitors, and integrated circuitry
A method of forming a plurality of capacitors includes providing a plurality of capacitor electrodes comprising sidewalls. The plurality of capacitor electrodes...
Memory device with high dielectric constant gate dielectrics and metal
A memory cell transistor includes a high dielectric constant tunnel insulator, a metal floating gate, and a high dielectric constant inter-gate insulator...
Methods of forming semiconductor constructions
Thin film transistor based three-dimensional CMOS inverters utilizing a common gate bridged between a PFET device and an NFET device. One or both of the NFET and...
Method of forming a pseudo SOI substrate and semiconductor devices
The present invention is generally directed to a method of forming a pseudo SOI substrate and semiconductor devices. In one illustrative embodiment, the method...
Stable PD-SOI devices and methods
One aspect of the present subject matter relates to a partially depleted silicon-on-insulator structure. The structure includes a well region formed above an...
Method for fabricating semiconductor component with stiffener and circuit
A semiconductor component includes a stiffener, a circuit decal attached to the stiffener, and a semiconductor die attached to the stiffener. The circuit decal...
Method of fabricating a semiconductor die package having improved
A ball grid array (BGA) package that includes a central cavity for receiving a semiconductor die therein is disclosed. The die rests on a base laminate, the die...
Methods for fabrication of thin semiconductor assemblies including
redistribution layers and packages and...
Methods for creating redistribution layers for only selected dice, such as known good dice, to form relatively thin semiconductor component assemblies and...
Thermoelectric control for field emission display
An active matrix display that does not require a transistor or similar current switching device at each pixel. Instead, the display employs in each pixel a...
MRAM layer having domain wall traps
A common pinned layer is shared by multiple memory cells in an MRAM device. The common pinned layer includes a plurality of domain wall traps that prevent the...
Method and apparatus for conditioning a chemical-mechanical polishing pad
A conditioner including abrasive elements for conditioning a polishing pad to be used in abrasive semiconductor substrate treatment processes, such as...
Method for magnetically establishing an electrical connection with a
contact of a semiconductor device component
A method for establishing electrical contact includes nonrigidly applying force to a semiconductor substrate in directions substantially normal to a plane of the...
System and method for communicating the synchronization status of memory
modules during initialization of the...
A memory system includes a memory hub controller coupled to a plurality of memory modules each of which includes a memory hub. The memory hub controller and the...
Minimized SAR-type column-wide ADC for image sensors
An improved analog-to-digital converter wherein a minimal amount of circuitry is provided for conversion of an analog signal to a series of digital bits. A...
Thin flexible, RFID labels, and method and apparatus for use
A radio frequency identification (REID) device may include a first, thin, flexible sheet, an antenna, and an integrated circuit. A surface portion of the first...
Test method for semiconductor components using anisotropic conductive
polymer contact system
A contact system for electrically engaging semiconductor components includes an interface board mountable to an automated test handler, and a floating substrate...
Zero power start-up circuit
An improved start-up circuit and method for self-bias circuits is described that applies a start-up voltage and current to a self-bias circuit to initialize its...
Semiconductor component having dummy segments with trapped corner air
A semiconductor component includes a leadframe, a die, upper and lower body segments encapsulating the die, and dummy segments on the leadframe. The dummy...
NROM memory device with a high-permittivity gate dielectric formed by the
low temperature oxidation of metals
A high permittivity gate dielectric formed by low temperature metal oxidation is used in an NROM memory cell. The gate dielectric has a dielectric constant...
Microelectronic imagers with optical devices and methods of manufacturing
such microelectronic imagers
Microelectronic imager assemblies comprising a workpiece including a substrate and a plurality of imaging dies on and/or in the substrate. The substrate includes...
Method and apparatus providing an optical guide for an imager pixel having
a ring of air-filled spaced slots...
A device and method to provide an optical guide of a pixel to guide incoming light onto a photosensor of the pixel and to improve the optical crosstalk immunity...
Methods of forming conductive through-wafer vias
The present invention is generally directed to various methods of forming conductive through-wafer vias. In one illustrative embodiment, the method comprises...
Stepped gate configuration for non-volatile memory
A memory device having a field effect transistor with a stepped gate dielectric and a method of making the same are herein disclosed. The stepped gate dielectric...
Formation of standard voltage threshold and low voltage threshold MOSFET
Wells are formed in a substrate where standard Vt and low Vt devices of both a first and second type are to be fabricated. Wells defining the locations of first...