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Electro-and electroless plating of metal in the manufacture of PCRAM
Non-volatile, resistance variable memory devices, integrated circuit elements, and methods of forming such devices are provided. According to one embodiment of a...
Forming oxide buffer layer for improved magnetic tunnel junctions
A metal manganese oxide buffer layer is used to seed a barrier layer in a magnetic tunnel junction memory element having pinned and free magnetic layers. An...
Single substrate annealing of magnetoresistive structure
A device for magnetically annealing magnetoresistive elements formed on wafers includes a heated chuck and a delivery mechanism for individually placing the...
Method of planarizing a surface
A method for removing at least a portion of a structure, such as a layer, film, or deposit, including ruthenium metal and/or ruthenium dioxide includes...
Systems and methods for removing microfeature workpiece surface defects
Systems and methods for removing microfeature workpiece surface defects are disclosed. A method for processing a microfeature workpiece in accordance with one...
Leadframe and method for reducing mold compound adhesion problems
An integrated circuit leadframe has a pair of leadframe rails that are specially treated to adhere to injection mold compounds to a lesser or greater degree than...
Method of making a semiconductor device having an opening in a solder mask
The present invention features a novel design for a fiducial and pin one indicator that utilizes a single solder resist opening in a die mounting substrate to...
Method of providing an interface to a plurality of peripheral devices
using bus adapter chips
A method of electrically coupling a central processing unit (CPU) of a network server to a plurality of network interface modules. The method comprises providing...
Method for manipulating data in a group of processing elements to
transpose the data using a memory stack
A method for transposing data in a plurality of processing elements is comprised of a plurality of shifting operations and a plurality of storing operations. The...
No-precharge FAMOS cell and latch circuit in a memory device
The fuse and latch circuit has a Floating gate Avalanche injection Metal Oxide Semiconductor (FAMOS) transistor (fuse) that is coupled to a read circuit. The...
AC sensing for a resistive memory
Alternating current is used to sense a logic state of a memory cell that has a resistive memory element. The memory element can be in an array and a memory...
Memory block erasing in a flash memory device
The flash memory cell erase operation performs an erase operation at a first erase voltage for a first erase time. An erase verify read operation is then...
Programmable soft-start control for charge pump
A programmable soft-start control circuit having two memory registers for regulating the ramp-up time period of charging current in a charge pump of an...
Simple and robust color saturation adjustment for digital images
A method and system for adjusting saturation in digital images that operates as closely as possible to the long-, medium-, short-(LMS) cone spectral response...
Current differential buffer
The present technique relates to a method and apparatus for operating a differential buffer. In the differential buffer, a first stage may include a differential...
Output buffer and method having a supply voltage insensitive slew rate
An output buffer includes a final driver formed by first and second MOSFET transistors that alternately couple an output terminal to respective supply voltages....
Methods for evaluating characteristics of a plasma or the effects of a
plasma on a substrate
A method for evaluating characteristics of a plasma or the effects of the plasma on a substrate includes introducing a plasma probe into a reaction chamber. The...
Method and system for discretely controllable plasma processing
A method and system for plasma generation and processing includes a plurality of beam generators each locally controllable and configured for operation upon a...
Stacked mass storage flash memory package
A stacked multiple offset chip device is formed of two or more dice of similar dimensions and bond pad arrangement, in which bond pads are located in fields...
Selective electroless-plated copper metallization
Structures and methods are provided which include a selective electroless copper metallization. The present invention includes a novel methodology for forming...
The invention encompasses methods of forming insulating materials between conductive elements. In one aspect, the invention includes a method of forming a...
The invention includes semiconductor packages having a patterned substrate with openings extending therethrough, conductive circuit traces over the substrate and...
Substrate with enhanced properties for planarization
A method and intermediate structure for improving the thinning and planarity of a wafer back side utilizing planarization material applied to the back side prior...
Semiconductor devices and other electronic components including porous
insulators created from "void" creating...
Semiconductor devices, other electronic components, and other articles of manufacture with porous insulator structures are disclosed. The insulative material of...
Open pattern inductor
The invention includes a stacked open pattern inductor fabricated above a semiconductor substrate. The stacked open pattern inductor includes a plurality of...
Metal to polysilicon contact in oxygen environment
A method for forming a contact capable of tolerating an O.sub.2 environment up to several hundred degrees Celsius for several hours is disclosed. To slow down...
Strained Si/SiGe/SOI islands and processes of making same
A process of making a strained silicon-on-insulator structure is disclosed. A recess is formed in a substrate to laterally isolate an active area. An...
Prefabricated housings for microelectronic imagers
Microelectronic imagers with prefabricated housings and methods of packaging microelectronic imagers are disclosed herein. In one embodiment, a microelectronic...
Modified facet etch to prevent blown gate oxide and increase etch chamber
A modified facet etch is disclosed to prevent blown gate oxide and increase etch chamber life. The modified facet etch is a two-stage process. The first stage is...
Methods of forming layers
The invention includes methods of forming layers conformally over undulating surface topographies associated with semiconductor substrates. The undulating...
Microfeature workpieces and methods for forming interconnects in
Methods for forming interconnects in microfeature workpieces, and microfeature workpieces having such interconnects are disclosed herein. In one embodiment, a...
Metal plating using seed film
A seed film and methods incorporating the seed film in semiconductor applications is provided. The seed film includes one or more noble metal layers, where each...
Methods for making integrated-circuit wiring from copper, silver, gold,
and other metals
Integrated circuits, the key components in thousands of electronic and computer products, include interconnected networks of electrical components. The...
Methods of forming wire bonds for semiconductor constructions
The invention includes a semiconductor construction having a wire bonding region associated with a metal-containing layer, and having radiation-imageable...
Integrated circuit and methods of redistributing bondpad locations
Integrated circuits and methods of redistributing bondpad locations are disclosed. In one implementation, a method of redistributing a bondpad location of an...
Trench isolation structure and method of formation
In general, the present invention discloses at least one trench isolation region formed in a semiconductor substrate to electrically and/or optically isolate at...
Reduction of field edge thinning in peripheral devices
A dielectric layer (e.g., an interpoly dielectric layer) is deposited over low and high voltage devices of a peripheral memory device. The dielectric behaves as...
Methods of forming field effect transistors
A mass of material is formed over a semiconductor substrate. Semiconductive material is formed laterally proximate the mass of material. A space is provided...
Methods of forming semiconductor structures
The invention includes semiconductor structures having buried silicide-containing bitlines. Vertical surround gate transistor structures can be formed over the...
Methods of fabricating underfilled, encapsulated semiconductor die
An apparatus and method may be used for packaging a semiconductor die and a carrier substrate to substantially prevent trapped moisture therebetween and provide...
Terraced film stack
A process and apparatus directed to forming a terraced film stack of a semiconductor device, for example, a DRAM memory device, is disclosed. The present...
Acid blend for removing etch residue
A method for removing organometallic and organosilicate residues remaining after a dry etch process from semiconductor substrates. The substrate is exposed to a...
Methods and apparatuses for monitoring and controlling mechanical or
chemical-mechanical planarization of...
Methods and devices for mechanical and/or chemical-mechanical planarization of semiconductor wafers, field emission displays and other microelectronic substrate...
Memory hub and access method having internal prefetch buffers
A memory module includes a memory hub coupled to several memory devices. The memory hub includes history logic that predicts on the basis of read memory requests...
Method of forming mirrors by surface transformation of empty spaces in
solid state materials
A multi-layered reflective mirror formed of spaced-apart plate-shaped empty space patterns formed within a substrate is disclosed. The plurality of plate-shaped...
Memory device and method having multiple internal data buses and memory
A memory device and method receives write data through a unidirectional downstream bus and outputs read data through a unidirectional upstream bus. The...
Flash memory supporting methods for erasing memory cells using a decrease in magnitude of a source voltage of a first polarity to increase the magnitude of a...
Operation of multiple select gate architecture
Methods of operating non-volatile memory devices including multiple series-coupled select gates on the drain and/or source ends of strings of non-volatile memory...
Microlens array sheet
Disclosed is a microlens array sheet capable of improving a viewing angle by maintaining a fill factor while reducing a radius of curvature of the microlens of...
System and method for open-loop synthesis of output clock signals having a
selected phase relative to an input...
Delay circuits are used in a manner similar to a synchronized mirror delay circuit to generate a quadrature clock signal from an input clock signal. The input...