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Patent # Description
US-7,259,604 Initialization scheme for a reduced-frequency, fifty percent duty cycle corrector
A reduced-frequency, 50% duty cycle corrector (DCC) circuit may be used in an electronic device (e.g., a memory chip) to generate output clocks with 50% duty...
US-7,259,601 Apparatus and method for suppressing jitter within a clock signal generator
A clock synchronization circuit (200, FIG. 2) includes a signal selector (202), phase detector (204), and delay line (206). The signal selector compares an...
US-7,259,581 Method for testing semiconductor components
A method for testing a semiconductor component includes the steps of bonding an interconnect to the component to form bonded electrical connections, applying...
US-7,259,578 System for testing semiconductor components having interconnect with variable flexure contacts
A test system for testing semiconductor components includes an interconnect having a substrate and contacts on the substrate for electrically engaging terminal...
US-7,259,464 Vertical twist scheme for high-density DRAMs
An interconnection array subunit and method for forming the interconnection array subunit are provided, the interconnection array subunit including a first pair...
US-7,259,451 Invertible microfeature device packages
Invertible microfeature device packages and associated methods for manufacture and use are disclosed. A package in accordance with one embodiment includes a...
US-7,259,450 Double-packaged multi-chip semiconductor module
A plurality of semiconductor die is packaged into one component. The inventive design comprises devices which have been singularized, packaged and thoroughly...
US-7,259,442 Selectively doped trench device isolation
A selectively doped trench isolation device is provided. The trench isolation device of the preferred embodiment includes a semiconductor substrate having a...
US-7,259,435 Intermediate semiconductor device having nitrogen concentration profile
A method for reducing the effective thickness of a gate oxide using nitrogen implantation and anneal subsequent to dopant implantation and activation is...
US-7,259,434 Highly reliable amorphous high-k gate oxide ZrO2
A gate oxide and method of fabricating a gate oxide that produces a more reliable and thinner equivalent oxide thickness than conventional SiO.sub.2 gate oxides...
US-7,259,415 Long retention time single transistor vertical memory gain cell
A single transistor vertical memory gain cell with long data retention times. The memory cell is formed from a silicon carbide substrate to take advantage of the...
US-7,259,413 High dynamic range image sensor
A pixel cell with controlled leakage is formed by modifying the location and gate profile of a high dynamic range (HDR) transistor. The HDR transistor may have a...
US-7,259,093 Methods of forming a conductive contact through a dielectric
A dielectric is formed over a node location on a semiconductor substrate. The dielectric comprises an insulative material over the node location, an insulative...
US-7,259,079 Methods for filling high aspect ratio trenches in semiconductor layers
Methods of filling high aspect ratio trenches in semiconductor layers are provided. The methods utilize HDP-CVD processes to fill trenches with trench filling...
US-7,259,066 One-transistor composite-gate memory
One-transistor memory devices facilitate nonvolatile data storage through the manipulation of oxygen vacancies within a trapping layer of a field-effect...
US-7,259,064 Forming integrated circuit devices
Methods of forming integrated circuit devices are provided. A first mask layer is formed overlying a first portion of a semiconductor substrate. The first mask...
US-7,258,954 Method to recover the exposure sensitivity of chemically amplified resins from post coat delay effect
Methods of fabricating a photomask, methods of treating a chemically amplified resist-coated photomask blank, a photomask blank resulting from the methods, and...
US-7,258,895 Methods of forming material on a substrate, and a method of forming a field effect transistor gate oxide on a...
The invention includes methods of forming material on a substrate and methods of forming a field effect transistor gate oxide. In one implementation, a first...
US-7,258,892 Methods and systems for controlling temperature during microfeature workpiece processing, e.g., CVD deposition
The present disclosure provides methods and systems for controlling temperature. The method has particular utility in connection with controlling temperature in...
US-7,258,596 Systems and methods for monitoring characteristics of a polishing pad used in polishing micro-device workpieces
Systems and methods for monitoring characteristics of a polishing pad used in polishing a micro-device workpiece are disclosed herein. In one embodiment, a...
US-7,257,884 Method for fabricating semiconductor component with adjustment circuitry for electrical characteristics or...
A semiconductor component includes adjustment circuitry configured to adjust selected physical and electrical characteristics of the component or elements...
US-7,257,697 Processing system with general purpose execution unit and separate independently operating data string...
A processing system optimized for data string manipulations includes data string execution circuitry associated with a bus interface unit or memory controller....
US-7,257,683 Memory arbitration system and method having an arbitration packet protocol
A memory hub and method for transmitting a read response on a data path of a memory hub interposed between a transmitting memory hub and a receiving memory hub....
US-7,257,670 Multipurpose CAM circuit
A content addressable memory (CAM) device for use in various sizes of systems while requiring minimal circuitry to enlarge the size of the prioritization...
US-7,257,667 Status register to improve initialization of a synchronous memory
A synchronous flash memory includes an array of non-volatile memory cells. The memory device has a package configuration that is compatible with an SDRAM. The...
US-7,257,043 Isolation device over field in a memory device
A memory device includes isolation devices located between-memory cells. A plurality of isolation lines connects the isolation devices to a positive voltage...
US-7,257,024 Minimizing adjacent wordline disturb in a memory device
A selected wordline that is coupled to cells for programming is biased with a programming voltage. The unselected wordlines that are adjacent to the selected...
US-7,257,022 Nanocrystal write once read only memory for archival storage
Structures and methods for write once read only memory employing charge trapping are provided. The write once read only memory cell includes a metal oxide...
US-7,256,643 Device and method for generating a low-voltage reference
A voltage reference generating method, source, memory device and substrate containing the same include a voltage reference generator comprised of a bandgap...
US-7,256,595 Test sockets, test systems, and methods for testing microfeature devices
Test sockets, test systems, and methods for testing microfeature devices with a substrate and a plurality of conductive interconnect elements projecting from the...
US-7,256,490 Test carrier for semiconductor components having conductors defined by grooves
A test carrier for a semiconductor component includes a base for retaining the component, and an interconnect on the base having contacts configured to...
US-7,256,452 NROM memory device with a high-permittivity gate dielectric formed by the low temperature oxidation of metals
A high permittivity gate dielectric formed by low temperature metal oxidation is used in an NROM memory cell. The gate dielectric has a dielectric constant...
US-7,256,451 NROM memory device with a high-permittivity gate dielectric formed by the low temperature oxidation of metals
A high permittivity gate dielectric formed by low temperature metal oxidation is used in an NROM memory cell. The gate dielectric has a dielectric constant...
US-7,256,450 NROM memory device with a high-permittivity gate dielectric formed by the low temperature oxidation of metals
A high permittivity gate dielectric formed by low temperature metal oxidation is used in an NROM memory cell. The gate dielectric has a dielectric constant...
US-7,256,138 Method and composition for selectively etching against cobalt silicide
An etching method for use in integrated circuit fabrication includes providing a metal nitride layer on a substrate assembly, providing regions of cobalt...
US-7,256,123 Method of forming an interface for a semiconductor device
In a semiconductor device using a polysilicon contact, such as a poly plug between a transistor and a capacitor in a container cell, an interface is provided...
US-7,256,116 Method for fabricating semiconductor components having encapsulated, bonded, interconnect contacts on...
A method for fabricating a semiconductor component includes the steps of providing a semiconductor die, forming a plurality of redistribution contacts on the...
US-7,256,115 Asymmetric plating
A method and apparatus are disclosed for forming a tapered contact structure over a contact pad. The tapered contact structure may be used to securely anchor an...
US-7,256,074 Methods for wafer-level packaging of microelectronic devices and microelectronic devices formed by such methods
Methods for packaging microelectronic devices, microelectronic workpieces having packaged dies, and microelectronic devices are disclosed herein. One aspect of...
US-7,256,069 Wafer-level package and methods of fabricating
A carrier for use in a chip-scale package, including a polymeric film with apertures defined therethrough. The apertures, which are alignable with corresponding...
US-7,256,068 Semiconductor package assembly and method for electrically isolating modules
A semiconductor package assembly and method for electrically isolating modules, having a capacitor within the semiconductor package assembly. The package...
US-7,255,803 Method of forming contact openings
The invention includes etching and contact opening forming methods. In one implementation, a plasma etching method includes providing a bottom powered plasma...
US-7,255,802 Tape substrate and method for fabricating the same
A method for fabricating a tape substrate includes forming, on an insulating film, a copper foil pattern having a connecting area; coating a solder resist on the...
US-7,255,630 Methods of manufacturing carrier heads for polishing micro-device workpieces
Carrier assemblies, polishing machines with carrier assemblies, and methods for mechanical and/or chemical-mechanical polishing of micro-device workpieces are...
US-7,255,273 Descriptor for identifying a defective die site
The present invention relates to the marking and identification of defective die sites on a mounting substrate. A mounting substrate is provided which is...
US-7,255,128 System and method for detecting flow in a mass flow controller
Systems and methods are provided for detecting flow in a mass flow controller (MFC). The position of a gate in the MFC is sensed or otherwise determined to...
US-RE39,768 VCC pump for CMOS imagers
A CMOS imaging device which includes a charge pump connected to one or more of a reset gate, transfer gate and row select gate of sensor cells and provides gate...
US-7,254,756 Data compression read mode for memory testing
A first series combination of bit match circuits compares a predetermined bit position in data words that are involved in a compression operation. The first...
US-7,254,753 Circuit and method for configuring CAM array margin test and operation
A test circuit for a content addressable memory (CAM) match detection circuit that permits testing of the margin of the match detection circuit. By applying...
US-7,254,331 System and method for multiple bit optical data transmission in memory systems
The disclosed system and method data increases data transmission speed through a memory system by using optical signals comprising a plurality of wavelengths of...
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