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Patent # Description
US-7,274,605 Per-bit set-up and hold time adjustment for double-data rate synchronous DRAM
A synchronous double-data-rate semiconductor memory device is adapted to receive write data on both the rising and falling edges of a data strobe signal derived...
US-7,274,604 Memory device having terminals for transferring multiple types of data
A memory device includes a number of terminals for transferring input data and output data to and from a memory array. The memory device includes an auxiliary...
US-7,274,600 NAND flash memory with read and verification threshold uniformity
A plurality of cells in a flash memory device are coupled together in a series configuration, as in a NAND flash memory. A position of a first accessed cell is...
US-7,274,596 Reduction of adjacent floating gate data pattern sensitivity
The method for programming non-volatile memory cells erases the memory cells to be programmed. The memory cells are then programmed to a reduced floating gate...
US-7,274,591 Write current shunting compensation
A magnetic random access memory (MRAM) is compensated for write current shunting by varying the bit size of each MRAM cell with position along the write line....
US-7,274,582 High speed data bus
The invention comprises data processing systems and components thereof. Such systems may include a memory controller, a plurality of memory devices, a data bus...
US-7,274,397 Image sensor with active reset and randomly addressable pixels
An imaging array having one or more columns of pixels is disclosed. Each pixel includes a photodiode including first and second terminals, a local reset circuit...
US-7,274,396 Image sensors with isolated flushed pixel reset
Techniques for use with image sensors include transferring a signal level from an active sensor pixel to a readout circuit, performing a flushed reset of the...
US-7,274,319 Ramp generators for imager analog-to-digital converters
An imager with an analog-to-digital converter having at least one ramp generator that precisely and efficiently produces the desired ramp voltages required by...
US-7,274,239 Method and apparatus to set a tuning range for an analog delay
An apparatus and method for an analog fine delay line, a hybrid delay line, and a delay locked loop (DLL) is described. In the DLL, a coarse phase detector...
US-7,274,237 Measure control delay and method having latching circuit integral with delay circuit
A measure control delay includes a measuring delay line and a signal generating delay line, each of which include a plurality of series-connected delay units. A...
US-7,274,236 Variable delay line with multiple hierarchy
Disclosed herein are improved, simplified designs for a hierarchical delay line (HDL). The HDL is useful in providing precise phase control between an input...
US-7,274,228 Method and apparatus for digital phase generation at high frequencies
An apparatus and method for generating phase related clocks, includes delaying a clock input by a cycle delay magnitude to generate a cycle delay signal and N...
US-7,274,221 Comparator circuit
An improved comparator circuit and associated methods are disclosed. In one embodiment, the comparator circuit comprises two voltage-to-time converter circuits,...
US-7,274,220 Method and apparatus for amplifying a regulated differential signal to a higher voltage
A sense amplifier for use in a memory device and in a memory-resident system. The sense amplifier operates on a lower voltage consistent with the voltage range...
US-7,274,205 System and method for testing devices utilizing capacitively coupled signaling
An apparatus and method for testing a semiconductor device in an AC test regime. The test apparatus includes a test plate capacitively couple to the signal...
US-7,274,204 System and method for testing devices utilizing capacitively coupled signaling
An apparatus and method for testing a semiconductor device in an AC test regime. The test apparatus includes a test plate capacitively couple to the signal...
US-7,274,201 Method and system for stressing semiconductor wafers during burn-in
A method and system for testing a plurality of semiconductor dice on a semiconductor wafer during burn-in includes forming a plurality of semiconductor dice with...
US-7,274,197 Contact system for interfacing a semiconductor wafer to an electrical tester
Disclosed herein are exemplary embodiments of a contact system (referred to as a "Z-block") for interfacing a semiconductor wafer to an electrical tester, and...
US-7,274,138 Spacers for field emission displays
The disclosed method for forming a field emission display includes forming a cathode and an anode, forming a plurality of photoresist posts over the cathode, and...
US-7,274,095 Interposers with receptacles for receiving semiconductor devices and assemblies and packages including such...
A semiconductor device package interposer including a receptacle extending substantially therethrough. Methods for assembling the interposer with one or more...
US-7,274,094 Leadless packaging for image sensor devices
A leadless image sensor package and methods for its assembly. In a first embodiment, an image sensor chip is mounted within a bottom-side cavity of a package...
US-7,274,086 Memory device power distribution in memory assemblies
Memory assemblies include memory chips having chip bond pads on both sides of the memory chip shorted to each other by a single lead of a leadframe. The memory...
US-7,274,076 Threshold voltage adjustment for long channel transistors
A threshold voltage adjusted long-channel transistor fabricated according to short-channel transistor processes is described. The threshold-adjusted transistor...
US-7,274,068 Ballistic direct injection NROM cell on strained silicon structures
A nitride read only memory cell comprising a silicon-germanium layer with a pair of source/drain regions. A strained silicon layer is formed overlying the...
US-7,274,067 Service programmable logic arrays with low tunnel barrier interpoly insulators
Structures and methods for in service programmable logic arrays with low tunnel barrier interpoly insulators are provided. The in-service programmable logic...
US-7,274,065 Source lines for NAND memory devices
A NAND memory device has a source line connected to two or more columns of serially-connected floating-gate transistors. The source line includes a first...
US-7,274,061 Capacitor constructions
The invention includes methods of forming rugged electrically conductive surfaces. In one method, a layer is formed across a substrate and subsequently at least...
US-7,274,059 Capacitor constructions
The invention includes methods of forming rugged electrically conductive surfaces. In one method, a layer is formed across a substrate and subsequently at least...
US-7,274,056 Semiconductor constructions
The invention includes a semiconductor construction having a pair of channel regions that have sub-regions doped with indium and surrounded by boron. A pair of...
US-7,274,054 Dual capacitor structure for imagers and method of formation
CMOS and CCD imaging devices comprising different in-pixel capacitors and peripheral capacitors and methods of formation are disclosed. The capacitors used in...
US-7,274,049 Semiconductor assemblies
The invention includes a semiconductor processing method wherein an insulative mass is formed across a first electrical node and a second electrical node. The...
US-7,274,034 Resistance variable memory device with sputtered metal-chalcogenide region and method of fabrication
A chalcogenide-based programmable conductor memory device and method of forming the device, wherein a chalcogenide glass region is provided with a plurality of...
US-7,273,817 Conditioning of a reaction chamber
A method is provided for forming polymer on an interior surface of a reaction chamber. A polymer-forming gas is introduced into the chamber during the etching of...
US-7,273,816 Methods for removal of organic materials
The invention includes methods of forming capacitor structures and removing organic material. An organic material, such as a photoresist, is disposed on a...
US-7,273,809 Method of fabricating a conductive path in a semiconductor device
A method for fabricating an ultra-small electrode or plug contact for use in chalcogenide memory cells specifically, and in semiconductor devices generally, in...
US-7,273,802 Methods for consolidating previously unconsolidated conductive material to form conductive structures or...
Methods for fabricating conductive structures on contact pads of semiconductor device components or other electronic components and for securing conductive...
US-7,273,797 Methods of forming semiconductor-on-insulator constructions
The invention encompasses a method of forming a semiconductor-on-insulator construction. A substrate is provided. The substrate includes a ...
US-7,273,796 Methods of forming trench isolation in the fabrication of integrated circuitry and methods of fabricating...
A method of fabricating integrated circuitry includes depositing a spin-on-dielectric over a semiconductor substrate. The spin-on-dielectric comprises a...
US-7,273,793 Methods of filling gaps using high density plasma chemical vapor deposition
The invention includes a method of filling gaps in a semiconductor substrate. A substrate and a gas mixture containing at least one heavy-hydrogen compound are...
US-7,273,791 Methods for forming a conductive structure using oxygen diffusion through one metal layer to oxidize a second...
A method for forming a metal/metal oxide structure that includes forming metal oxide regions, e.g. ruthenium oxide regions, at grain boundaries of a metal layer,...
US-7,273,788 Ultra-thin semiconductors bonded on glass substrates
A method for forming a semiconductor on insulator structure includes providing a glass substrate, providing a semiconductor wafer, and performing a bonding cut...
US-7,273,784 Scalable high density non-volatile memory cells in a contactless memory array
A plurality of split gate non-volatile memory cells are formed vertically in a trench along the sidewalls. Each cell is comprised of a bistable element and an...
US-7,273,779 Method of forming a double-sided capacitor
A method of forming a double-sided capacitor using at least one sacrificial structure, such as a sacrificial liner or a sacrificial plug. A sacrificial liner is...
US-7,273,778 Method of electroplating a substance over a semiconductor substrate
The invention includes methods of electrochemically treating semiconductor substrates. The invention includes a method of electroplating a substance. A substrate...
US-7,273,769 Method and apparatus for removing encapsulating material from a packaged microelectronic device
A method and apparatus for encapsulating microelectronic devices. In one embodiment, the method includes removing a portion of encapsulating material that at...
US-7,273,684 Mask having transmissive elements and a common sidelobe inhibitor for sidelobe suppression in radiated patterning
A mask having transmissive elements and one or more sidelobe inhibitors for sidelobe suppression during a radiation-patterning process is provided. Sidelobe...
US-7,273,660 Mixed composition interface layer and method of forming
An interface forming method includes forming a first layer containing a first chemical element and chemisorbing on the first layer an interface layer containing...
US-7,273,566 Gas compositions
Processes, etchants, and apparatus useful for etching an insulating oxide layer of a substrate without damaging underlying nitride features or field oxide...
US-7,273,525 Methods for forming phosphorus- and/or boron-containing silica layers on substrates
A method of forming a phosphorus- and/or boron-containing silica layer, such as a PSG, BSG, or BPSG layer, on a substrate, such as a semiconductor substrate or...
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