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| Patent # | Description |
|---|---|
| US-7,273,411 |
Polishing apparatus A chemical-mechanical polishing apparatus is provided with a downstream device for conditioning a web-shaped polishing pad. The device may be used to condition a... |
| US-7,272,758 |
Defective memory block identification in a memory device During manufacture and testing of a memory device, a memory test is performed to determine which, if any, memory blocks are defective. A memory map of the... |
| US-7,272,747 |
Use of non-volatile memory to perform rollback function A mechanism and method for maintaining a consistent state in a non-volatile random access memory system without constraining normal computer operation is... |
| US-7,272,742 |
Method and apparatus for improving output skew for synchronous integrated
circuits A method and apparatus for improving output skew across the data bus of a synchronous integrated circuit device. The device includes a clock input buffer that... |
| US-7,272,709 |
Using chip select to specify boot memory A synchronous Flash memory device is described that enhances initialization and boot memory device identification in synchronous memory systems. A boot memory is... |
| US-7,272,703 |
Program controlled embedded-DRAM-DSP architecture and methods An efficient embedded-DRAM processor architecture and associated methods. In one exemplary embodiment, the architecture includes a DRAM array, a set of register... |
| US-7,272,697 |
Systems and methods for managing data stored in a multi-drive storage
device A virtual mass storage device implements a data manager for storing information on multiple physical mass storage devices. The virtual mass storage device is... |
| US-7,272,696 |
Dynamic volume management A method for managing a range of memory in a flash memory space in which a plurality of data objects are stored. A volume defined for the range of memory has a... |
| US-7,272,694 |
Chip protection register lock circuit in a flash memory device A chip protection register lock circuit uses a plurality of lock bits in a lock bit register. If the register contains N bits, N/2 bits of the register are... |
| US-7,272,683 |
Memory device controller A controller for a memory device and methods are provided. The controller has an updateable register bank adapted to send a first signal to an analog/memory core... |
| US-7,272,678 |
DSP bus monitoring apparatus and method A bus monitor is provided as a tool for developing, debugging and testing a system having an embedded processor. The bus monitor resides within the same chip or... |
| US-7,272,066 |
Method and system for controlling refresh to avoid memory cell data losses A DRAM includes a register storing subsets of row addresses corresponding to rows containing at least one memory cell that is unable to store a data bit during a... |
| US-7,272,054 |
Time domain bridging circuitry for use in determining output enable timing A method and circuitry for alleviating the adverse effect of variable read decode propagation delays and variable output circuitry propagation delays on the read... |
| US-7,272,046 |
High voltage switching circuit A high voltage switching circuit that has a depletion mode NMOS transistor, an enhancement mode PMOS transistor and an, enhancement mode NMOS transistor. A... |
| US-7,272,045 |
Method for programming and erasing an NROM cell A nitride read only memory (NROM) cell can be programmed by applying a ramp voltage to the gate input, a constant voltage to one of the two source/drain regions,... |
| US-7,272,044 |
Flash memory Flash memory supporting methods for erasing memory cells using a decrease in magnitude of a source voltage of a first polarity to increase the magnitude of a... |
| US-7,272,039 |
Minimizing adjacent wordline disturb in a memory device A selected wordline that is coupled to cells for programming is biased with a programming voltage. The unselected wordlines that are adjacent to the selected... |
| US-7,271,654 |
Low voltage CMOS differential amplifier A low voltage CMOS differential amplifier is provided. More specifically, in one embodiment, there is provided a method of manufacturing a device comprising... |
| US-7,271,635 |
Method and apparatus for reducing duty cycle distortion of an output
signal A method and apparatus for reducing the duty cycle distortion of a periodic signal in high speed devices. More specifically, there is provided a device having a... |
| US-7,271,628 |
Reduced current input buffer circuit There is provided a reduced current input buffer circuit. More specifically, in one embodiment, there is provided an input buffer circuit comprising an input... |
| US-7,271,620 |
Variable impedance output buffer An output buffer for a semiconductor memory device and other semiconductor devices includes a feedback circuit to dynamically control the output impedance of the... |
| US-7,271,611 |
Method for testing semiconductor components using bonded electrical
connections A method for testing a semiconductor component includes the steps of bonding an interconnect to the component to form bonded electrical connections, applying... |
| US-7,271,581 |
Integrated circuit characterization printed circuit board, test equipment
including same, method of fabrication... An integrated circuit characterization printed circuit board and method is provided for improving the uniformity of impedance introduced by a test fixture across... |
| US-7,271,528 |
Uniform emitter array for display devices An emitter array produced using etch mask and a method for making such an etch mask. The emitter comprises a substrate, forming a conducting layer on the... |
| US-7,271,491 |
Carrier for wafer-scale package and wafer-scale package including the
carrier A carrier for use in a chip-scale package, including a semiconductor substrate, such as a semiconductor wafer, with a plurality of apertures formed therethrough.... |
| US-7,271,482 |
Methods for forming interconnects in microelectronic workpieces and
microelectronic workpieces formed using... Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces having such interconnects are disclosed herein. One aspect of the... |
| US-7,271,467 |
Multiple oxide thicknesses for merged memory and logic applications Structures are provided for multiple oxide thicknesses on a single silicon wafer. In particular, structures are provided for multiple gate oxide thicknesses on a... |
| US-7,271,464 |
Liner for shallow trench isolation A method of depositing dielectric material into sub-micron spaces and resultant structures is provided. After a trench is etched in the surface of a wafer, a... |
| US-7,271,463 |
Trench insulation structures including an oxide liner that is thinner
along the walls of the trench than along... A method of depositing dielectric material into sub-micron spaces and resultant structures is provided. After a trench is etched in the surface of a wafer, a... |
| US-7,271,445 |
Ultra-thin semiconductors bonded on glass substrates A method for forming a semiconductor on insulator structure includes providing a glass substrate, providing a semiconductor wafer, and performing a bonding cut... |
| US-7,271,440 |
Method and apparatus for forming an integrated circuit electrode having a
reduced contact area A method and an apparatus for manufacturing a memory cell having a non-volatile resistive memory element with a limited size active area. The method comprises a... |
| US-7,271,438 |
Self-aligned silicide for word lines and contacts An embodiment of a floating-gate memory cell has a tunnel dielectric layer formed overlying a semiconductor substrate; a drain region formed in a semiconductor... |
| US-7,271,437 |
Non-volatile memory with hole trapping barrier A non-volatile memory is described having memory cells with a gate dielectric. The gate dielectric is a multilayer charge trapping dielectric between a control... |
| US-7,271,435 |
Modified source/drain re-oxidation method and system Methods and devices are disclosed utilizing a phosphorous-doped oxide layer that is added prior to re-oxidation. This allows greater control of the re-oxidation... |
| US-7,271,433 |
High-density single transistor vertical memory gain cell A memory cell which is formed on a substrate of a first conductivity type. A pillar of the first conductivity type extends vertically upward from the substrate.... |
| US-7,271,413 |
Semiconductor constructions The invention includes semiconductor constructions containing vertically-extending pillars, and methods for forming such constructions. The vertically-extending... |
| US-7,271,407 |
Switchable circuit assemblies and semiconductor constructions The invention includes a switchable circuit device. The device comprises a first conductive layer and a porous silicon matrix over the first conductive layer. A... |
| US-7,271,106 |
Critical dimension control for integrated circuits Methods of etching substrates with small critical dimensions and altering the critical dimensions are disclosed. In one embodiment, a sulfur oxide based plasma... |
| US-7,271,096 |
Method for improved deposition of dielectric material A gas delivery device useful in material deposition processes executed during semiconductor device fabrication in a reaction chamber, including the gas delivery... |
| US-7,271,092 |
Boron incorporated diffusion barrier material A diffusion barrier layer comprising TiN.sub.xB.sub.y is disclosed for protection of gate oxide layers in integrated transistors. The diffusion barrier layer can... |
| US-7,271,089 |
Barrier layer, IC via, and IC line forming methods A barrier layer forming method includes providing a porous dielectric layer over a substrate, the dielectric layer having a surface with exposed pores, and... |
| US-7,271,086 |
Microfeature workpieces and methods of forming a redistribution layer on
microfeature workpieces Methods for forming a redistribution layer on microfeature workpieces, and microfeature workpieces having such a redistribution layer are disclosed herein. In... |
| US-7,271,085 |
Method of fabricating a semiconductor interconnect structure A method of fabricating a semiconductor interconnect structure is disclosed. The method includes forming a first metal plug in a first opening defined by a first... |
| US-7,271,077 |
Deposition methods with time spaced and time abutting precursor pulses An atomic layer deposition method includes positioning a semiconductor substrate within an atomic layer deposition chamber. A first precursor gas is flowed to... |
| US-7,271,072 |
Stud electrode and process for making same A process of making a stud capacitor structure is disclosed. The process includes embedding the stud in a dielectric stack. In one embodiment, the process... |
| US-7,271,071 |
Method of forming a catalytic surface comprising at least one of Pt, Pd,
Co and Au in at least one of elemental... The invention includes methods of forming a substrate having a surface comprising at least one of Pt, Pd, Co and Au in at least one of elemental and alloy forms.... |
| US-7,271,065 |
Horizontal memory devices with vertical gates Structures and methods for memory devices are provided which operate with lower control gate voltages than conventional floating gate transistors, and which do... |
| US-7,271,064 |
Method of forming a field effect transistor using conductive masking
material The invention includes methods of forming field effect transistors. In one implementation, a method of forming a field effect transistor having a gate comprising... |
| US-7,271,060 |
Semiconductor processing methods The invention includes methods in which common processing steps are utilized during fabrication of components of a memory array region of a semiconductor... |
| US-7,271,057 |
Memory array with overlapping buried digit line and active area and method
for forming same A memory cell, array and device include an active area formed in a substrate with a vertical transistor including a first end disposed over a first portion of... |
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