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| Patent # | Description |
|---|---|
| US-7,303,404 |
Contact and electrical connecting apparatus A contact includes: a first and a second conductive contact pieces and at least one sheet-like electrical insulator such as polyimide. Each contact piece has a... |
| US-7,302,519 |
Distributed content addressable memory The present invention provides a large capacity distributed content addressable memory (CAM) made up of a plurality of smaller CAMs interconnected on a high... |
| US-7,302,111 |
Graphics engine for high precision lithography The present invention includes a method to use a phase modulating micromirror array to create an intensity image that has high image fidelity, good stability... |
| US-7,301,221 |
Controlling diffusion in doped semiconductor regions A method and device for reducing a dopant diffusion rate in a doped semiconductor region is provided. The methods and devices include selecting a plurality of... |
| US-7,301,190 |
Structures and methods to enhance copper metallization Disclosed structures and methods inhibit atomic migration and related capacitive-resistive effects between a metallization layer and an insulator layer in a... |
| US-7,300,873 |
Systems and methods for forming metal-containing layers using vapor
deposition processes A method of forming (and an apparatus for forming) a metal containing layer on a substrate, particularly a semiconductor substrate or substrate assembly for use... |
| US-7,300,870 |
Systems and methods of forming refractory metal nitride layers using
organic amines A method of forming (and apparatus for forming) refractory metal nitride layers (including silicon nitride layers), such as a tantalum nitride barrier layer, on... |
| US-7,300,857 |
Through-wafer interconnects for photoimager and memory wafers A through-wafer interconnect for imager, memory and other integrated circuit applications is disclosed, thereby eliminating the need for wire bonding, making... |
| US-7,300,839 |
Selective polysilicon stud growth A memory cell having a bit line contact is provided. The memory cell may be a 6F.sup.2 memory cell. The bit line contact may have a contact hole bounded by... |
| US-7,300,821 |
Integrated circuit cooling and insulating device and method A method and device for cooling an integrated circuit is provided. A method and device using a gas to cool circuit structures such as a number of air bridge... |
| US-7,300,526 |
Method and system for removal of contaminates from phaseshift photomasks A system and method to clean the pellicle frame and adhesive ring of a photomask reticle are described. One embodiment includes a cover that isolates the... |
| US-7,299,381 |
Discrete tests for weak bits A testing method for semiconductor memory that selects memory cells adjacent to the periphery of the memory array and to a memory twist. These memory cells are... |
| US-7,299,329 |
Dual edge command in DRAM A technique to increase transfer rate of command and address signals via a given number of command and address pins in each of one or more integrated circuit... |
| US-7,298,638 |
Operating an electronic device having a vertical gain cell that includes
vertical MOS transistors A high density vertical gain cell is realized for memory operation. The gain cell includes a vertical MOS transistor used as a sense transistor having a floating... |
| US-7,298,453 |
Method and apparatus for irradiating a microlithographic substrate A method and apparatus for exposing a radiation-sensitive material of a microlithographic substrate to a selected radiation. The method can include directing the... |
| US-7,298,425 |
Method for assisting video compression in a computer system One embodiment of the present invention provides a method that facilitates compression of video data in a computer system by performing the time-consuming task... |
| US-7,298,406 |
Ground referenced pixel reset A ground referenced pixel reset circuit is disclosed. The ground referenced pixel reset circuit supplies a pixel with a reset signal such that when the reset... |
| US-7,298,401 |
Method and apparatus for removing flicker from images Method and apparatus for removing image artifacts from an image of a scene illuminated by a periodically varying light source such as a fluorescent light source.... |
| US-7,298,031 |
Multiple substrate microelectronic devices and methods of manufacture A microelectronic device and method for manufacture. In one embodiment, two microelectronic substrates are directly bonded to each other without an intermediate... |
| US-7,298,025 |
Microelectronic component assemblies and microelectronic component lead
frame structures The present invention provides microelectronic component assemblies and lead frame structures that may be useful in such assemblies. For example, one such lead... |
| US-7,298,024 |
Transparent amorphous carbon structure in semiconductor devices A transparent amorphous carbon layer is formed. The transparent amorphous carbon layer has a low absorption coefficient such that the amorphous carbon is... |
| US-7,298,000 |
Conductive container structures having a dielectric cap Container structures for use in integrated circuits and methods of their manufacture. The container structures have a dielectric cap on the top of a conductive... |
| US-7,297,995 |
Transparent metal shielded isolation for image sensors An isolation region formed in a substrate and lined with a transparent metal layer. The isolation region provides isolation between adjacent active areas of an... |
| US-7,297,917 |
Readout technique for increasing or maintaining dynamic range in image
sensors The apparatus and method provide a readout technique and circuit for increasing or maintaining dynamic range of an image sensor. The readout technique and... |
| US-7,297,915 |
Compensation methods and systems for imaging detectors Imaging arrays typically include thousands or millions of photodetectors that convert sensed light into corresponding electric signals, which are ultimately... |
| US-7,297,639 |
Methods for etching doped oxides in the manufacture of microfeature
devices Methods for selectively etching doped oxides in the manufacture of microfeature devices are disclosed herein. An embodiment of one such method for etching... |
| US-7,297,637 |
Use of pulsed grounding source in a plasma reactor A method for grounding a semiconductor substrate pedestal during a portion of a high voltage power bias oscillation cycle to reduce or eliminate the detrimental... |
| US-7,297,623 |
Etch stop layer in poly-metal structures In accordance with one embodiment of the present invention, a method of interfacing a poly-metal structure and a semiconductor substrate is provided where an... |
| US-7,297,617 |
Method for controlling diffusion in semiconductor regions A method and device for reducing a dopant diffusion rate in a doped semiconductor region is provided. The methods and devices include selecting a plurality of... |
| US-7,297,563 |
Method of making contact pin card system A compliant contact pin contactor card method for making is provided. The compliant contact pin assembly includes a contact pin formed from a portion of a... |
| US-7,297,412 |
Fabrication of stacked microelectronic devices Manufacture of stacked microelectronic devices is facilitated by producing subassemblies wherein adhesive pads are applied to the back surfaces of a plurality of... |
| US-7,296,346 |
Plating buss and a method of use thereof The present invention relates generally to a plating buss design and method for minimizing short circuit problems in PCB panel singulation. More particularly,... |
| US-7,295,462 |
Method and apparatus processing variable resistance memory cell write
operation A circuit and method for writing to a variable resistance memory cell. The circuit includes a variable resistance memory cell, a switchable current blocking... |
| US-7,295,081 |
Time delay oscillator for integrated circuits One aspect relates to an oscillator, and various oscillator embodiments comprise an amplifier and line driver with an input and an output and a transmission line... |
| US-7,294,921 |
System-on-a-chip with multi-layered metallized through-hole
interconnection The present invention is directed to a high-performance system on a chip which uses multi-layer wiring/insulation through-hole interconnections to provide short... |
| US-7,294,911 |
Ultrathin leadframe BGA circuit package A circuit package is formed using a leadframe. The leadframe is formed or etched to align a plurality of bond pad structures above a reference plane while... |
| US-7,294,903 |
Transistor assemblies Semiconductor processing methods of forming transistors, semiconductor processing methods of forming dynamic random access memory circuitry, and related... |
| US-7,294,897 |
Packaged microelectronic imagers and methods of packaging microelectronic
imagers Microelectronic imagers, methods for packaging microelectronic imagers, and methods for forming electrically conductive through-wafer interconnects in... |
| US-7,294,893 |
Titanium silicide boride gate electrode A method for use in the fabrication of a gate electrode includes providing a gate oxide layer and forming a titanium boride layer on the oxide layer. An... |
| US-7,294,790 |
Apparatus for measuring parasitic capacitance and inductance of I/O leads
on an electrical component using a... Apparatus is provided for measuring the potential for mutual coupling in an integrated circuit package of any type or configuration using a network analyzer in... |
| US-7,294,578 |
Use of a plasma source to form a layer during the formation of a
semiconductor device A method used to form a semiconductor device having a capacitor comprises placing a semiconductor wafer assembly into a chamber of a plasma source, the wafer... |
| US-7,294,570 |
Contact integration method A method of making a contact plug and a metallization line structure is disclosed in which a substrate is provided with at least one contact hole within an... |
| US-7,294,567 |
Semiconductor contact device and method The invention provides an advanced metallization technique for fabricating a memory cell array on a substrate. The array is fabricated by forming discrete and... |
| US-7,294,556 |
Method of forming trench isolation in the fabrication of integrated
circuitry This invention includes methods of forming a phosphorus doped silicon dioxide comprising layers, and methods of forming trench isolation in the fabrication of... |
| US-7,294,549 |
Vertical floating gate transistor A floating gate transistor has been described that includes source and drain regions that are fabricated on different horizontal planes. A floating gate and a... |
| US-7,294,545 |
Selective polysilicon stud growth A memory cell having a bit line contact is provided. The memory cell may be a 6F.sup.2 memory cell. The bit line contact may have a contact hole bounded by... |
| US-7,294,527 |
Method of forming a memory cell The invention relates to the fabrication of a resistance variable material cell or programmable metallization cell. The processes described herein can form a... |
| US-7,294,049 |
Method and apparatus for removing material from microfeature workpieces Methods and apparatus for removing materials from microfeature workpieces. One embodiment of a subpad in accordance with the invention comprises a matrix having... |
| US-7,294,040 |
Method and apparatus for supporting a microelectronic substrate relative
to a planarization pad A method and apparatus for planarizing a microelectronic substrate. In one embodiment, one surface of the microelectronic substrate is engaged with a planarizing... |
| US-7,293,526 |
Plasma reaction chamber liner consisting essentially of osmium The invention encompasses a method of enhancing selectivity of etching silicon dioxide relative to one or more organic substances. A material comprising one or... |
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