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| Patent # | Description |
|---|---|
| US-7,353,281 |
Method and system for providing access to computer resources A method and computer system for providing access to computer resources on a computer system and includes generating a token containing encrypted user... |
| US-7,352,892 |
System and method for shape reconstruction from optical images Reconstructing the shape of the surface of an object in greater than two dimensions is performed using a noise-tolerant reconstruction process and/or a... |
| US-7,352,649 |
High speed array pipeline architecture A memory device including a memory array having a plurality of memory cells, and a plurality of peripheral devices for reading data out of and writing data into... |
| US-7,352,643 |
Regulating voltages for refresh operation using flash trim bits in
semiconductor memory devices A method and apparatus for regulating voltages in semiconductor devices. Trim bits are stored in a trim flash array, where the trim bits define a voltage value... |
| US-7,352,624 |
Reduction of adjacent floating gate data pattern sensitivity The method for programming non-volatile memory cells erases the memory cells to be programmed. The memory cells are then programmed to a reduced floating gate... |
| US-7,352,603 |
Apparatus and methods for optically-coupled memory systems Optically-coupled memory systems are disclosed. In one embodiment, a system memory includes a carrier substrate, and a controller attached to the carrier... |
| US-7,352,602 |
Configurable inputs and outputs for memory stacking system and method Embodiments of the present invention relate to configurable inputs and/or outputs for memory and memory stacking applications. More specifically, embodiments of... |
| US-7,352,511 |
Micro-lenses for imagers A micro-lens and a method for forming the micro-lens is provided. A micro-lens includes a substrate and lens material located within the substrate, the substrate... |
| US-7,352,201 |
System and method for testing devices utilizing capacitively coupled
signaling An apparatus and method for testing a semiconductor device in an AC test regime. The test apparatus includes a test plate capacitively couple to the signal... |
| US-7,352,023 |
Constructions comprising hafnium oxide The invention includes methods of forming hafnium-containing materials, such as, for example, hafnium oxide. In one aspect, a semiconductor substrate is... |
| US-7,352,019 |
Capacitance reduction by tunnel formation for use with a semiconductor
device A method used during the manufacture of a semiconductor device comprises providing at least first, second, and third spaced conductive structures, where the... |
| US-7,352,007 |
Phosphorescent nanotube memory device An optical memory cell having a material layer associated with a pixel capable of emitting and receiving light. The material layer has phosphorescent material... |
| US-7,351,945 |
Alignment among elements in an image sensor An image sensor is formed with shifts among the optical parts of the sensor and the photosensitive parts of the sensor. The optical parts of the sensor may... |
| US-7,351,659 |
Methods of forming a transistor with an integrated metal silicide gate
electrode Methods of forming a transistor having integrated metal silicide transistor gate electrode on a semiconductor assembly are described. The transistor gate is... |
| US-7,351,640 |
Methods of fabricating double-sided hemispherical silicon grain electrodes
and capacitor modules Methods are provided for robust and cost effective techniques to fabricate a semiconductor device having double-sided hemispherical silicon grain (HSG)... |
| US-7,351,628 |
Atomic layer deposition of CMOS gates with variable work functions Structures, systems and methods for transistors having gates with variable work functions formed by atomic layer deposition are provided. One transistor... |
| US-7,351,620 |
Methods of forming semiconductor constructions The invention includes BIFETRAM devices. Such devices comprise a bipolar transistor in combination with a field effect transistor (FET) in a three-dimensional... |
| US-7,350,182 |
Methods of forming patterned reticles The invention includes methods of forming patterned reticles. Design features can be introduced into a layout for a reticle prior to optical proximity... |
| US-7,350,093 |
Apparatus and method for generating a delayed clock signal An apparatus and method for generating a delayed clock signal is provided. The clock signal generator includes a synchronizing circuit for generating an output... |
| US-7,350,044 |
Data move method and apparatus An improved Flash memory device, control circuit, or data handling methods is described that facilitate the moving and consolidating data in split and non-split... |
| US-7,350,018 |
Method and system for using dynamic random access memory as cache memory A cache memory system and method includes a DRAM having a plurality of banks, and it also includes 2 SRAMs each having a capacity that is equal to the capacity... |
| US-7,349,277 |
Method and system for reducing the peak current in refreshing dynamic
random access memory devices A dynamic random access memory device includes a mode register that is programmed with a delay value. In some embodiments, a offset code is also stored in the... |
| US-7,349,273 |
Access circuit and method for allowing external test voltage to be applied
to isolated wells An access circuit selectively couples an externally accessible terminal to each of a plurality of isolated DRAM wells in which respective DRAM arrays are... |
| US-7,349,270 |
Semiconductor memory with wordline timing A semiconductor memory with wordline timing, which links activating a wordline to an isolation signal. The isolation signal is applied to a memory section... |
| US-7,349,269 |
Programmable DQS preamble A method and apparatus for programming a data strobe (DQS) preamble in a memory by loading a defined set of bits into one or more registers of the memory, where... |
| US-7,349,252 |
Integrated DRAM-NVRAM multi-level memory An integrated DRAM-NVRAM, multi-level memory cell is comprised of a vertical DRAM device with a shared vertical gate floating plate device. The floating plate... |
| US-7,349,232 |
6F.sup.2 DRAM cell design with 3F-pitch folded digitline sense amplifier The present invention is generally directed to a DRAM cell design with folded digitline sense amplifier. In one illustrative embodiment, a memory array having a... |
| US-7,348,674 |
Low capacitance wiring layout Integrated circuits having multi-level wiring layouts designed to inhibit the capacitive-resistance effect, and a method for fabricating such integrated... |
| US-7,348,671 |
Vias having varying diameters and fills for use with a semiconductor
device and methods of forming... A method for forming electrical interconnects having different diameters and filler materials through a semiconductor wafer comprises forming first and second... |
| US-7,348,652 |
Bulk-isolated PN diode and method of forming a bulk-isolated PN diode A technique for making a bulk isolated PN diode. Specifically, a technique is provided for making a voltage clamp with a pair of bulk isolated PN diode. Another... |
| US-7,348,613 |
CMOS imager with selectively silicided gates The invention also relates to an apparatus and method for selectively providing a silicide coating over the transistor gates of a CMOS imager to improve the... |
| US-7,348,238 |
Bottom electrode for memory device and method of forming the same Contacts having use in an integrated circuit and exemplary methods of forming the contacts are disclosed. The methods involve forming a conductive cap over a... |
| US-7,348,237 |
NOR flash memory cell with high storage density Structures and methods for NOR flash memory cells, arrays and systems are provided. The NOR flash memory cell includes a vertical floating gate transistor... |
| US-7,348,236 |
Formation of memory cells and select gates of NAND memory arrays Apparatus and methods are provided. Floating-gate memory cells and select gates of NAND memory arrays are formed concurrently by anisotropically removing... |
| US-7,348,234 |
Methods of forming capacitor constructions The invention includes methods of electrochemically treating semiconductor substrates. The invention includes a method of electroplating a substance. A substrate... |
| US-7,348,215 |
Methods for assembly and packaging of flip chip configured dice with
interposer A method for assembly and packaging of one or more flip chip-configured semiconductor dice with an interposer substrate to form a flip chip-type semiconductor... |
| US-7,348,213 |
Method for forming component mounting hole in semiconductor substrate The present invention provides to a substrate for a semiconductor device, in which electric characteristics to high-speed signals are enhanced by facilitating... |
| US-7,348,209 |
Resistance variable memory device and method of fabrication Methods and apparatus for providing a resistance variable memory device with agglomeration prevention and thermal stability. According to one embodiment, a... |
| US-7,348,205 |
Method of forming resistance variable devices A method of forming a resistance variable device includes forming a first conductive electrode material on a substrate. A metal doped chalcogenide comprising... |
| US-7,347,767 |
Retaining rings, and associated planarizing apparatuses, and related
methods for planarizing micro-device... Retaining rings and associated planarizing apparatuses, and related methods for planarizing micro-device workpieces are disclosed herein. A carrier head... |
| US-7,347,349 |
Apparatus and method for printing micro metal structures A method and device for printing liquid material such as liquid solder is provided. C4 structures as small as 10 microns in diameter can be produced using... |
| US-7,347,348 |
Apparatus and method for depositing and reflowing solder paste on a
microelectronic workpiece Stenciling machines and methods for forming solder balls on microelectronic workpieces are disclosed herein. In one embodiment, a method for depositing and... |
| US-7,346,818 |
Method and apparatus for redundant location addressing using data
compression A method and apparatus for identifying defective cells in a memory array includes receiving a request for accessing an address and analyzing the address to... |
| US-7,346,817 |
Method and apparatus for generating and detecting initialization patterns
for high speed DRAM systems A method and apparatus for determining the characteristics of a communications channel within a high speed memory system includes generating a first signal... |
| US-7,346,182 |
Electroacoustic transducer and method for manufacturing the same A diaphragm subassembly comprises a voice coil, a diaphragm, a frame, and a pair of terminal members. A magnetic circuit unit comprises a yoke, a magnet, and a... |
| US-7,346,162 |
Public key cryptography using matrices The invention provides techniques for secure messages transmission using a public key system to exchange secret keys. A first entity creates public and private... |
| US-7,345,937 |
Open digit line array architecture for a memory array A system and method for sensing a data state stored by a memory cell that includes coupling a first digit line and a second digit line to a precharge voltage and... |
| US-7,345,932 |
Low power dissipation voltage generator A voltage generator circuit is described for providing a regulated voltage, such as a negative word line voltage in a semiconductor memory. The generator uses a... |
| US-7,345,924 |
Programming memory devices A target memory cell of a memory device is programmed by applying a programming voltage to a word line that includes the target memory cell, determining whether... |
| US-7,345,922 |
Position based erase verification levels in a flash memory device The location of a cell to be erase verified is determined. The erase verification threshold voltage is then set. The threshold voltage is changed in response to... |
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