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| Patent # | Description |
|---|---|
| US-7,423,676 |
Asymmetric comparator for use in pixel oversaturation detection An imaging circuit using an asymmetric comparator to detect an oversaturated pixel is disclosed. The comparator employs a transistor differential pair which are... |
| US-7,423,476 |
Current mirror circuit having drain-source voltage clamp A circuit and method for providing an output current that includes biasing an output transistor in accordance with a reference current to conduct the output... |
| US-7,423,465 |
Duty cycle error calculation circuit for a clock generator having a delay
locked loop and duty cycle correction... A system and method for generating a correction signal for correcting duty cycle error of a first clock signal relative to a second complementary clock signal.... |
| US-7,423,463 |
Clock capture in clock synchronization circuitry Clock capturing synchronization circuitry first generates a synchronized clock signal from a reference clock signal, then captures the synchronized clock signal,... |
| US-7,423,462 |
Clock capture in clock synchronization circuitry Clock capturing synchronization circuitry first generates a synchronized clock signal from a reference clock signal, then captures the synchronized clock signal,... |
| US-7,423,456 |
Fast response time, low power phase detector circuits, devices and systems
incorporating the same, and... A circuit for quickly accomplishing highly accurate phase detection using low power is described. The circuit includes a phase decision circuit that receives two... |
| US-7,423,345 |
Semiconductor constructions comprising a layer of metal over a substrate The invention includes a method of forming a metal-containing film over a surface of a semiconductor substrate. The surface is exposed to a supercritical fluid.... |
| US-7,423,338 |
Methods for stacking wire-bonded integrated circuit dice on flip-chip
bonded integrated circuit dice An inventive electronic device, such as a multi-chip module (MCM), a Single In-line Memory Module (SIMM), or a Dual In-line Memory Module (DIMM), includes a... |
| US-7,423,336 |
Bond pad rerouting element, rerouted semiconductor devices including the
rerouting element, and assemblies... A rerouting element for a semiconductor device that includes a dielectric film that carries conductive vias, conductive elements, and contact pads. The... |
| US-7,423,331 |
Molded stiffener for thin substrates A stiffener molded to a semiconductor substrate, such as a lead frame, and methods of molding the stiffener to the substrate are provided. The stiffener is... |
| US-7,423,311 |
Atomic layer deposition of Zr.sub.3N.sub.4/ZrO.sub.2 films as gate
dielectrics The use of atomic layer deposition (ALD) to form a dielectric layer of zirconium nitride (Zr.sub.3N.sub.4) and zirconium oxide (ZrO.sub.2) and a method of... |
| US-7,423,249 |
Layout technique for address signal lines in decoders including stitched
blocks A decoder block includes a number of generic blocks stitched together. The generic blocks have an address line layout that enables the decoders to be addressed... |
| US-7,422,986 |
Deposition methods utilizing microwave excitation The invention includes a deposition apparatus having a reaction chamber, and a microwave source external to the chamber. The microwave source is configured to... |
| US-7,422,978 |
Methods of manufacturing interposers with flexible solder pad elements Various embodiments of an interposer for mounting a semiconductor die, as well as methods for forming the interposer, are disclosed. The interposer includes... |
| US-7,422,966 |
Technique for passivation of germanium A method of passivating germanium that comprises providing a germanium material and carburizing the germanium material to form a germanium carbide layer. The... |
| US-7,422,960 |
Method of forming gate arrays on a partial SOI substrate The invention includes methods for utilizing partial silicon-on-insulator (SOI) technology in combination with fin field effect transistor (finFET) technology to... |
| US-7,422,948 |
Threshold voltage adjustment for long channel transistors A threshold voltage adjusted long-channel transistor fabricated according to short-channel transistor processes is described. The threshold-adjusted transistor... |
| US-7,422,927 |
Methods of forming a resistance variable element The invention includes methods of depositing silver onto a metal selenide-comprising surface, and methods of forming a resistance variable device. In one... |
| US-7,422,924 |
Image device and photodiode structure The invention provides a photodiode with an increased charge collection area, laterally spaced from an adjacent isolation region. Dopant ions of a first... |
| US-7,422,639 |
Method of reducing water spotting and oxide growth on a semiconductor
structure The present invention relates to a method of cleaning and drying a semiconductor structure in a modified conventional gas etch/rinse or dryer vessel. |
| US-7,422,635 |
Methods and apparatus for processing microfeature workpieces, e.g., for
depositing materials on microfeature... The present disclosure suggests several systems and methods for batch processing of microfeature workpieces, e.g., semiconductor wafers or the like. One... |
| US-RE40,490 |
Method and apparatus for programmable field emission display A method and apparatus for programmable field emission display comprising an array of cathodoluminescent elements. Each cathodoluminescent element in the array... |
| US-7,421,630 |
Apparatus and methods for testing memory devices Each match line of a memory device such as a content addressable memory (CAM) device and a related part of a priority encoder can be separately tested. In test... |
| US-7,421,607 |
Method and apparatus for providing symmetrical output data for a double
data rate DRAM An apparatus and method is disclosed to compensate for skew and asymmetry of a locally processed system clock used to synchronize an output signal, e.g., a data... |
| US-7,421,606 |
DLL phase detection using advanced phase equalization A system and method are disclosed to generate and terminate clock shift modes during initialization of a synchronous circuit (e.g., a delay-locked loop or DLL).... |
| US-7,421,121 |
Spectral normalization using illuminant exposure estimation After image capture, scene parameters are analyzed, e.g. lux, flicker, or world estimation. A best guess illuminant for the scene parameters is determined. At... |
| US-7,420,849 |
Memory device distributed controller system A memory device distributed controller circuit distributes memory control functions amongst a plurality of memory controllers. A master controller receives an... |
| US-7,420,361 |
Method for improving stability and lock time for synchronous circuits Delay-locked loops, signal locking methods and devices and systems incorporating delay-locked loops are described. A delay-locked loop includes a forward delay... |
| US-7,420,240 |
Method to remove an oxide seam along gate stack edge, when nitride space
formation begins with an oxide liner... An exposed top end of a vertical oxide spacer is removed, and a nitride layer is deposited in an amount sufficient to replace the removed portion prior to... |
| US-7,420,239 |
Dielectric layer forming method and devices formed therewith Embodiments in accordance with the present invention provide alternative materials, and methods of forming such materials, that are effective as dielectric... |
| US-7,420,238 |
Semiconductor constructions The invention includes semiconductor constructions, and also includes methods of forming pluralities of capacitor devices. An exemplary method of the invention... |
| US-7,420,233 |
Photodiode for improved transfer gate leakage An image sensing circuit and method is disclosed, wherein a photodiode is formed in a substrate through a series of angled implants. The photodiode is formed by... |
| US-7,420,154 |
Pixel circuit with non-destructive readout circuit and methods of
operation thereof A pixel cell allows both correlated double sampling (CDS) and automatic light control (ALC) operations through a non-destructive, parallel readout. An image... |
| US-7,419,913 |
Methods of forming openings into dielectric material This invention includes methods of forming openings into dielectric material. In one implementation, an opening is partially etched through dielectric material,... |
| US-7,419,895 |
NAND memory arrays Methods and apparatus are provided. A source slot and a drain contact region are formed at opposite ends of a NAND string disposed on a substrate of a NAND... |
| US-7,419,871 |
Methods of forming semiconductor constructions The invention includes a method in which a semiconductor substrate is provided to have a memory array region, and a peripheral region outward of the memory array... |
| US-7,419,865 |
Methods of forming memory circuitry The invention includes methods of forming memory circuitry. In one implementation, a semiconductor substrate includes a pair of word lines having a bit node... |
| US-7,419,854 |
Methods for packaging image sensitive electronic devices The invention provides methods for packaging for electronic devices that are light or other radiation-sensitive, such as image sensors including CCD or CMOS... |
| US-7,419,852 |
Low temperature methods of forming back side redistribution layers in
association with through wafer... Low temperature processed back side redistribution lines (RDLs) are disclosed. Low temperature processed back side RDLs may be electrically connected to the... |
| US-7,419,841 |
Microelectronic imagers and methods of packaging microelectronic imagers Microelectronic imagers and methods for packaging microelectronic imagers are disclosed herein. In one embodiment, a microelectronic imaging unit can include a... |
| US-7,419,768 |
Methods of fabricating integrated circuitry The invention includes methods of fabricating integrated circuitry and semiconductor processing polymer residue removing solutions. In one implementation, a... |
| US-7,419,638 |
Microfluidic devices for fluid manipulation and analysis The present invention relates to microfluidic devices and methods for manipulating and analyzing fluid samples. The disclosed microfluidic devices utilize a... |
| US-7,419,299 |
Methods of sensing temperature of an electronic device workpiece The present invention includes electronic device workpieces, methods of semiconductor processing and methods of sensing temperature of an electronic device... |
| US-7,418,526 |
Memory hub and method for providing memory sequencing hints A memory module includes a memory hub coupled to several memory devices. The memory hub is also coupled to receive a memory packet from a system controller... |
| US-7,418,161 |
Photonic crystal-based optical elements for integrated circuits and
methods therefor Exemplary embodiments of the invention provide photonic crystal-based optical elements for integrated circuits. A photonic crystal optical device comprises a... |
| US-7,418,071 |
Method and apparatus for generating a phase dependent control signal A phase detector generates a phase dependent control signal according to the phase relationship between a first and second clock signal. The phase detector... |
| US-7,417,916 |
Methods of reducing coupling noise between wordlines Memory devices configured to reduce coupling noise between adjacent wordlines in a memory array. More specifically, wordline drivers are interleaved such that... |
| US-7,417,901 |
Memory device having terminals for transferring multiple types of data A memory device includes a number of terminals for transferring input data and output data to and from a memory array. The memory device includes an auxiliary... |
| US-7,417,894 |
Single latch data circuit in a multiple level cell non-volatile memory
device A single latch circuit is coupled to each bit line in a multiple level cell memory device to handle reading multiple data bits. The circuit is comprised of a... |
| US-7,417,893 |
Integrated DRAM-NVRAM multi-level memory An integrated DRAM-NVRAM, multi-level memory cell is comprised of a vertical DRAM device with a shared vertical gate floating plate device. The floating plate... |
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