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| Patent # | Description |
|---|---|
| US-7,374,993 |
Methods of forming capacitors A method of forming a capacitor includes forming a first capacitor electrode over a semiconductor substrate. A capacitor dielectric region is formed onto the... |
| US-7,374,990 |
Vertical wrap-around-gate field-effect-transistor for high density, low
voltage logic and memory array A vertical transistor having a wrap-around-gate and a method of fabricating such a transistor. The wrap-around-gate (WAG) vertical transistors are fabricated by... |
| US-7,374,964 |
Atomic layer deposition of CeO.sub.2/Al.sub.2O.sub.3 films as gate
dielectrics The use of atomic layer deposition (ALD) to form a nanolaminate layered dielectric layer of cerium oxide and aluminum oxide acting as a single dielectric layer... |
| US-7,374,617 |
Atomic layer deposition methods and chemical vapor deposition methods The invention includes atomic layer deposition methods and chemical vapor deposition methods. In a particular aspect of the invention, a source of microwave... |
| US-7,374,476 |
Method and apparatus for forming a planarizing pad having a film and
texture elements for planarization of... A planarizing pad for planarizing a microelectronic substrate, and a method and apparatus for forming the planarizing pad. In one embodiment, planarizing pad... |
| US-7,374,174 |
Small electrode for resistance variable devices A memory element comprising first and second electrodes is provided. The first electrode is tapered such that a first end of the first electrode is larger than a... |
| US-7,373,645 |
Method for using extrema to load balance a loop of parallel processing
elements A method for balancing the load of a parallel processing system having a plurality of parallel processing elements arranged in a loop, each processing element... |
| US-7,373,575 |
Method and apparatus for generating expect data from a captured bit
pattern, and memory device using same Expect data signals are generated for a series of applied data signals having a known sequence to determine if groups of the data signals were properly captured.... |
| US-7,373,005 |
Compression system for integrated sensor devices An imaging system incorporating adaptive compression which includes determining linear predictive differential residuals from an imager array pixel row. The... |
| US-7,372,768 |
Memory with address management The present invention allows for the reduction in power consumption of memory devices. A memory device in one embodiment prohibits address signal propagation on... |
| US-7,372,756 |
Non-skipping auto-refresh in a DRAM In a dynamic random access memory device, an auto-refresh method comprises receiving a command for the memory device to operate in a half-density mode. This... |
| US-7,372,751 |
Using redundant memory for extra features Apparatus and methods are provided. A memory device has a memory array comprising primary and redundant portions. A redundancy circuit is coupled to the memory... |
| US-7,372,746 |
Low voltage sensing scheme having reduced active power down standby
current A low voltage sensing scheme reduces active power down standby leakage current in a memory device. During memory's active power down state, the leak current may... |
| US-7,372,742 |
Memory block erasing in a flash memory device The erase and verify method performs an erase operation and an erase verify read operation. If the erase verify read operation fails because unerased memory... |
| US-7,372,739 |
High voltage generation and regulation circuit in a memory device An auxiliary voltage generation circuit is part of a high voltage generation and regulation circuit. The auxiliary voltage generation circuit generates an... |
| US-7,372,729 |
High speed low voltage driver A high speed high and low voltage driver provides an output voltage without taxing a pumped voltage. The pumped voltage is used only when the output node has... |
| US-7,372,723 |
State save-on-power-down using GMR non-volatile elements The semiconductor industry seeks to reduce the risk of traditional volatile storage devices with improved non-volatile storage devices. The increased demand for... |
| US-7,372,717 |
Methods for resistive memory element sensing using averaging A system for determining the logic state of a resistive memory cell element, for example an MRAM resistive cell element. The system includes a controlled voltage... |
| US-7,372,715 |
Architecture and method for NAND flash memory A NAND memory architecture arranges all even bitlines of a page together, and arranges all odd bitlines of a page together, so that programming operations are... |
| US-7,372,495 |
CMOS aps with stacked avalanche multiplication layer and low voltage
readout electronics An image sensor includes a pixel having a protection circuit connected to a charge multiplying photoconversion layer. The protection circuit prevents the pixel... |
| US-7,372,493 |
Column-wise clamp voltage driver for suppression of noise in an imager An imager having column-wise clamp voltage drivers. Each clamp voltage driver is substantially identical to the output circuitry of the imager's pixels in that... |
| US-7,372,490 |
Multi junction APS with dual simultaneous integration A new kind of pixel is formed of two floating diffusions of different sizes and different conductivity type. The two floating diffusions have different image... |
| US-7,372,484 |
Method and apparatus for reducing effects of dark current and defective
pixels in an imaging device A method and apparatus for identifying and compensating for the effects of defective pixels in high resolution digital cameras having image processing apparatus.... |
| US-7,372,358 |
Portable computer supporting paging instructions A portable computer is described that contains a circuit for receiving pages and performing security functions based on the received page. Once a page has been... |
| US-7,372,310 |
Digital frequency-multiplying DLLs Digital delay-locked loops (DLLs) and methods are provided for signal frequency multiplication. Analog delay elements of typical frequency-multiplying DLLs are... |
| US-7,372,138 |
Routing element for use in multi-chip modules, multi-chip modules
including the routing element and methods A routing element for use in a semiconductor device assembly includes a substrate that carries conductive traces that provide either additional electrical paths... |
| US-7,372,131 |
Routing element for use in semiconductor device assemblies A routing element for use in a semiconductor device assembly includes a substrate that carries conductive traces that provide either additional electrical paths... |
| US-7,372,129 |
Two die semiconductor assembly and system including same A semiconductor die assembly includes a substantially planar lead frame including a die paddle and a plurality of lead fingers, a first semiconductor die secured... |
| US-7,372,098 |
Low power flash memory devices A buried bipolar junction is provided in a floating gate transistor flash memory device. During a write operation electrons are injected into a surface depletion... |
| US-7,372,097 |
Programmable array logic or memory with p-channel devices and asymmetrical
tunnel barriers Structures and methods for programmable array type logic and/or memory with p-channel devices and asymmetrical low tunnel barrier intergate insulators are... |
| US-7,372,096 |
Programmable array logic or memory with p-channel devices and asymmetrical
tunnel barriers Structures and methods for programmable array type logic and/or memory with p-channel devices and asymmetrical low tunnel barrier intergate insulators are... |
| US-7,372,094 |
Semiconductor constructions The invention includes a method of depositing a noble metal. A substrate is provided. The substrate has a first region and a second region. The first and second... |
| US-7,372,092 |
Memory cell, device, and system A memory cell, device, and system include a memory cell having a shared digitline, a storage capacitor, and a plurality of access transistors configured to... |
| US-7,372,091 |
Selective epitaxy vertical integrated circuit components Integrated circuit components are described that are formed using selective epitaxy such that the integrated circuit components, such as transistors, are... |
| US-7,371,697 |
Ion-assisted oxidation methods and the resulting structures Oxidation methods and resulting structures including providing an oxide layer on a substrate and then re-oxidizing the oxide layer by vertical ion bombardment of... |
| US-7,371,676 |
Method for fabricating semiconductor components with through wire
interconnects A method for fabricating a semiconductor component with a through wire interconnect includes the step of providing a substrate having a circuit side, a back... |
| US-7,371,647 |
Methods of forming transistors The invention encompasses a method of forming a structure over a semiconductor substrate. A silicon dioxide containing layer is formed across at least some of... |
| US-7,371,642 |
Multi-state NROM device An array of NROM flash memory cells configured to store at least two bits per four F.sup.2. Split vertical channels are generated along each side of adjacent... |
| US-7,371,627 |
Memory array with ultra-thin etched pillar surround gate access
transistors and buried data/bit lines A memory array with data/bit lines extending generally in a first direction formed in an upper surface of a substrate and access transistors extending generally... |
| US-7,371,612 |
Method of fabrication of stacked semiconductor devices A method for increasing integrated circuit density is disclosed comprising stacking an upper wafer and a lower wafer, each of which having fabricated circuitry... |
| US-7,371,608 |
Method of fabricating a stacked die having a recess in a die BGA package Semiconductor devices and stacked die assemblies, and methods of fabricating the devices and assemblies for increasing semiconductor device density are provided. |
| US-7,371,587 |
Method for reducing diffusion through ferromagnetic materials A method and apparatus are disclosed for inhibiting diffusion of mobile atoms from an antiferromagnetic layer toward a tunnel oxide layer and through a... |
| US-7,371,509 |
Resist pattern and reflow technology A reflow stabilizing solution for treating photoresist patterns and a reflow technology are disclosed. The reflow stabilizing solution comprises a polymer and is... |
| US-7,371,333 |
Methods of etching nickel silicide and cobalt silicide and methods of
forming conductive lines The invention includes methods of etching nickel silicide and cobalt silicide, and methods of forming conductive lines. In one implementation, a substrate... |
| US-7,371,263 |
Plasmaless dry contact cleaning method using interhalogen compounds A method of removing an oxide layer from an article. The article may be located in a reaction chamber into which an interhalogen compound reactive with the oxide... |
| US-7,370,659 |
Photolithographic stepper and/or scanner machines including cleaning
devices and methods of cleaning... Stepper and/or scanner machines including cleaning devices and methods for cleaning stepper and/or scanner machines are disclosed herein. In one embodiment, a... |
| US-7,370,306 |
Method and apparatus for designing a pattern on a semiconductor surface A method of forming a pattern of elements is shown. In one embodiment, the method is used to create a reticle. In another embodiment, the method is used to... |
| US-7,370,226 |
System and method for communicating a software-generated pulse waveform
between two servers in a network A method of monitoring a status condition of a first server with a second server in a server network, and also providing synchronization and messaging between... |
| US-7,370,225 |
System and method for communicating a software-generated pulse waveform
between two servers in a network A method of monitoring a status condition of a first server with a second server in a server network, and also providing synchronization and messaging between... |
| US-7,370,150 |
System and method for managing a cache memory A processing system optimized for data string manipulations includes data string execution circuitry associated with a bus interface unit or memory controller.... |
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