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| Patent # | Description |
|---|---|
| US-7,254,756 |
Data compression read mode for memory testing A first series combination of bit match circuits compares a predetermined bit position in data words that are involved in a compression operation. The first... |
| US-7,254,753 |
Circuit and method for configuring CAM array margin test and operation A test circuit for a content addressable memory (CAM) match detection circuit that permits testing of the margin of the match detection circuit. By applying... |
| US-7,254,331 |
System and method for multiple bit optical data transmission in memory
systems The disclosed system and method data increases data transmission speed through a memory system by using optical signals comprising a plurality of wavelengths of... |
| US-7,254,281 |
Method and apparatus for electronic image processing A method and apparatus for electronic image processing are described. One embodiment includes a method of resizing an electronic image that includes image data... |
| US-7,254,074 |
Open digit line array architecture for a memory array A system and method for sensing a data state stored by a memory cell that includes coupling a first digit line and a second digit line to a precharge voltage and... |
| US-7,254,067 |
Memory device and method having low-power, high write latency mode and
high-power, low write latency mode... A logic circuit operates write receivers in a dynamic random access memory device in either a low-power mode, high write latency mode or a high-power mode, low... |
| US-7,254,049 |
Method of comparison between cache and data register for non-volatile
memory A non-volatile memory device and data comparison circuit are described that facilitate the comparison of data between two blocks of data, such as the I/O buffer... |
| US-7,253,957 |
Integrated optics units and methods of manufacturing integrated optics
units for use with microelectronic imagers Microelectronic imagers, optical devices for microelectronic imagers, methods for manufacturing integrated optical devices for use with microelectronic imagers,... |
| US-7,253,737 |
Automated antenna trim for transmitting and receiving semiconductor
devices A radio frequency communication device and methods of testing and tuning an antenna attached thereto are disclosed. A radio frequency communication device... |
| US-7,253,715 |
Secure cargo transportation system A method of controlling access to a movable container, the method comprising controllably locking the container using an electronically actuated locking... |
| US-7,253,672 |
System and method for reduced power open-loop synthesis of output clock
signals having a selected phase... A signal generating circuit includes a pulse generator generating a pulse responsive to a periodic clock reference signal. The pulse propagates through a... |
| US-7,253,668 |
Delay-locked loop with feedback compensation A delay-locked loop (DLL) with feedback compensation is provided to increase the speed and accuracy of the DLL. After the variable delay line of the DLL is... |
| US-7,253,655 |
Output driver robust to data dependent noise Techniques for controlling a driver to reduce data dependent noise, such as simultaneous switching effects and cross-talk effects. A plurality of drivers may... |
| US-7,253,608 |
Planarity diagnostic system, e.g., for microelectronic component test
systems Maintaining proper planarity of elements of a microelectronic component test system helps ensure reliable operation of the test system. Aspects of the invention... |
| US-7,253,521 |
Methods for making integrated-circuit wiring from copper, silver, gold,
and other metals Integrated circuits include networks of electrical components that are typically wired, or interconnected, together with aluminum wires. In recent years,... |
| US-7,253,493 |
High density access transistor having increased channel width and methods
of fabricating such devices A memory device having decreased cell size and having transistors with increased channel widths. More specifically, pillars are formed in a substrate such that... |
| US-7,253,469 |
Flash memory device having a graded composition, high dielectric constant
gate insulator A graded composition, high dielectric constant gate insulator is formed between a substrate and floating gate in a flash memory cell transistor. The gate... |
| US-7,253,464 |
Junction-isolated depletion mode ferroelectric memory devices and systems Depletion-mode ferroelectric transistors are adapted for use as non-volatile memory cells for memory devices and electronic systems. Various embodiments are... |
| US-7,253,430 |
Controllable ovonic phase-change semiconductor memory device An ovonic phase-change semiconductor memory device having a reduced area of contact between electrodes of chalcogenide memories, and methods of forming the same... |
| US-7,253,428 |
Apparatus and method for feature edge detection in semiconductor
processing A system for identifying a mark or other recess formed in a substrate and at least partially covered by at least one layer of opaque or visibly opaque material.... |
| US-7,253,397 |
Packaged microelectronic imagers and methods of packaging microelectronic
imagers Microelectronic imagers and methods of packaging microelectronic imagers are disclosed herein. In one embodiment, a microelectronic imager can include a... |
| US-7,253,392 |
Image sensor with photo diode gate A photodiode has a photodiode gate structure on the surface of the substrate. The photodiode may be located in a pixel sensor cell comprising a substrate having... |
| US-7,253,390 |
Methods for packaging microelectronic imagers Microelectronic imagers with prefabricated housings and methods of packaging microelectronic imagers are disclosed herein. In one embodiment, a microelectronic... |
| US-7,253,122 |
Systems and methods for forming metal oxides using metal diketonates
and/or ketoimines A method of forming (and an apparatus for forming) a metal oxide layer on a substrate, particularly a semiconductor substrate or substrate assembly, using a... |
| US-7,253,118 |
Pitch reduced patterns relative to photolithography features Differently-sized features of an integrated circuit are formed by etching a substrate using a mask which is formed by combining two separately formed patterns.... |
| US-7,253,117 |
Methods for use of pulsed voltage in a plasma reactor A method and apparatus for providing a positive voltage spike to a semiconductor substrate pedestal during a portion of a high voltage power bias oscillation... |
| US-7,253,104 |
Methods of forming particle-containing materials The invention includes methods of forming particle-containing materials, and also includes semiconductor constructions comprising particle-containing materials.... |
| US-7,253,102 |
Methods for forming and integrated circuit structures containing
enhanced-surface-area conductive layers An enhanced-surface-area conductive layer compatible with high-dielectric constant materials is created by forming a film or layer having at least two phases, at... |
| US-7,253,089 |
Microfeature devices and methods for manufacturing microfeature devices Microfeature devices, microfeature workpieces, and methods for manufacturing microfeature devices and microfeature workpieces are disclosed herein. The... |
| US-7,253,085 |
Deposition methods The invention includes a method for selective deposition of semiconductor material. A substrate is placed within a reaction chamber. The substrate comprises a... |
| US-7,253,076 |
Methods for forming and integrated circuit structures containing ruthenium
and tungsten containing layers Capacitors having increased capacitance include an enhanced-surface-area (rough-surfaced) electrically conductive layer or other layers that are compatible with... |
| US-7,253,064 |
Cascode I/O driver with improved ESD operation A cascode I/O driver is described that includes a barrier formed in the shared region between the two transistors. The barrier region allows the I/O driver to be... |
| US-7,253,053 |
Methods of forming transistor devices and capacitor constructions The invention includes methods of forming circuit devices. A metal-containing material comprising a thickness of no more than 20 .ANG. (or alternatively... |
| US-7,253,052 |
Method for forming a storage cell capacitor compatible with high
dielectric constant materials Described are integrated circuit electrodes and method for fabricating an electrode, which include, in an embodiment forming a silicon, first portion of the... |
| US-7,253,047 |
Semiconductor processing methods of forming transistors, semiconductor
processing methods of forming dynamic... Semiconductor processing methods of forming transistors, semiconductor processing methods of forming dynamic random access memory circuitry, and related... |
| US-7,253,025 |
Multiple substrate microelectronic devices and methods of manufacture A microelectronic device and method for manufacture. In one embodiment, two microelectronic substrates are directly bonded to each other without an intermediate... |
| US-7,253,022 |
Method for fabricating semiconductor package with multi-layer metal bumps A semiconductor package includes a substrate formed of a board material, a semiconductor die bonded to the substrate, and an encapsulant on the die. The package... |
| US-7,251,762 |
On-chip sampling circuit and method Through addressing circuitry, a sampling circuit can choose a unique internal node/signal on an encapsulated/packaged chip to be output to one or more drivers.... |
| US-7,251,715 |
Double data rate scheme for data output Systems, devices, and methods for a double data rate memory device includes a storage element, a first pipeline, and a second pipeline. The pipelines are... |
| US-7,251,714 |
Method and system for capturing and bypassing memory transactions in a
hub-based memory system A memory hub includes a reception interface that receives data words and captures the data words in response to a first clock signal in a first time domain. The... |
| US-7,251,711 |
Apparatus and methods having a command sequence Power consumption by a memory device is optimized by maintaining data input buffers in an off state until a command sequence containing a write command is... |
| US-7,251,618 |
Method and system for purchasing a memory upgrade for a computer system One embodiment of the present invention provides a system that facilitates purchasing a memory upgrade for a computer system. This system operates by obtaining... |
| US-7,251,387 |
Optical integrated circuit and method for fabricating the same The present technique relates to a method and apparatus for fabricating an optical integrated circuit amplifier with another type of optical integrated circuit.... |
| US-7,251,194 |
Memory system and method for strobing data, command and address signals A memory system couples command, address or write data signals from a memory controller to a memory device and read data signals from the memory device to the... |
| US-7,251,187 |
Memory system, method and predecoding circuit operable in different modes
for selectively accessing multiple... A memory system including a non-volatile flash memory and a method for simultaneously selecting a plurality of memory blocks are disclosed. The memory system is... |
| US-7,251,181 |
Techniques for storing accurate operating current values Methods of manufacturing memory devices and memory modules comprising memory device. Specifically, respective operating current values may be measured and/or... |
| US-7,251,177 |
Skewed sense AMP for variable resistance memory sensing A variable resistance memory sense amplifier has a built-in offset to assist in switching the sense amplifier when a resistive memory cell is in a low resistance... |
| US-7,251,173 |
Combination column redundancy system for a memory array A column redundancy system combining at least two different redundancy systems to provide local redundant memory and shared redundant memory. The column... |
| US-7,251,154 |
Method and apparatus providing a cross-point memory array using a variable
resistance memory cell and capacitance The invention relates to a method and apparatus providing a memory cell array in which each resistance memory cell is connected in series to a capacitive... |
| US-7,250,798 |
Synchronous clock generator including duty cycle correction A clock generator for generating an output clock signal synchronized with an input clock signal and having a corrected duty cycle. The clock generator includes... |
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