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| Patent # | Description |
|---|---|
| US-7,417,677 |
Lag cancellation in CMOS image sensors A pixel cell with improved lag characteristics without increased noise. The pixel cell according to embodiments of the invention includes a photo-conversion... |
| US-7,417,674 |
Multi-magnification color image sensor A color image sensor has imaging elements each structured to form, at an image plane, an image of a subject having a respective magnification. Ones of the... |
| US-7,417,505 |
CMOS amplifiers with frequency compensating capacitors The frequency and transient responses of a CMOS differential amplifier are improved by employing one or more compensating capacitors. A compensating capacitor... |
| US-7,417,478 |
Delay line circuit Methods, circuits, devices, and systems are provided, including a delay line for a delay-locked loop. One method includes providing a reference clock to a first... |
| US-7,417,325 |
Semiconductor component having thinned die with conductive vias configured
as conductive pin terminal contacts A semiconductor component includes a thinned semiconductor die having protective polymer layers on up to six surfaces. The component also includes contact bumps... |
| US-7,417,305 |
Electronic devices at the wafer level having front side and edge
protection material and systems including the... Methods for applying a dielectric protective layer to a wafer in wafer-level chip scale package manufacture are disclosed. A flowable dielectric protective... |
| US-7,417,294 |
Microelectronic imaging units and methods of manufacturing microelectronic
imaging units Microelectronic imaging units and methods for manufacturing microelectronic imaging units are disclosed herein. In one embodiment, a method includes placing a... |
| US-7,417,280 |
Method and apparatus for a flash memory device comprising a source local
interconnect A method for forming a flash memory device having a local interconnect connecting source regions of a plurality of transistors within a sector allows for a... |
| US-7,417,272 |
Image sensor with improved dynamic range and method of formation Embodiments of the invention provide an image sensor having an improved dynamic range. A pixel cell comprises at least one transistor structure. The transistor... |
| US-7,416,994 |
Atomic layer deposition systems and methods including metal
beta-diketiminate compounds The present invention provides atomic layer deposition systems and methods that include metal compounds with at least one .beta.-diketiminate ligand. Such... |
| US-7,416,958 |
Epitaxial semiconductor layer and method A method for epitaxially forming a first semiconductor structure attached to a second semiconductor structure is provided. Devices and methods described include... |
| US-7,416,943 |
Peripheral gate stacks and recessed array gates Methods are provided for simultaneously processing transistors in two different regions of an integrated circuit. Planar transistors are provided in a logic... |
| US-7,416,933 |
Methods of enabling polysilicon gate electrodes for high-k gate
dielectrics Complementary transistors and methods of forming the complementary transistors on a semiconductor assembly are described. The transistors are formed with an... |
| US-7,416,913 |
Methods of manufacturing microelectronic imaging units with discrete
standoffs Microelectronic imaging units and methods for manufacturing microelectronic imaging units are disclosed herein. In one embodiment, a method includes placing a... |
| US-7,416,892 |
Method and system for microfluidic manipulation, amplification and
analysis of fluids, for example, bacteria... A microfluidic system for isolation and amplification of DNA or RNA from aqueous solutions and detection of the DNA or RNA on a lateral flow detection strip,... |
| US-7,416,472 |
Systems for planarizing workpieces, e.g., microelectronic workpieces This disclosure provides methods and apparatus for predictably changing the thickness of a microfeature workpiece. One implementation provides a planarizing... |
| US-7,416,107 |
Concave face wire bond capillary and method An improved wire bonding capillary used in the bonding of wires to the bond pads of a semiconductor device and the leads of a lead frame, the wire bonding... |
| US-7,415,567 |
Memory hub bypass circuit and method A computer system and a method used to access data from a plurality of memory devices with a memory hub. The computer system includes a plurality of memory... |
| US-7,415,404 |
Method and apparatus for generating a sequence of clock signals A clock generator circuit generates a sequence of clock signals equally phased from each other from a master clock signal. The clock generator is formed by inner... |
| US-7,415,317 |
Method and system for correlating and combining production and
non-production data for analysis This document discusses, among other things, a method and system for correlating and combining production and non-production data for analysis for the purposes... |
| US-7,414,895 |
NAND flash memory cell programming A flash memory device, such as a NAND flash, having an array of floating gate transistor memory cells arranged in a first and second addressable blocks. A... |
| US-7,414,662 |
Multifunction lens An image capture apparatus having a multifunction lens and a method for capturing an image are disclosed. The multifunction lens has an imaging lens portion... |
| US-7,414,661 |
CMOS image sensor using gradient index chip scale lenses A camera module includes a gradient index lens on a spacer plate attached over an array of pixel sensors and associated micro lenses. The spacer plate and... |
| US-7,414,653 |
Dark reduction via feedback control of photodiode bias An active pixel sensor comprises a photodiode providing a photodiode output current indicative of an intensity of light incident the photodiode and an integrator... |
| US-7,414,444 |
Clock capture in clock synchronization circuitry Clock capturing synchronization circuitry first generates a synchronized clock signal from a reference clock signal, then captures the synchronized clock signal,... |
| US-7,414,299 |
Semiconductor package assembly and method for electrically isolating
modules A semiconductor package assembly and method for electrically isolating modules, having a capacitor within the semiconductor package assembly. The package... |
| US-7,414,297 |
Capacitor constructions The invention includes methods of forming rugged electrically conductive surfaces. In one method, a layer is formed across a substrate and subsequently at least... |
| US-7,414,260 |
Vertical tunneling transistor The disclosed embodiments relate to a vertical tunneling transistor that may include a channel disposed on a substrate. A quantum dot may be disposed so that an... |
| US-7,413,981 |
Pitch doubled circuit layout In one embodiment of the present invention, a method for connecting a plurality of bit lines to sense circuitry includes providing a plurality of bit lines... |
| US-7,413,979 |
Methods for forming vias in microelectronic devices, and methods for
packaging microelectronic devices Microelectronic devices, methods for packaging microelectronic devices, and methods for forming vias and conductive interconnects in microfeature workpieces and... |
| US-7,413,962 |
Method for forming sublithographic features during the manufacture of a
semiconductor device and a resulting... A method for forming a semiconductor device comprises forming a layer to be etched, then forming a hard mask layer over the layer to be etched. The hard mask is... |
| US-7,413,952 |
Methods of forming a plurality of circuit components and methods of
forming a plurality of structures suspended... A plurality of capacitor electrode openings is formed within capacitor electrode-forming material. A first set of the openings is formed to a depth which is... |
| US-7,413,948 |
Semiconductor capacitor structure and method to form same A semiconductor capacitor structure comprising sidewalls of conductive hemispherical grained material, a base of metal silicide material, and a metal nitride... |
| US-7,413,946 |
Formation of standard voltage threshold and low voltage threshold MOSFET
devices Wells are formed in a substrate where standard Vt and low Vt devices of both a first and second type are to be fabricated. Wells defining the locations of first... |
| US-7,413,928 |
Die-wafer package and method of fabricating same A die-wafer package includes a singulated semiconductor die having a first plurality of bond pads on a first surface and a second plurality of bond pads on a... |
| US-7,413,500 |
Methods for planarizing workpieces, e.g., microelectronic workpieces This disclosure provides methods and apparatus for predictably changing the thickness of a microfeature workpiece. One implementation provides a planarizing... |
| US-7,413,480 |
Silicon pillars for vertical transistors In order to form a more stable silicon pillar which can be used for the formation of vertical transistors in DRAM cells, a multi-step masking process is used. In... |
| US-7,413,342 |
DRAM temperature measurement system A converter comprising a comparator having a first input operable to receive a first signal, a second input operable to receive a second signal, and an output, a... |
| US-7,412,634 |
On-chip sampling circuit and method Through addressing circuitry, a sampling circuit can choose a unique internal node/signal on an encapsulated/packaged chip to be output to one or more drivers.... |
| US-7,412,574 |
System and method for arbitration of memory responses in a hub-based
memory system A memory hub module includes a decoder that receives memory requests determines a memory request identifier associated with each memory request. A packet memory... |
| US-7,412,571 |
Memory arbitration system and method having an arbitration packet protocol A memory hub and method for transmitting a read response on a data path of a memory hub interposed between a transmitting memory hub and a receiving memory hub.... |
| US-7,412,566 |
Memory hub and access method having internal prefetch buffers A memory module includes a memory hub coupled to several memory devices. The memory hub includes history logic that predicts on the basis of read memory requests... |
| US-7,411,857 |
Power savings in active standby mode Apparatus for reducing the power consumed by a memory device selectively activates a power saving mode in which operation of a delay compensation circuit may be... |
| US-7,411,848 |
Independent polling for multi-page programming A method of testing, polling and trimming memory pages in different memory banks simultaneously is presented, using a cache memory located in each one of the... |
| US-7,411,832 |
Programming a non-volatile memory device A non-volatile memory device that changes the programming step voltage between the source side of the array and the drain side of the array. After the initial... |
| US-7,411,823 |
In-service reconfigurable DRAM and flash memory device A memory cell that has both a DRAM cell and a non-volatile memory cell. The non-volatile memory cell might include a flash memory or an NROM cell. The memory... |
| US-7,411,812 |
Memory architecture and method of manufacture and operation thereof An architecture, and its method of formation and operation, containing a high density memory array of semi-volatile or non-volatile memory elements, including,... |
| US-7,411,807 |
System and method for optically interconnecting memory devices A memory device includes a semiconductor substrate in which memory circuitry has been fabricated. An address converter and a control signal converter are coupled... |
| US-7,411,651 |
PSM alignment method and device The present invention relates to alignment of a writing system and a workpiece. In particular, it relates to alignment to write a second layer pattern on a... |
| US-7,411,621 |
Apparatus and method for eliminating artifacts in active pixel sensor
(APS) imagers An active pixel sensor (APS) that includes circuitry to eliminate artifacts in digital images. The APS includes a comparator for comparing a signal level from a... |
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