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Patent # Description
US-7,259,066 One-transistor composite-gate memory
One-transistor memory devices facilitate nonvolatile data storage through the manipulation of oxygen vacancies within a trapping layer of a field-effect...
US-7,259,064 Forming integrated circuit devices
Methods of forming integrated circuit devices are provided. A first mask layer is formed overlying a first portion of a semiconductor substrate. The first mask...
US-7,258,954 Method to recover the exposure sensitivity of chemically amplified resins from post coat delay effect
Methods of fabricating a photomask, methods of treating a chemically amplified resist-coated photomask blank, a photomask blank resulting from the methods, and...
US-7,258,895 Methods of forming material on a substrate, and a method of forming a field effect transistor gate oxide on a...
The invention includes methods of forming material on a substrate and methods of forming a field effect transistor gate oxide. In one implementation, a first...
US-7,258,892 Methods and systems for controlling temperature during microfeature workpiece processing, e.g., CVD deposition
The present disclosure provides methods and systems for controlling temperature. The method has particular utility in connection with controlling temperature in...
US-7,258,596 Systems and methods for monitoring characteristics of a polishing pad used in polishing micro-device workpieces
Systems and methods for monitoring characteristics of a polishing pad used in polishing a micro-device workpiece are disclosed herein. In one embodiment, a...
US-7,257,884 Method for fabricating semiconductor component with adjustment circuitry for electrical characteristics or...
A semiconductor component includes adjustment circuitry configured to adjust selected physical and electrical characteristics of the component or elements...
US-7,257,697 Processing system with general purpose execution unit and separate independently operating data string...
A processing system optimized for data string manipulations includes data string execution circuitry associated with a bus interface unit or memory controller....
US-7,257,683 Memory arbitration system and method having an arbitration packet protocol
A memory hub and method for transmitting a read response on a data path of a memory hub interposed between a transmitting memory hub and a receiving memory hub....
US-7,257,670 Multipurpose CAM circuit
A content addressable memory (CAM) device for use in various sizes of systems while requiring minimal circuitry to enlarge the size of the prioritization...
US-7,257,667 Status register to improve initialization of a synchronous memory
A synchronous flash memory includes an array of non-volatile memory cells. The memory device has a package configuration that is compatible with an SDRAM. The...
US-7,257,043 Isolation device over field in a memory device
A memory device includes isolation devices located between-memory cells. A plurality of isolation lines connects the isolation devices to a positive voltage...
US-7,257,024 Minimizing adjacent wordline disturb in a memory device
A selected wordline that is coupled to cells for programming is biased with a programming voltage. The unselected wordlines that are adjacent to the selected...
US-7,257,022 Nanocrystal write once read only memory for archival storage
Structures and methods for write once read only memory employing charge trapping are provided. The write once read only memory cell includes a metal oxide...
US-7,256,643 Device and method for generating a low-voltage reference
A voltage reference generating method, source, memory device and substrate containing the same include a voltage reference generator comprised of a bandgap...
US-7,256,595 Test sockets, test systems, and methods for testing microfeature devices
Test sockets, test systems, and methods for testing microfeature devices with a substrate and a plurality of conductive interconnect elements projecting from the...
US-7,256,490 Test carrier for semiconductor components having conductors defined by grooves
A test carrier for a semiconductor component includes a base for retaining the component, and an interconnect on the base having contacts configured to...
US-7,256,452 NROM memory device with a high-permittivity gate dielectric formed by the low temperature oxidation of metals
A high permittivity gate dielectric formed by low temperature metal oxidation is used in an NROM memory cell. The gate dielectric has a dielectric constant...
US-7,256,451 NROM memory device with a high-permittivity gate dielectric formed by the low temperature oxidation of metals
A high permittivity gate dielectric formed by low temperature metal oxidation is used in an NROM memory cell. The gate dielectric has a dielectric constant...
US-7,256,450 NROM memory device with a high-permittivity gate dielectric formed by the low temperature oxidation of metals
A high permittivity gate dielectric formed by low temperature metal oxidation is used in an NROM memory cell. The gate dielectric has a dielectric constant...
US-7,256,138 Method and composition for selectively etching against cobalt silicide
An etching method for use in integrated circuit fabrication includes providing a metal nitride layer on a substrate assembly, providing regions of cobalt...
US-7,256,123 Method of forming an interface for a semiconductor device
In a semiconductor device using a polysilicon contact, such as a poly plug between a transistor and a capacitor in a container cell, an interface is provided...
US-7,256,116 Method for fabricating semiconductor components having encapsulated, bonded, interconnect contacts on...
A method for fabricating a semiconductor component includes the steps of providing a semiconductor die, forming a plurality of redistribution contacts on the...
US-7,256,115 Asymmetric plating
A method and apparatus are disclosed for forming a tapered contact structure over a contact pad. The tapered contact structure may be used to securely anchor an...
US-7,256,074 Methods for wafer-level packaging of microelectronic devices and microelectronic devices formed by such methods
Methods for packaging microelectronic devices, microelectronic workpieces having packaged dies, and microelectronic devices are disclosed herein. One aspect of...
US-7,256,069 Wafer-level package and methods of fabricating
A carrier for use in a chip-scale package, including a polymeric film with apertures defined therethrough. The apertures, which are alignable with corresponding...
US-7,256,068 Semiconductor package assembly and method for electrically isolating modules
A semiconductor package assembly and method for electrically isolating modules, having a capacitor within the semiconductor package assembly. The package...
US-7,255,803 Method of forming contact openings
The invention includes etching and contact opening forming methods. In one implementation, a plasma etching method includes providing a bottom powered plasma...
US-7,255,802 Tape substrate and method for fabricating the same
A method for fabricating a tape substrate includes forming, on an insulating film, a copper foil pattern having a connecting area; coating a solder resist on the...
US-7,255,630 Methods of manufacturing carrier heads for polishing micro-device workpieces
Carrier assemblies, polishing machines with carrier assemblies, and methods for mechanical and/or chemical-mechanical polishing of micro-device workpieces are...
US-7,255,273 Descriptor for identifying a defective die site
The present invention relates to the marking and identification of defective die sites on a mounting substrate. A mounting substrate is provided which is...
US-7,255,128 System and method for detecting flow in a mass flow controller
Systems and methods are provided for detecting flow in a mass flow controller (MFC). The position of a gate in the MFC is sensed or otherwise determined to...
US-RE39,768 VCC pump for CMOS imagers
A CMOS imaging device which includes a charge pump connected to one or more of a reset gate, transfer gate and row select gate of sensor cells and provides gate...
US-7,254,756 Data compression read mode for memory testing
A first series combination of bit match circuits compares a predetermined bit position in data words that are involved in a compression operation. The first...
US-7,254,753 Circuit and method for configuring CAM array margin test and operation
A test circuit for a content addressable memory (CAM) match detection circuit that permits testing of the margin of the match detection circuit. By applying...
US-7,254,331 System and method for multiple bit optical data transmission in memory systems
The disclosed system and method data increases data transmission speed through a memory system by using optical signals comprising a plurality of wavelengths of...
US-7,254,281 Method and apparatus for electronic image processing
A method and apparatus for electronic image processing are described. One embodiment includes a method of resizing an electronic image that includes image data...
US-7,254,074 Open digit line array architecture for a memory array
A system and method for sensing a data state stored by a memory cell that includes coupling a first digit line and a second digit line to a precharge voltage and...
US-7,254,067 Memory device and method having low-power, high write latency mode and high-power, low write latency mode...
A logic circuit operates write receivers in a dynamic random access memory device in either a low-power mode, high write latency mode or a high-power mode, low...
US-7,254,049 Method of comparison between cache and data register for non-volatile memory
A non-volatile memory device and data comparison circuit are described that facilitate the comparison of data between two blocks of data, such as the I/O buffer...
US-7,253,957 Integrated optics units and methods of manufacturing integrated optics units for use with microelectronic imagers
Microelectronic imagers, optical devices for microelectronic imagers, methods for manufacturing integrated optical devices for use with microelectronic imagers,...
US-7,253,737 Automated antenna trim for transmitting and receiving semiconductor devices
A radio frequency communication device and methods of testing and tuning an antenna attached thereto are disclosed. A radio frequency communication device...
US-7,253,715 Secure cargo transportation system
A method of controlling access to a movable container, the method comprising controllably locking the container using an electronically actuated locking...
US-7,253,672 System and method for reduced power open-loop synthesis of output clock signals having a selected phase...
A signal generating circuit includes a pulse generator generating a pulse responsive to a periodic clock reference signal. The pulse propagates through a...
US-7,253,668 Delay-locked loop with feedback compensation
A delay-locked loop (DLL) with feedback compensation is provided to increase the speed and accuracy of the DLL. After the variable delay line of the DLL is...
US-7,253,655 Output driver robust to data dependent noise
Techniques for controlling a driver to reduce data dependent noise, such as simultaneous switching effects and cross-talk effects. A plurality of drivers may...
US-7,253,608 Planarity diagnostic system, e.g., for microelectronic component test systems
Maintaining proper planarity of elements of a microelectronic component test system helps ensure reliable operation of the test system. Aspects of the invention...
US-7,253,521 Methods for making integrated-circuit wiring from copper, silver, gold, and other metals
Integrated circuits include networks of electrical components that are typically wired, or interconnected, together with aluminum wires. In recent years,...
US-7,253,493 High density access transistor having increased channel width and methods of fabricating such devices
A memory device having decreased cell size and having transistors with increased channel widths. More specifically, pillars are formed in a substrate such that...
US-7,253,469 Flash memory device having a graded composition, high dielectric constant gate insulator
A graded composition, high dielectric constant gate insulator is formed between a substrate and floating gate in a flash memory cell transistor. The gate...
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