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Patent # Description
US-1,000,8503 Memory devices which include memory arrays
Some embodiments include a memory device. The device has a fin with a first source/drain region, a second source/drain region and a channel region. The first...
US-1,000,8468 Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices
Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices are disclosed herein. In one embodiment, a packaged...
US-1,000,8461 Semiconductor structure having a patterned surface structure and semiconductor chips including such structures
A connector structure and a manufacturing method thereof are provided. The connector structure includes a semiconductor substrate, a metal layer, a passivation...
US-1,000,8395 Stacked semiconductor die assemblies with high efficiency thermal paths and molded underfill
Semiconductor die assemblies having high efficiency thermal paths and molded underfill material. In one embodiment, a semiconductor die assembly comprises a...
US-1,000,8381 Constructions comprising rutile-type titanium oxide; and methods of forming and utilizing rutile-type titanium...
Some embodiments include methods of forming rutile-type titanium oxide. A monolayer of titanium nitride may be formed. The monolayer of titanium nitride may...
US-1,000,8287 Shared error detection and correction memory
Apparatuses and methods for an interface chip are described. An example apparatus includes a first chip. The first chip includes, on a single semiconductor...
US-1,000,8254 Apparatus having dice to perorm refresh operations
Some embodiments include an apparatus that comprise an interface chip having an oscillator to produce an original clock signal, a first memory chip having first...
US-1,000,7630 Encapsulation enabled PCIE virtualisation
A method for transmitting data packets from a first device through a switch to a second device is described. The method is performed at an intercepting device...
US-1,000,7486 Systems and methods to enable identification of different data sets
Systems and methods are provided, such as those that enable identification of data flows and corresponding results in a pattern-recognition processor. In one...
US-1,000,7465 Remapping in a memory device
Methods of operating a memory device, and memory devices and systems so configured, include receiving a first address range for programming user data to a first...
US-1,000,7435 Translation lookaside buffer in memory
Examples of the present disclosure provide apparatuses and methods related to a translation lookaside buffer in memory. An example method comprises receiving a...
US-1,000,7431 Storage devices configured to generate linked lists
Storage devices including a controller, a first memory coupled to the controller, and a second memory coupled to the controller, wherein the controller is...
US-1,000,7428 Data storage management
A method of managing a plurality of storage devices. The method comprises at a first device connected to the plurality of storage devices via a switch,...
US-1,000,5308 Stamps and methods of forming a pattern on a substrate
Methods for fabricating stamps and systems for patterning a substrate, and devices resulting from those methods are provided.
US-1,000,3675 Packet processor receiving packets containing instructions, data, and starting location and generating packets...
A method, an apparatus, and a system have been disclosed. An embodiment of the method includes an autonomous memory device receiving a set of instructions, the...
US-1,000,2994 Solid state lighting devices having improved color uniformity and associated methods
Solid state lighting (SSL) devices and methods of manufacturing SSL devices are disclosed herein. In one embodiment, an SSL device comprises a support having a...
US-1,000,2935 Semiconductor devices and structures and methods of formation
A semiconductor device structure is disclosed. The semiconductor device structure includes a mesa extending above a substrate. The mesa has a channel region...
US-1,000,2874 Method of forming conductive material of a buried transistor gate line and method of forming a buried...
A method of forming conductive material of a buried transistor gate line includes adhering a precursor comprising tungsten and chlorine to material within a...
US-1,000,2840 Semiconductor devices having discretely located passivation material, and associated systems and methods
Semiconductor devices having discretely located passivation material are disclosed herein. In one embodiment, a semiconductor device assembly can include a bond...
US-1,000,2666 FeRAM-DRAM hybrid memory
Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. One method includes determining whether to access a first memory...
US-1,000,2659 System and method for decoding commands based on command signals and operating state
A system and method for decoding command signals that includes a command decoder configured to generate internal control signals to perform an operation based...
US-1,000,2647 Apparatuses and methods for sharing transmission vias for memory devices
Apparatuses and methods for transmitting die state information between a plurality of dies are described. An example apparatus includes: a plurality of dies,...
US-1,000,1793 Apparatuses and methods for providing constant current
An apparatus is described comprising a bandgap reference circuit comprising: an amplifier including first and second inputs and an output; and a bandgap...
US-9,997,662 Light-emitting metal-oxide-semiconductor devices and associated systems, devices, and methods
Various embodiments of solid state transducer ("SST") devices are disclosed. In several embodiments, a light emitter device includes a metal-oxide-semiconductor...
US-9,997,592 Capacitor, array of capacitors, and device comprising an electrode
A capacitor includes an elevationally inner capacitor electrode, an elevationally outer capacitor electrode, and capacitor insulator between the elevationally...
US-9,997,461 Electrically conductive laminate structures
Some embodiments include electrical interconnects. The interconnects may contain laminate structures having a graphene region sandwiched between non-graphene...
US-9,997,452 Forming conductive plugs for memory device
Apparatuses and methods with conductive plugs for a memory device are described. An example method includes: forming a plurality of shallow trench isolations...
US-9,997,398 Methods of forming one or more covered voids in a semiconductor substrate
Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for...
US-9,997,247 Memory devices having source lines directly coupled to body regions and methods
Memory devices, memory cell strings and methods of operating memory devices are shown. Configurations described include directly coupling an elongated body...
US-9,997,246 Memory devices and their operation having trim registers associated with access operation commands
Methods including performing an access operation on a memory device using trims corresponding to trim settings, receiving a command to suspend the access...
US-9,997,232 Processing in memory (PIM) capable memory device having sensing circuitry performing logic operations
Apparatuses and methods are provided for logic/memory devices. An example apparatus comprises a plurality of memory components adjacent to and coupled to one...
US-9,997,220 Apparatuses and methods for adjusting delay of command signal path
Apparatuses and methods related to adjusting a delay of a command signal path are disclosed. An example apparatus includes: a timing circuit that includes a...
US-9,997,212 Accessing data in memory
The present disclosure includes apparatuses and methods related to accessing data in memory. One example method comprises storing data associated with a first...
US-9,996,496 Devices, systems, and methods of reducing chip select
Several systems and methods of chip select are described. In one such method, a device maintains two identifiers, (ID_a and ID_m). When the device receives a...
US-9,996,479 Encryption of executables in computational memory
The present disclosure is related to encryption of executables in computational memory. Computational memory can traverse an operating system page table in the...
US-9,991,331 Apparatuses and methods for semiconductor circuit layout
Apparatuses including compensation capacitors are described. An example apparatus includes: first, second and third capacitors arranged such that the second...
US-9,991,273 Floating gate memory cells in vertical memory
Floating gate memory cells in vertical memory. A control gate is formed between a first tier of dielectric material and a second tier of dielectric material. A...
US-9,991,210 Electromagnetic shield and associated methods
Semiconductor devices are described, along with methods and systems that include them. One such device includes a diffusion region in a semiconductor material,...
US-9,991,122 Methods of forming semiconductor device structures including two-dimensional material structures
A method of forming a semiconductor device structure comprises forming at least one 2D material over a substrate. The at least one 2D material is treated with...
US-9,990,995 Systems having a resistive memory device
Systems having a resistive memory device having control circuitry configured to build a data word from remapped data bits from a received data word such that...
US-9,990,994 Methods of programming memories having a shared resistance variable material
Methods for programming data to an array of memory cells having a first memory cell, a second memory cell that is adjacent to the first memory cell in a first...
US-9,990,990 Apparatuses and methods for accessing variable resistance memory device
The disclosed technology generally relates to memory apparatuses and methods of operating the same, and more particularly to a memory device having a controller...
US-9,990,989 Enhancing nucleation in phase-change memory cells
Various embodiments disclosed herein comprise methods and apparatuses for placing phase-change memory (PCM) cells of a memory array into a temperature regime...
US-9,990,988 Determining whether a memory cell state is in a valley between adjacent data states
A determination can be made as to whether a state of a memory cell is in a valley between adjacent distributions of states associated with respective data...
US-9,990,977 Power reduction for a sensing operation of a memory cell
Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A memory device may leverage non-volatile memory properties of a...
US-9,990,971 Devices, methods, and systems supporting on unit termination
The present disclosure includes devices, methods, and systems supporting on unit termination. A number of embodiments include a number of memory units, wherein...
US-9,990,967 Apparatuses and methods for performing corner turn operations using sensing circuitry
The present disclosure includes apparatuses and methods related to performing corner turn operations using sensing circuitry. An example apparatus comprises a...
US-9,990,144 Stacked memory devices, systems, and methods
Memory requests for information from a processor are received in an interface device, and the interface device is coupled to a stack including two or more...
US-9,989,616 Memory arrays
Some embodiments include memory arrays. The memory arrays can have global bitlines extending along a first horizontal direction, vertical local bitlines...
US-9,985,651 Read threshold calibration for LDPC
Apparatuses and methods for soft read threshold location calibration are provided. One example method can include selecting read threshold sets (RTSs), and...
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