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Apparatus and methods for through substrate via test
A stack of vertically-connected, horizontally-oriented integrated circuits (ICs) may have electrical connections from the front side of one IC to the back side...
Methods of fabricating memory devices having charged species
Methods for fabricating memory devices having charged species. In one such method, a dielectric material is formed adjacent to a semiconductor. A charged...
Memory cell coupling compensation
Methods for memory cell coupling compensation and apparatuses configured to perform the same are described. One or more methods for memory cell coupling...
Apparatuses and methods including memory array data line selection
Some embodiments include an apparatus having data lines coupled to memory cell strings and a selector configured to selectively couple one of the data lines to...
Mapping between program states and data patterns
The present disclosure includes methods and apparatuses for mapping between program states and data patterns. One method includes: programming a group of G...
Methods and apparatuses including a string of memory cells having a first
select transistor coupled to a second...
Generally discussed herein are apparatuses and methods. One such apparatus includes a data line, a first memory cell and a first select transistor. The first...
Partial page memory operations
Apparatuses may include a memory block with strings of memory cells formed in a plurality of tiers. The apparatus may further comprise access lines and data...
Method and apparatus for sensing in a memory
A method and a memory for sensing a state of a memory cell while the memory cell capacitor is isolated from a data line are described. An activation device of...
Apparatuses and methods for measuring an electrical characteristic of a
model signal line and providing...
Apparatuses and methods for measuring an electrical characteristic of a model signal line and providing measurement information based at least in part on the...
Stacked device detection and identification
Various embodiments include apparatus and methods having circuitry to detect and/or assign identification information to dice arranged in a stack and coupled by...
Memory device distributed controller system
A memory device distributed controller circuit distributes memory control functions amongst a plurality of memory controllers. A master controller receives an...
Security protection for memory content of processor main memory
Subject matter disclosed herein relates to memory devices and security of same.
Thermal anneal of block copolymer films with top interface constrained to
wet both blocks with equal preference
Methods for fabricating sub-lithographic, nanoscale microstructures utilizing self-assembling block copolymers, and films and devices formed from these methods...
Conductive structures for microfeature devices and methods for fabricating
Methods for fabricating conductive structures on and/or in interposing devices and microfeature devices that are formed using such methods are disclosed herein....
Memory arrays and methods of forming memory arrays
Some embodiments include memory arrays having a plurality of memory cells vertically between bitlines and wordlines. The memory cells contain phase change...
Some embodiments include a memory cell having a data storage region between a pair of conductive structures. The data storage region is configured to support a...
Memories with memory arrays extending in opposite directions from a
semiconductor and their formation
Memories and their formation are disclosed. One such memory has a first array of first memory cells extending in a first direction from a first surface of a...
Devices and methods of programming memory cells
Devices and methods of programming memory cells, both SLC and MLC, such as to reduce charge-storage structure to charge-storage structure coupling, are shown...
Memory timing self-calibration
Methods for memory input timing self-calibration, apparatuses for input timing self-calibration, and systems are disclosed. One such method includes...
Methods of operating memory devices
Methods of operating a memory device include applying an increasing sense voltage to a plurality of memory cells, wherein memory cells of the plurality of...
Memory device and method having charge level assignments selected to
minimize signal coupling
A non-volatile memory device programs memory cells in each row in a manner that minimizes the coupling of spurious signals. A control logic unit programs the...
Accessing memory cells in parallel in a cross-point array
Methods and structures for accessing memory cells in parallel in a cross-point array include accessing in parallel a first memory cell disposed between a first...
Memory sense amplifiers and memory verification methods
Memory sense amplifiers and memory verification methods are described. According to one aspect, a memory sense amplifier includes a first input coupled with a...
Methods and apparatus providing thermal isolation of photonic devices
Described embodiments include photonic integrated circuits and systems with photonic devices, including thermal isolation regions for the photonic devices....
Read threshold calibration for LDPC
Apparatuses and methods for soft read threshold location calibration are provided. One example method can include selecting read threshold sets (RTSs), and...
Output driver robust to data dependent noise
Techniques for controlling a driver to reduce data dependent noise, such as simultaneous switching effects and cross-talk effects. A plurality of drivers may...
Voltage regulators, amplifiers, memory devices and methods
Circuits, devices and methods are provided, such as an amplifier (e.g., a voltage regulator) that includes a feedback circuit that supplies negative feedback...
Replacement materials processes for forming cross point memory
Methods of forming memory cells comprising phase change and/or chalcogenide materials are disclosed. In one aspect, the method includes providing a lower line...
Phase change memory stack with treated sidewalls
Memory devices and methods for fabricating memory devices have been disclosed. One such method includes forming the memory stack out of a plurality of elements....
Methods of fabricating integrated structures, and methods of forming
vertically-stacked memory cells
Some embodiments include a method of fabricating integrated structures. A metal-containing material is formed over a stack of alternating first and second...
A memory cell includes a select device and a capacitor electrically coupled in series with the select device. The capacitor includes two conductive capacitor...
Apparatuses and related methods for staggering power-up of a stack of
An apparatus including semiconductor dies in a stack. The semiconductor dies are configured to power-up in a staggered manner. Methods for powering up an...
Devices, systems and methods for manufacturing through-substrate vias and
Methods of manufacturing semiconductor devices and semiconductor devices with through-substrate vias (TSVs). One embodiment of a method of manufacturing a...
Method and system for electrically coupling a chip to chip package
A chip and a chip package can transmit information to each other by using a set of converters capable of communicating with each other through the emission and...
Method of making a semiconductor device
Some embodiments include a semiconductor device having a stack structure including a plurality of alternating tiers of dielectric material and poly-silicon...
Semiconductor substrate for photonic and electronic structures and method
A method of forming a substrate with isolation areas suitable for integration of electronic and photonic devices is provided. A common reticle and...
Pitch reduction technology using alternating spacer depositions during the
formation of a semiconductor device...
A method for patterning a layer increases the density of features formed over an initial patterning layer using a series of self-aligned spacers. A layer to be...
Page buffer connections and determining pass/fail condition of memories
Apparatus and methods for determining pass/fail condition of memories facilitate array efficiencies. In at least one embodiment, a set of common lines, one for...
Dynamic program window determination in a memory device
A memory device has an array of memory cells and a controller coupled to the array of memory cells. The controller is configured to determine a program window...
Methods applying a non-zero voltage differential across a memory cell not
involved in an access operation
Methods applying a non-zero voltage differential across a memory cell not involved in an access operation can facilitate improved data retention characteristics.
Apparatuses and methods for unit identification in a master/slave memory
Apparatuses and methods including a plurality of memory units are disclosed. An example apparatus includes a plurality of memory units. Each of the plurality of...
System and method of command based and current limit controlled memory
device power up
Devices and systems for powering up a memory device, for example, are disclosed. One such memory device includes power up circuitry configured to receive an...
High-speed wireless serial communication link for a stacked device
configuration using near field coupling
A memory module houses stacked memory devices and a memory controller each having a near-field interface coupled to loop antennas to communicate over-the-air...
Methods and devices for programming a state machine engine
A state machine engine having a program buffer. The program buffer is configured to receive configuration data via a bus interface for configuring a state...
System and method for processor with predictive memory retrieval assist
A system and method are described for a memory management processor which, using a table of reference addresses embedded in the object code, can open the...
Memory cells, integrated devices, and methods of forming memory cells
Some embodiments include integrated devices, such as memory cells. The devices may include chalcogenide material, an electrically conductive material over the...
Phase change memory cells including nitrogenated carbon materials, and
A phase change memory cell comprising a first chalcogenide compound on a first electrode, a first nitrogenated carbon material directly on the first...
High-voltage solid-state transducers and associated systems and methods
High-voltage solid-state transducer (SST) devices and associated systems and methods are disclosed herein. An SST device in accordance with a particular...
Semiconductor device and semiconductor memory devices having first,
second, and third insulating layers
Disclosed herein is a device that includes: a semiconductor substrate; a first insulating layer over a surface of the semiconductor substrate; first and second...
Microelectronic device packages, stacked microelectronic device packages,
and methods for manufacturing...
A stackable microelectronic package includes a first microelectronic die attached to and electrically connecting with a first substrate. A second ...