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Patent # Description
US-7,256,450 NROM memory device with a high-permittivity gate dielectric formed by the low temperature oxidation of metals
A high permittivity gate dielectric formed by low temperature metal oxidation is used in an NROM memory cell. The gate dielectric has a dielectric constant...
US-7,256,138 Method and composition for selectively etching against cobalt silicide
An etching method for use in integrated circuit fabrication includes providing a metal nitride layer on a substrate assembly, providing regions of cobalt...
US-7,256,123 Method of forming an interface for a semiconductor device
In a semiconductor device using a polysilicon contact, such as a poly plug between a transistor and a capacitor in a container cell, an interface is provided...
US-7,256,116 Method for fabricating semiconductor components having encapsulated, bonded, interconnect contacts on...
A method for fabricating a semiconductor component includes the steps of providing a semiconductor die, forming a plurality of redistribution contacts on the...
US-7,256,115 Asymmetric plating
A method and apparatus are disclosed for forming a tapered contact structure over a contact pad. The tapered contact structure may be used to securely anchor an...
US-7,256,074 Methods for wafer-level packaging of microelectronic devices and microelectronic devices formed by such methods
Methods for packaging microelectronic devices, microelectronic workpieces having packaged dies, and microelectronic devices are disclosed herein. One aspect of...
US-7,256,069 Wafer-level package and methods of fabricating
A carrier for use in a chip-scale package, including a polymeric film with apertures defined therethrough. The apertures, which are alignable with corresponding...
US-7,256,068 Semiconductor package assembly and method for electrically isolating modules
A semiconductor package assembly and method for electrically isolating modules, having a capacitor within the semiconductor package assembly. The package...
US-7,255,803 Method of forming contact openings
The invention includes etching and contact opening forming methods. In one implementation, a plasma etching method includes providing a bottom powered plasma...
US-7,255,802 Tape substrate and method for fabricating the same
A method for fabricating a tape substrate includes forming, on an insulating film, a copper foil pattern having a connecting area; coating a solder resist on the...
US-7,255,630 Methods of manufacturing carrier heads for polishing micro-device workpieces
Carrier assemblies, polishing machines with carrier assemblies, and methods for mechanical and/or chemical-mechanical polishing of micro-device workpieces are...
US-7,255,273 Descriptor for identifying a defective die site
The present invention relates to the marking and identification of defective die sites on a mounting substrate. A mounting substrate is provided which is...
US-7,255,128 System and method for detecting flow in a mass flow controller
Systems and methods are provided for detecting flow in a mass flow controller (MFC). The position of a gate in the MFC is sensed or otherwise determined to...
US-RE39,768 VCC pump for CMOS imagers
A CMOS imaging device which includes a charge pump connected to one or more of a reset gate, transfer gate and row select gate of sensor cells and provides gate...
US-7,254,756 Data compression read mode for memory testing
A first series combination of bit match circuits compares a predetermined bit position in data words that are involved in a compression operation. The first...
US-7,254,753 Circuit and method for configuring CAM array margin test and operation
A test circuit for a content addressable memory (CAM) match detection circuit that permits testing of the margin of the match detection circuit. By applying...
US-7,254,331 System and method for multiple bit optical data transmission in memory systems
The disclosed system and method data increases data transmission speed through a memory system by using optical signals comprising a plurality of wavelengths of...
US-7,254,281 Method and apparatus for electronic image processing
A method and apparatus for electronic image processing are described. One embodiment includes a method of resizing an electronic image that includes image data...
US-7,254,074 Open digit line array architecture for a memory array
A system and method for sensing a data state stored by a memory cell that includes coupling a first digit line and a second digit line to a precharge voltage and...
US-7,254,067 Memory device and method having low-power, high write latency mode and high-power, low write latency mode...
A logic circuit operates write receivers in a dynamic random access memory device in either a low-power mode, high write latency mode or a high-power mode, low...
US-7,254,049 Method of comparison between cache and data register for non-volatile memory
A non-volatile memory device and data comparison circuit are described that facilitate the comparison of data between two blocks of data, such as the I/O buffer...
US-7,253,957 Integrated optics units and methods of manufacturing integrated optics units for use with microelectronic imagers
Microelectronic imagers, optical devices for microelectronic imagers, methods for manufacturing integrated optical devices for use with microelectronic imagers,...
US-7,253,737 Automated antenna trim for transmitting and receiving semiconductor devices
A radio frequency communication device and methods of testing and tuning an antenna attached thereto are disclosed. A radio frequency communication device...
US-7,253,715 Secure cargo transportation system
A method of controlling access to a movable container, the method comprising controllably locking the container using an electronically actuated locking...
US-7,253,672 System and method for reduced power open-loop synthesis of output clock signals having a selected phase...
A signal generating circuit includes a pulse generator generating a pulse responsive to a periodic clock reference signal. The pulse propagates through a...
US-7,253,668 Delay-locked loop with feedback compensation
A delay-locked loop (DLL) with feedback compensation is provided to increase the speed and accuracy of the DLL. After the variable delay line of the DLL is...
US-7,253,655 Output driver robust to data dependent noise
Techniques for controlling a driver to reduce data dependent noise, such as simultaneous switching effects and cross-talk effects. A plurality of drivers may...
US-7,253,608 Planarity diagnostic system, e.g., for microelectronic component test systems
Maintaining proper planarity of elements of a microelectronic component test system helps ensure reliable operation of the test system. Aspects of the invention...
US-7,253,521 Methods for making integrated-circuit wiring from copper, silver, gold, and other metals
Integrated circuits include networks of electrical components that are typically wired, or interconnected, together with aluminum wires. In recent years,...
US-7,253,493 High density access transistor having increased channel width and methods of fabricating such devices
A memory device having decreased cell size and having transistors with increased channel widths. More specifically, pillars are formed in a substrate such that...
US-7,253,469 Flash memory device having a graded composition, high dielectric constant gate insulator
A graded composition, high dielectric constant gate insulator is formed between a substrate and floating gate in a flash memory cell transistor. The gate...
US-7,253,464 Junction-isolated depletion mode ferroelectric memory devices and systems
Depletion-mode ferroelectric transistors are adapted for use as non-volatile memory cells for memory devices and electronic systems. Various embodiments are...
US-7,253,430 Controllable ovonic phase-change semiconductor memory device
An ovonic phase-change semiconductor memory device having a reduced area of contact between electrodes of chalcogenide memories, and methods of forming the same...
US-7,253,428 Apparatus and method for feature edge detection in semiconductor processing
A system for identifying a mark or other recess formed in a substrate and at least partially covered by at least one layer of opaque or visibly opaque material....
US-7,253,397 Packaged microelectronic imagers and methods of packaging microelectronic imagers
Microelectronic imagers and methods of packaging microelectronic imagers are disclosed herein. In one embodiment, a microelectronic imager can include a...
US-7,253,392 Image sensor with photo diode gate
A photodiode has a photodiode gate structure on the surface of the substrate. The photodiode may be located in a pixel sensor cell comprising a substrate having...
US-7,253,390 Methods for packaging microelectronic imagers
Microelectronic imagers with prefabricated housings and methods of packaging microelectronic imagers are disclosed herein. In one embodiment, a microelectronic...
US-7,253,122 Systems and methods for forming metal oxides using metal diketonates and/or ketoimines
A method of forming (and an apparatus for forming) a metal oxide layer on a substrate, particularly a semiconductor substrate or substrate assembly, using a...
US-7,253,118 Pitch reduced patterns relative to photolithography features
Differently-sized features of an integrated circuit are formed by etching a substrate using a mask which is formed by combining two separately formed patterns....
US-7,253,117 Methods for use of pulsed voltage in a plasma reactor
A method and apparatus for providing a positive voltage spike to a semiconductor substrate pedestal during a portion of a high voltage power bias oscillation...
US-7,253,104 Methods of forming particle-containing materials
The invention includes methods of forming particle-containing materials, and also includes semiconductor constructions comprising particle-containing materials....
US-7,253,102 Methods for forming and integrated circuit structures containing enhanced-surface-area conductive layers
An enhanced-surface-area conductive layer compatible with high-dielectric constant materials is created by forming a film or layer having at least two phases, at...
US-7,253,089 Microfeature devices and methods for manufacturing microfeature devices
Microfeature devices, microfeature workpieces, and methods for manufacturing microfeature devices and microfeature workpieces are disclosed herein. The...
US-7,253,085 Deposition methods
The invention includes a method for selective deposition of semiconductor material. A substrate is placed within a reaction chamber. The substrate comprises a...
US-7,253,076 Methods for forming and integrated circuit structures containing ruthenium and tungsten containing layers
Capacitors having increased capacitance include an enhanced-surface-area (rough-surfaced) electrically conductive layer or other layers that are compatible with...
US-7,253,064 Cascode I/O driver with improved ESD operation
A cascode I/O driver is described that includes a barrier formed in the shared region between the two transistors. The barrier region allows the I/O driver to be...
US-7,253,053 Methods of forming transistor devices and capacitor constructions
The invention includes methods of forming circuit devices. A metal-containing material comprising a thickness of no more than 20 .ANG. (or alternatively...
US-7,253,052 Method for forming a storage cell capacitor compatible with high dielectric constant materials
Described are integrated circuit electrodes and method for fabricating an electrode, which include, in an embodiment forming a silicon, first portion of the...
US-7,253,047 Semiconductor processing methods of forming transistors, semiconductor processing methods of forming dynamic...
Semiconductor processing methods of forming transistors, semiconductor processing methods of forming dynamic random access memory circuitry, and related...
US-7,253,025 Multiple substrate microelectronic devices and methods of manufacture
A microelectronic device and method for manufacture. In one embodiment, two microelectronic substrates are directly bonded to each other without an intermediate...
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