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Patent # Description
US-7,250,687 Systems for degating packaged semiconductor devices with tape substrates
A system for degating a packaged semiconductor device that includes a tape substrate includes a first element and a second element. The first element of the...
US-7,250,680 Semiconductor circuitry constructions
The invention includes a method of forming semiconductor circuitry wherein a first semiconductor structure comprising a first monocrystalline semiconductor...
US-7,250,663 Frame scale package using contact lines through the elements
A package for an integrated circuit contacting device which is shaped like a frame. A portion of the contacting device may be bonded to the printed circuit...
US-7,250,647 Asymmetrical transistor for imager device
An imager device that has mitigated dark current leakage and punch-through protection. The transistor associated with the photoconversion device is formed with a...
US-7,250,628 Memory devices and electronic systems comprising thyristors
The invention includes SOI constructions containing one or more memory cells which include a transistor and a thyristor. In one aspect, a scalable GLTRAM cell...
US-7,250,591 Photonic crystal-based filter for use in an image sensor
The invention, in various exemplary embodiments, incorporates a photonic crystal filter into an image sensor. The photonic crystal filter comprises a substrate...
US-7,250,380 Method of depositing a silicon dioxide-comprising layer in the fabrication of integrated circuitry
This invention includes methods of depositing a silicon dioxide comprising layer in the fabrication of integrated circuitry, and to methods of forming trench...
US-7,250,378 Method of depositing a silicon dioxide-comprising layer in the fabrication of integrated circuitry
This invention includes methods of depositing a silicon dioxide comprising layer in the fabrication of integrated circuitry, and to methods of forming trench...
US-7,250,367 Deposition methods using heteroleptic precursors
An ALD method includes exposing a substrate to a first precursor including a plurality of different ligands, chemisorbing a precursor monolayer on the substrate,...
US-7,250,338 Scalable Flash/NV structures and devices with extended endurance
Devices and methods are provided with respect to a gate stack for a nonvolatile structure. According to one aspect, a gate stack is provided. One embodiment of...
US-7,250,328 Microelectronic component assemblies with recessed wire bonds and methods of making same
The present disclosure suggests various microelectronic component assembly designs and methods for manufacturing microelectronic component assemblies. In one...
US-7,250,321 Method of forming a photosensor
A trench photosensor for use in a CMOS imager having an improved charge capacity. The trench photosensor may be either a photogate or photodiode structure. The...
US-7,250,247 Photolithographic structures using multiple anti-reflecting coatings
A method for fabricating an integrated circuit using a photo-lithographic process includes the steps of placing at least two anti-reflective coating layers...
US-7,249,236 Method and system for controlling memory accesses to memory modules having a memory hub architecture
A computer system includes a memory hub controller coupled to a plurality of memory modules. The memory hub controller includes a memory request queue that...
US-7,248,532 Device, system and method for reducing power in a memory device during standby modes
A memory device responsive to standby mode commands for reducing internal operational power on a memory device is disclosed. The memory device includes a circuit...
US-7,248,521 Negative voltage discharge scheme to improve snapback in a non-volatile memory
Charge pump and discharge circuitry for a non-volatile memory device that splits up the discharge operation into two discharge periods. In a first discharge...
US-7,248,516 Data compression read mode for memory testing
Memory devices having a normal mode of operation and a test mode of operation are useful in quality programs. The test mode of operation includes a data...
US-7,248,515 Non-volatile memory with test rows for disturb detection
A non-volatile memory device has an array of memory cells arranged in rows and columns. The memory cells can be externally accessed for programming, erasing and...
US-7,248,499 Layout for NAND flash memory array having reduced word line impedance
A memory array including a first region in which a first memory sub-array is located and a second region separated from the first region in which a second memory...
US-7,248,498 Serial transistor-cell array architecture
A memory device having memory cells in which a single access transistor controls the grounding of at least four storage elements, such as resistive storage...
US-7,248,407 Microlens array sheet of projection screen, and method for manufacturing the same
The present invention discloses a microlens array sheet of a projection screen including a lens sheet having a predetermined area, microlenses arranged on one...
US-7,248,088 Devices and methods for controlling a slew rate of a signal line
In one aspect of the invention, a method of reducing intersymbol interference on a signal line is disclosed. A state machine records previous bits that were...
US-7,248,063 Plasma probe systems
A plasma probe system includes a plasma probe, at least one meter, and a diagnostic apparatus. The probe may include a substrate having substantially the same...
US-7,247,987 Rear plate for plasma display panel
Disclosed is a rear plate of a plasma display panel. In the rear plate, a dielectric layer or a barrier wall layer is formed by forming slurry in a tape of a...
US-7,247,944 Connector assembly
An apparatus and method for attaching a semiconductor die to a lead frame wherein the electric contact points of the semiconductor die are relocated to the...
US-7,247,927 Leadframe alteration to direct compound flow into package
A leadframe comprising a downset formed adjacent to an edge of the leadframe so as to direct the molding compound to flow evenly inside the mold cavity. The...
US-7,247,920 Method of composite gate formation
Methods for forming a nitride barrier film layer in semiconductor devices such as gate structures, and barrier layers, semiconductor devices and gate electrodes...
US-7,247,919 Method and device to reduce gate-induced drain leakage (GIDL) current in thin gate oxides MOSFETs
An integrated circuit which provides a FET device having reduced GIDL current is described. A semiconductor substrate is provided wherein active regions are...
US-7,247,836 Method and system for determining motion based on difference image correlation
An imager captures successive images of an object. One image is then subtracted from another image to generate difference images. Each difference image is then...
US-7,247,831 Reduction in size of column sample and hold circuitry in a CMOS imager
Improved column sample-and-hold (CSH) circuitry particularly useful in a CMOS imager is disclosed. In the improved circuitry layout, the overall column height of...
US-7,247,584 System and method for selectively increasing surface temperature of an object
A system and method for selectively increasing the thermal effect of a radiant energy source to the surface of an object relative to the substrate is described...
US-7,247,581 Methods for treating pluralities of discrete semiconductor substrates
The invention includes a method for treating a plurality of discrete semiconductor substrates. The discrete semiconductor substrates are placed within a reactor...
US-7,247,570 Silicon pillars for vertical transistors
In order to form a more stable silicon pillar which can be used for the formation of vertical transistors in DRAM cells, a multi-step masking process is used. In...
US-7,247,561 Method of removing residual contaminants from an environment
A method of reducing the amount of halogenated materials in a halogen-containing environment. The method comprises introducing an aluminum compound into the...
US-7,247,521 Semiconductor assembly encapsulation mold and method for forming same
An encapsulation mold for forming an encapsulation layer over a semiconductor assembly is disclosed. A semiconductor assembly with multiple semiconductor dies...
US-7,247,520 Microelectronic component assemblies and microelectronic component lead frame structures
The present invention provides microelectronic component assemblies and lead frame structures that may be useful in such assemblies. For example, one such lead...
US-7,247,492 Method for observing chemical substances
An apparatus and method for observing a chemical substance. In one embodiment, the apparatus includes a vessel having a base portion and an at least partially...
US-7,247,227 Buffer layer in flat panel display
In devices such as flat panel displays, an aluminum oxide layer is provided between an aluminum layer and an ITO layer when such materials would otherwise be in...
US-D547,305 Speaker for vehicle
US-7,245,785 Suppression of ringing artifacts during image resizing
An economical method of detecting and suppressing ringing artifacts during digital image resizing is presented. The economical method substitutes costly division...
US-7,245,553 Memory system and method for strobing data, command and address signals
A memory system couples command, address or write data signals from a memory controller to a memory device and read data signals from the memory device to the...
US-7,245,551 Read command triggered synchronization circuitry
A memory READ command triggered clock synchronization mode turns on a clock synchronization circuit only for memory READ operations. The clock synchronization...
US-7,245,550 Memory array decoder
An apparatus and method for selecting a storage location in a memory device including receiving at least one of a pre-decoded location address signal, a match...
US-7,245,548 Techniques for reducing leakage current in memory devices
Techniques for reducing gate induced drain leakage (GIDL) in memory devices utilizing negative wordline architectures. More specifically, a method and apparatus...
US-7,245,541 Active termination control
A method and apparatus are provided for active termination control in a memory by an module register providing an active termination control signal to the...
US-7,245,540 Controller for delay locked loop circuits
A method of controlling a delay locked loop (DLL) in a memory device is provided. The DLL generates an internal clock signal based on an external clock signal....
US-7,245,538 High voltage generation and regulation circuit in a memory device
An auxiliary voltage generation circuit is part of a high voltage generation and regulation circuit. The auxiliary voltage generation circuit generates an...
US-7,245,321 Readout circuit with gain and analog-to-digital conversion for image sensor
A CMOS imager includes an array of active pixel sensors, wherein each pixel is associated with a respective column in the array. The imager also includes...
US-7,245,320 Method and apparatus for automatic gain and exposure control for maintaining target image brightness in video...
In an image processing system, the imager gain and the exposure time are adjusted based on a predefined stepping sequence using a stepping table designed to...
US-7,245,300 Architecture for real-time texture look-up's for volume rendering
A slice plane, oriented parallel to a viewing plane, is passed through a cuboidal dataset at regular intervals. The intersection of the slice plane with the...
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