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Patent # Description
US-7,245,785 Suppression of ringing artifacts during image resizing
An economical method of detecting and suppressing ringing artifacts during digital image resizing is presented. The economical method substitutes costly division...
US-7,245,553 Memory system and method for strobing data, command and address signals
A memory system couples command, address or write data signals from a memory controller to a memory device and read data signals from the memory device to the...
US-7,245,551 Read command triggered synchronization circuitry
A memory READ command triggered clock synchronization mode turns on a clock synchronization circuit only for memory READ operations. The clock synchronization...
US-7,245,550 Memory array decoder
An apparatus and method for selecting a storage location in a memory device including receiving at least one of a pre-decoded location address signal, a match...
US-7,245,548 Techniques for reducing leakage current in memory devices
Techniques for reducing gate induced drain leakage (GIDL) in memory devices utilizing negative wordline architectures. More specifically, a method and apparatus...
US-7,245,541 Active termination control
A method and apparatus are provided for active termination control in a memory by an module register providing an active termination control signal to the...
US-7,245,540 Controller for delay locked loop circuits
A method of controlling a delay locked loop (DLL) in a memory device is provided. The DLL generates an internal clock signal based on an external clock signal....
US-7,245,538 High voltage generation and regulation circuit in a memory device
An auxiliary voltage generation circuit is part of a high voltage generation and regulation circuit. The auxiliary voltage generation circuit generates an...
US-7,245,321 Readout circuit with gain and analog-to-digital conversion for image sensor
A CMOS imager includes an array of active pixel sensors, wherein each pixel is associated with a respective column in the array. The imager also includes...
US-7,245,320 Method and apparatus for automatic gain and exposure control for maintaining target image brightness in video...
In an image processing system, the imager gain and the exposure time are adjusted based on a predefined stepping sequence using a stepping table designed to...
US-7,245,300 Architecture for real-time texture look-up's for volume rendering
A slice plane, oriented parallel to a viewing plane, is passed through a cuboidal dataset at regular intervals. The intersection of the slice plane with the...
US-7,245,145 Memory module and method having improved signal routing topology
A registered memory module includes several memory devices coupled to a register through a plurality of transmission lines forming a symmetrical tree topology....
US-7,245,136 Methods of processing a workpiece, methods of communicating signals with respect to a wafer, and methods of...
An electronic device workpiece processing apparatus and method of communicating signals within an electronic device workpiece processing apparatus are provided....
US-7,245,010 System and device including a barrier layer
Systems and devices are disclosed utilizing a silicon-containing barrier layer. A semiconductor device is disclosed and includes a substrate, a gate oxide, a...
US-7,244,987 NROM flash memory devices on ultrathin silicon
An NROM flash memory cell is implemented in an ultra-thin silicon-on-insulator structure. In a planar device, the channel between the source/drain areas is...
US-7,244,981 Scalable high performance non-volatile memory cells using multi-mechanism carrier transport
A plurality of select gates are formed over a substrate. In one embodiment, the select gates are formed vertically on the sidewalls of trenches. The substrate...
US-7,244,918 Method and apparatus providing a two-way shared storage gate on a four-way shared pixel
A method of operating a pixel array includes activating a global storage signal to store a photosensor charge in a first storage region of each pixel, activating...
US-7,244,682 Methods of removing metal-containing materials
Various methods for selectively etching metal-containing materials (such as, for example, metal nitrides, which can include, for example, titanium nitride)...
US-7,244,681 Methods for selective removal of material from wafer alignment marks
A process and apparatus for locally removing any material, such as a refractory metal, in particular tungsten, from any desired area of a wafer, such as an...
US-7,244,678 Methods for planarization of Group VIII metal-containing surfaces using complexing agents
A planarization method includes providing a second and/or third row Group VIII metal-containing surface (preferably, a platinum-containing surface) and...
US-7,244,665 Wafer edge ring structures and methods of formation
An elevated containment structure in the shape of a wafer edge ring surrounding a surface of a semiconductor wafer is disclosed, as well as methods of forming...
US-7,244,663 Wafer reinforcement structure and methods of fabrication
A method of fabricating a thinned, reinforced semiconductor wafer is disclosed. Particularly, a semiconductor wafer may be provided and a plurality of separate...
US-7,244,659 Integrated circuits and methods of forming a field effect transistor
Integrated circuits and methods of forming field effect transistors are disclosed. In one aspect, an integrated circuit includes a semiconductor substrate...
US-7,244,648 Methods of forming semiconductor constructions
The invention encompasses a method of forming a silicon nitride layer. A substrate is provided which comprises a first mass and a second mass. The first mass...
US-7,244,646 Pixel design to improve photodiode capacitance and method of forming same
A CMOS imager with two adjacent pixel active area regions without the presence of an intervening trench isolation region that typically separates two adjacent...
US-7,244,637 Chip on board and heat sink attachment methods
A process for forming a thermally enhanced Chip On Board semiconductor device with a heat sink is described. In one aspect, a thermally conductive-filled gel...
US-7,243,290 Data encoding for fast CAM and TCAM access times
A method and apparatus for operating a content addressable memory (CAM) and a ternary CAM (TCAM) are described including an encoding circuit for encoding an...
US-7,242,603 Method of operating a complementary bit resistance memory sensor
The present invention relates to a method and apparatus for sensing the resistance state of a programmable resistance memory, using complementary memory...
US-7,242,332 Column-parallel sigma-delta analog-to-digital conversion with gain and offset control
A sigma-delta modulation sensing circuit and an analog-to-digital converter for an imager that eliminate the erroneous conversion of non-zero analog voltages to...
US-7,242,213 Memory module and method having improved signal routing topology
A registered memory module includes several memory devices coupled to a register through a plurality of transmission lines forming a symmetrical tree topology....
US-7,242,067 MRAM sense layer isolation
A process for forming an MRAM element. The process comprises patterning a globally deposited sense layer and then forming a spacer about the patterned sense...
US-7,242,057 Vertical transistor structures having vertical-surrounding-gates with self-aligned features
The present inventions include a vertical transistor formed by defining a channel length of the vertical-surrounding-gate field effect transistor with...
US-7,242,049 Memory device
A floating gate transistor has a reduced barrier energy at an interface with an adjacent gate insulator, allowing faster charge transfer across the gate...
US-7,241,705 Methods of forming conductive contacts to source/drain regions and methods of forming local interconnects
The invention comprises methods of forming a conductive contact to a source/drain region of a field effect transistor, and methods of forming local...
US-7,241,673 Methods of forming silicon-doped aluminum oxide, and methods of forming transistors and memory devices
The invention encompasses a method of forming a silicon-doped aluminum oxide. Aluminum oxide and silicon monoxide are co-evaporated. Subsequently, at least some...
US-7,241,662 Reduction of field edge thinning in peripheral devices
A dielectric layer (e.g., an interpoly dielectric layer) is deposited over low and high voltage devices of a peripheral memory device. The dielectric behaves as...
US-7,241,661 Method of forming a coupling dielectric Ta.sub.2O.sub.5 in a memory device
A method of forming a coupling dielectric in a memory cell includes forming an oxide on a substrate, forming Ta.sub.2O.sub.5 on the oxide, oxidizing the...
US-7,241,658 Vertical gain cell
A high density vertical gain cell is realized for memory operation. The gain cell includes a vertical MOS transistor used as a sense transistor having a floating...
US-7,241,655 Method of fabricating a vertical wrap-around-gate field-effect-transistor for high density, low voltage logic...
A vertical transistor having a wrap-around-gate and a method of fabricating such a transistor. The wrap-around-gate (WAG) vertical transistors are fabricated by...
US-7,241,654 Vertical NROM NAND flash memory array
Memory devices, arrays, and strings are described that facilitate the use of NROM memory cells in NAND architecture memory strings, arrays, and devices. NROM...
US-D546,275 Electroacoustic transducer
US-D546,274 Electroacoustic transducer
US-7,240,316 Apparatus and method to facilitate hierarchical netlist checking
An apparatus and method are disclosed which determine locations where verification data should exist in a circuit representation and then propagates verification...
US-7,240,148 Parity-scanning and refresh in dynamic memory devices
A method and apparatus that coordinates refresh and parity-scanning in DRAM-based devices such that parity-scan operations substitute for refresh operations when...
US-7,240,147 Memory decoder and data bus for burst page read
Memory device is described that utilizes a reduced number of sense amplifiers to sense the data bits of a selected column page. The sense amplifiers are...
US-7,240,146 Random access interface in a serial memory device
A random access interface is provided to a non-volatile, serial memory array. An address multiplexer has an external address connection and a serial address...
US-7,239,933 Substrate supports for use with programmable material consolidation apparatus and systems
A programmed material consolidation apparatus includes at least one fabrication site and a material consolidation system associated with the at least one...
US-7,239,932 Methods and apparatus for calibrating programmable material consolidation apparatus
A programmed material consolidation apparatus includes at least one fabrication site and a material consolidation system associated with the at least one...
US-7,239,575 Delay-locked loop having a pre-shift phase detector
A clock generator for generating an output clock signal synchronized with an input clock signal having first and second adjustable delay lines. The first...
US-7,239,557 Program method with optimized voltage level for flash memory
A non-volatile memory device and programming process is described that increases the programming voltage of successive programming cycles in relation to the...
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