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Patent # Description
US-7,270,715 Chemical vapor deposition apparatus
A chemical vapor deposition apparatus includes a subatmospheric substrate transfer chamber. A subatmospheric deposition chamber is defined at least in part by a...
US-7,270,596 Chemical mechanical polishing process
A chemical mechanical polishing process includes rotating at least one of a semiconductor substrate and polishing pad relative to the other. A chemical...
US-7,269,898 Method for making an edge intensive antifuse
An antifuse including a bottom plate having a plurality of longitudinal members arranged substantially parallel to a first axis, a dielectric layer formed on the...
US-7,269,765 Method and apparatus for storing failing part locations in a module
A non-volatile storage device on a memory module comprising a plurality of memory devices is used to store the locations of defective parts on the memory module,...
US-7,269,686 Synchronous memory open page register
A memory device includes memory cells arranged in multiple blocks. A register is provided to track multiple open pages per block of the memory. In one...
US-7,269,685 Apparatus and methods for storing data in a magnetic random access memory (MRAM)
An apparatus and methods store data in a magnetic random access memory (MRAM) in a fast and efficient manner. Embodiments advantageously decrease the number of...
US-7,269,094 Memory system and method for strobing data, command and address signals
A memory system couples command, address or write data signals from a memory controller to a memory device and read data signals from the memory device to the...
US-7,269,091 Word line driver circuitry and methods for using the same
Word line driver circuitry for selectively charging and discharging one or more word lines is provided. The driver circuitry uses a dual transistor topology,...
US-7,269,083 Using redundant memory for extra features
An access request for a first memory location of a memory device is received at the memory device. A second memory location is selected in response to the...
US-7,269,079 Power circuits for reducing a number of power supply voltage taps required for sensing a resistive memory
A resistive memory device requires a power supply having a reduced number of voltage taps and reduced power consumption. In accordance with one exemplary...
US-7,269,072 NROM memory cell, memory array, related devices and methods
An array of memory cells configured to store at least one bit per one F.sup.2 includes substantially vertical structures providing an electronic memory function...
US-7,269,071 NROM memory cell, memory array, related devices and methods
An array of memory cells configured to store at least one bit per one F.sup.2 includes substantially vertical structures providing an electronic memory function...
US-7,269,066 Programming memory devices
A target memory cell of a memory device is programmed by applying a programming voltage to a word line that includes the target memory cell, determining whether...
US-7,269,044 Method and apparatus for accessing a memory array
A memory device including first and second memory elements is provided. The first and second memory elements each have first and second electrodes. The first...
US-7,269,042 Memory stacking system and method
A method of forming a stacked memory module from a plurality of memory devices is provided. Each of the plurality of memory devices is modified to include a...
US-7,269,040 Static content addressable memory cell
A static content addressable memory (CAM) cell. The CAM cell includes a latch having complementary data nodes capacitively coupled to ground, first and second...
US-7,268,949 Microlens array sheet and manufacturing method thereof
A microlens array sheet and a manufacturing method thereof. The microlens array sheet comprises: a transparent substrate; bases formed on the transparent...
US-7,268,869 In-situ spectrograph and method of measuring light wavelength characteristics for photolithography
An in-situ spectrograph having a spectrometer module positioned at a reticle plane or at a wafer plane of a photolithography projection system is disclosed. The...
US-7,268,614 Low supply voltage bias circuit, semiconductor device, wafer and system including same, and method of...
A bias generator and a method of generating a bias reference are disclosed. A reference transistor is connected in a diode configuration. An n-channel transistor...
US-7,268,603 Method and apparatus for reducing duty cycle distortion of an output signal
A method and apparatus for reducing the duty cycle distortion of a periodic signal in high speed devices. More specifically, there is provided a device having a...
US-7,268,574 Systems and methods for sensing obstructions associated with electrical testing of microfeature workpieces
Systems and methods for sensing obstructions associated with electrical testing of microfeature workpieces are disclosed. An apparatus in accordance with one...
US-7,268,531 Apparatus for improving stability and lock time for synchronous circuits
Delay-locked loops, signal locking methods and devices and system incorporating delay-locked loops are described. A delay-locked loop includes a forward delay...
US-7,268,482 Preventing junction leakage in field emission devices
An apparatus for stabilizing the threshold voltage in an active matrix field emission device is disclosed. The apparatus includes the formation of...
US-7,268,481 Field emission display with smooth aluminum film
This invention provides a conductive aluminum film and method of forming the same, wherein a non-conductive impurity is incorporated into the aluminum film. In...
US-7,268,413 Bipolar transistors with low-resistance emitter contacts
Many integrated circuits include a type of transistor known as a bipolar junction transistor, which has an emitter contact formed of polysilicon. Unfortunately,...
US-7,268,402 Memory cell with trench-isolated transistor including first and second isolation trenches
An isolation trench in a semiconductor includes a first isolation trench portion having a first depth and having a first sidewall intersecting a surface of the...
US-7,268,388 One-transistor composite-gate memory
One-transistor memory devices facilitate nonvolatile data storage through the manipulation of oxygen vacancies within a trapping layer of a field-effect...
US-7,268,384 Semiconductor substrate having first and second pairs of word lines
The invention includes methods of forming memory circuitry. In one implementation, a semiconductor substrate includes a pair of word lines having a bit node...
US-7,268,382 DRAM cells
The invention includes a method of forming a rugged semiconductor-containing surface. A first semiconductor layer is formed over a substrate, and a second...
US-7,268,078 Chemical vapor deposition of titanium from titanium tetrachloride and hydrocarbon reactants
A process for depositing titanium metal layers via chemical vapor deposition is disclosed. The process provides deposited titanium layers having a high degree of...
US-7,268,072 Method and structure for reducing contact aspect ratios
An intermediate metal plug is used to raise the platform to which contact is to be made. In the illustrated process, a partial bit line plug is formed adjacent a...
US-7,268,067 Semiconductor integrated circuit package having electrically disconnected solder balls for mounting
Integrated circuit packages that connect solder balls between solder ball pads of a die and substrate pads of a printed circuit board (PCB). The solder balls are...
US-7,268,059 Methods for securing components of semiconductor device assemblies to each other with adhesive materials that...
A method for securing a semiconductor device component to another element is provided. An adhesive material includes a pressure-sensitive component and a curable...
US-7,268,057 Methods of filling openings with oxide, and methods of forming trenched isolation regions
The invention includes methods in which oxide is formed within openings in a three-step process. A first step is deposition of oxide under a pressure of greater...
US-7,268,054 Methods for increasing photo-alignment margins
Methods and structures are provided for increasing alignment margins when contacting pitch multiplied interconnect lines with other conductive features in memory...
US-7,268,039 Method of forming a contact using a sacrificial structure
A method of forming a double-sided capacitor using at least one sacrificial structure, such as a sacrificial liner or a sacrificial plug. A sacrificial liner is...
US-7,268,035 Methods of forming semiconductor constructions comprising cerium oxide and titanium oxide
The invention includes semiconductor constructions comprising dielectric materials which contain cerium oxide and titanium oxide. The dielectric materials can...
US-7,268,034 Methods of forming pluralities of capacitors, and integrated circuitry
A method of forming a plurality of capacitors includes providing a plurality of capacitor electrodes comprising sidewalls. The plurality of capacitor electrodes...
US-7,268,031 Memory device with high dielectric constant gate dielectrics and metal floating gates
A memory cell transistor includes a high dielectric constant tunnel insulator, a metal floating gate, and a high dielectric constant inter-gate insulator...
US-7,268,030 Methods of forming semiconductor constructions
Thin film transistor based three-dimensional CMOS inverters utilizing a common gate bridged between a PFET device and an NFET device. One or both of the NFET and...
US-7,268,023 Method of forming a pseudo SOI substrate and semiconductor devices
The present invention is generally directed to a method of forming a pseudo SOI substrate and semiconductor devices. In one illustrative embodiment, the method...
US-7,268,022 Stable PD-SOI devices and methods
One aspect of the present subject matter relates to a partially depleted silicon-on-insulator structure. The structure includes a well region formed above an...
US-7,268,018 Method for fabricating semiconductor component with stiffener and circuit decal
A semiconductor component includes a stiffener, a circuit decal attached to the stiffener, and a semiconductor die attached to the stiffener. The circuit decal...
US-7,268,013 Method of fabricating a semiconductor die package having improved inductance characteristics
A ball grid array (BGA) package that includes a central cavity for receiving a semiconductor die therein is disclosed. The die rests on a base laminate, the die...
US-7,268,012 Methods for fabrication of thin semiconductor assemblies including redistribution layers and packages and...
Methods for creating redistribution layers for only selected dice, such as known good dice, to form relatively thin semiconductor component assemblies and...
US-7,268,004 Thermoelectric control for field emission display
An active matrix display that does not require a transistor or similar current switching device at each pixel. Instead, the display employs in each pixel a...
US-7,267,999 MRAM layer having domain wall traps
A common pinned layer is shared by multiple memory cells in an MRAM device. The common pinned layer includes a plurality of domain wall traps that prevent the...
US-7,267,608 Method and apparatus for conditioning a chemical-mechanical polishing pad
A conditioner including abrasive elements for conditioning a polishing pad to be used in abrasive semiconductor substrate treatment processes, such as...
US-7,266,879 Method for magnetically establishing an electrical connection with a contact of a semiconductor device component
A method for establishing electrical contact includes nonrigidly applying force to a semiconductor substrate in directions substantially normal to a plane of the...
US-7,266,633 System and method for communicating the synchronization status of memory modules during initialization of the...
A memory system includes a memory hub controller coupled to a plurality of memory modules each of which includes a memory hub. The memory hub controller and the...
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