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Chip scale package with heat spreader
A dense semiconductor flip-chip device assembly is provided with a heat sink/spreading/dissipating member that is formed as a paddle of a metallic paddle frame...
Transistor with nitrogen-hardened gate oxide
An improved surface P-channel transistor includes providing a semiconductor substrate, forming a gate oxide layer over the semiconductor substrate, subjecting...
Method of forming inside rough and outside smooth HSG electrodes and
A container capacitor and method of forming the container capacitor are provided. The container capacitor comprises a lower electrode fabricated by forming a...
Self masking contact using an angled implant
A method of implanting, for example, a phosphorous plug over a charge collection region and a method of forming a contact over the phosphorous plug implant and...
Microelectronic devices and methods for forming interconnects in
Microelectronic devices, methods for packaging microelectronic devices, and methods for forming interconnects in microelectronic devices are disclosed herein. In...
Method of wafer bumping for enabling a stitch wire bond in the absence of
discrete bump formation
A method of bumping a wafer for facilitating bonding of bond wires to elevate the bond location above the passivation layer. The wafer is bumped by disposing the...
High quality oxide on an epitaxial layer
This invention improves the quality of gate oxide dielectric layers using a two-pronged approach, thus permitting the use of much thinner silicon dioxide gate...
Structures and methods for enhancing capacitors in integrated circuits
Systems, devices, structures, and methods are described that inhibit dielectric degradation at high temperatures. An enhanced capacitor is discussed. The...
Methods of forming interconnect lines
In one aspect, the invention provides a method of forming an electrical connection in an integrated circuitry device. According to one preferred implementation,...
Printer and print control method
In a printer, an MPU makes a flash ROM store a temperature read by a temperature sensor at the time of setting of a correction value and a misalignment...
Fast data access mode in a memory device
A fast data access circuit that has both a standard clock mode and a fast data access mode. The mode is selectable through a mode/configuration register. A...
Erase verify for non-volatile memory using bitline/reference
A memory device verify system determines a state of memory cells in a memory. The memory includes a memory array having a plurality of memory cells coupled to...
User configurable commands for flash memory
A memory device includes a plurality of memory dies, each having an assigned address. A register on each die is reset on power-up. Boot data is loaded as part of...
Vertical NROM having a storage density of 1 bit per 1F2
The multiple bit, vertical memory cell includes a vertical metal oxide semiconductor field effect transistor (MOSFET) extending horizontally outward from a...
Method and apparatus for controlling radiation beam intensity directed to
A method and apparatus for controlling an intensity distribution of a radiation beam directed to a microlithographic substrate. The method can include directing...
Method of operating a CMOS APS pixel sensor
A method of operating a CMOS imager is presented wherein a reset transistor source/drain of a first pixel is biased with a first voltage source, a source...
Programmable integrating ramp generator and method of operating the same
A ramp generator for an analog-to-digital converter comprises an array of capacitors each controlled by a switch responsive to one or more control signals and...
Method and system for identifying lost or stolen devices
A method and system for identifying a lost or stolen device is disclosed herein. The system includes: a transmitter, coupled to said device, for transmitting...
Phase-locked loop circuits with reduced lock time
PLL circuits are provided in which a voltage-controlled oscillator (VCO) comprising one or more voltage-controlled delay units (VCDs) is initialized with the...
Low voltage CMOS differential amplifier
A low voltage CMOS differential amplifier is provided. More specifically, there is provided a device comprising a differential pair coupled to a first tail...
Technique to improve the gain and signal to noise ratio in CMOS switched
The present invention comprises switched capacitor amplifiers including positive feedback, semiconductor devices, wafers and systems incorporating same and...
Programmable dual drive strength output buffer with a shared boot circuit
An integrated circuit device is discussed that includes a data output driver having two modes of operation for driving a data bus. The output driver includes a...
High density memory array having increased channel widths
A memory array having decreased cell sizes and having transistors with increased channel widths. More specifically, pillars are formed in a substrate such that...
Semiconductor die packages with recessed interconnecting structures
Apparatus and methods relating to semiconductor assemblies. A semiconductor assembly includes an interposer which may be constructed from a flexible material,...
Transistor having vertical junction edge and method of manufacturing the
Techniques for forming devices, such as transistors, having vertical junction edges. More specifically, shallow trenches are formed in a substrate and filled...
Stud electrode and process for making same
A process of making a stud capacitor structure is disclosed. The process includes embedding the stud in a dielectric stack. In one embodiment, the process...
Surface barriers for copper and silver interconnects produced by a
A semiconductor device structure having a barrier layer comprising a conductive portion and a nonconductive portion is disclosed. The conductive portion includes...
Alignment and orientation features for a semiconductor package
A semiconductor device formed by an automated wire bonding system. The semiconductor device comprises a lead frame having a plurality of lead fingers and a die...
Memory array buried digit line
A method of forming a buried digit line is disclosed. Sacrificial spacers are formed along the sidewalls of an isolation trench, which is then filled with a...
Forming integrated circuits using selective deposition of undoped silicon
film seeded in chlorine and hydride gas
A polysilicon film is formed with enhanced selectivity by flowing chlorine during the formation of the film. The chlorine acts as an etchant to insulative areas...
Methods of making semiconductor-on-insulator thin film transistor
The invention includes SOI thin film transistor constructions, memory devices, computer systems, and methods of forming various structures, devices and systems....
Methods for improving angled line feature accuracy and throughput using
electron beam lithography and electron...
Methods to reduce the write time for forming mask patterns having angled and non-angled features using electron beam lithography are disclosed. In one exemplary...
Method to recover the exposure sensitivity of chemically amplified resins
from post coat delay effect
Methods of fabricating a photomask, methods of treating a chemically amplified resist-coated photomask blank, a photomask blank resulting from the methods, and...
Reticles and methods of forming and using the same
Reticles having reticle patterns suitable for reducing edge of array effects are provided. The reticle patterns have unresolvable patterns formed in the...
Chemical vapor deposition method
Methods of chemical vapor deposition include providing a deposition chamber defined at least in part by at least one of a chamber sidewall and a chamber base...
Apparatuses and methods for in-situ optical endpointing on web-format
planarizing machines in mechanical or...
Planarizing machines, planarizing pads, and methods for planarizing or endpointing mechanical and/or chemical-mechanical planarization of microelectronic...
Apparatus and method for conditioning and monitoring media used for
A method and apparatus for conditioning and monitoring a planarizing medium used for planarizing a microelectronic substrate. In one embodiment, the apparatus...
Write address synchronization useful for a DDR prefetch SDRAM
Disclosed herein are exemplary embodiments of an improved write address shift register structure useful for example in a DDR3 DRAM having read/write latency. The...
Clock generator having a delay locked loop and duty cycle correction
circuit in a parallel configuration
A clock generator having a delay locked loop and a duty cycle correction circuit. The delay locked loop adjusts a first adjustable delay circuit to generate a...
High speed wordline decoder for driving a long wordline
A method and apparatus for improving the performance of a memory wordline decoder is disclosed. A decoder latch is attached to an inverter which drives the...
Noise suppression in memory device sensing
NAND memory devices utilize sensing devices for sensing a programmed state of a nonvolatile memory cell or writing a data value to a nonvolatile memory cell....
Voltage translator for multiple voltage operations
A method and apparatus is provided for a voltage translator for performing a voltage-level translation of a signal. The voltage translator of the present...
Method and apparatus for filtering output data
Apparatus and methods for filtering spurious output transitions with an adaptive filtering circuit which tracks the memory architecture and form factors with a...
Method for erasing an NROM cell
An operation to erase a nitride read only memory (NROM) memory block starts by erasing the memory block. An erase verify operation can then be performed to...
Mode selection in a flash memory device
A single flash memory device has selectable read modes for either a segment mode or a page mode. The desired mode is selected by writing a control word to a mode...
MRAM integrated circuits, MRAM circuits, and systems for testing MRAM
An integrated circuit includes operational circuitry; a sensor configured to sense an environmental parameter; and adjustment circuitry coupled to the sensor and...
Method and apparatus for balancing color response of imagers
A micro-lens array with reduced or no empty space between individual micro-lenses and a method for forming same. The micro-lens array is formed by patterning a...
System and method for controlling input buffer biasing current
A system and method for controlling input buffer biasing current include an input buffer circuit with an input current detector circuit configured to generate a...
On-chip substrate regulator test mode
An on-chip circuit for defect testing with the ability to maintain a substrate voltage at a level more positive or more negative than a normal negative operating...
Vertical surface mount assembly and methods
A vertically mountable semiconductor device assembly including a semiconductor device and a mechanism for attaching the semiconductor device to a carrier...