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Patent # Description
US-7,265,012 Formation of standard voltage threshold and low voltage threshold MOSFET devices
Wells are formed in a substrate where standard Vt and low Vt devices of both a first and second type are to be fabricated. Wells defining the locations of first...
US-7,264,988 Electro-and electroless plating of metal in the manufacture of PCRAM devices
Non-volatile, resistance variable memory devices, integrated circuit elements, and methods of forming such devices are provided. According to one embodiment of a...
US-7,264,844 Forming oxide buffer layer for improved magnetic tunnel junctions
A metal manganese oxide buffer layer is used to seed a barrier layer in a magnetic tunnel junction memory element having pinned and free magnetic layers. An...
US-7,264,768 Single substrate annealing of magnetoresistive structure
A device for magnetically annealing magnetoresistive elements formed on wafers includes a heated chuck and a delivery mechanism for individually placing the...
US-7,264,742 Method of planarizing a surface
A method for removing at least a portion of a structure, such as a layer, film, or deposit, including ruthenium metal and/or ruthenium dioxide includes...
US-7,264,539 Systems and methods for removing microfeature workpiece surface defects
Systems and methods for removing microfeature workpiece surface defects are disclosed. A method for processing a microfeature workpiece in accordance with one...
US-7,264,456 Leadframe and method for reducing mold compound adhesion problems
An integrated circuit leadframe has a pair of leadframe rails that are specially treated to adhere to injection mold compounds to a lesser or greater degree than...
US-7,263,768 Method of making a semiconductor device having an opening in a solder mask
The present invention features a novel design for a fiducial and pin one indicator that utilizes a single solder resist opening in a die mounting substrate to...
US-7,263,570 Method of providing an interface to a plurality of peripheral devices using bus adapter chips
A method of electrically coupling a central processing unit (CPU) of a network server to a plurality of network interface modules. The method comprises providing...
US-7,263,543 Method for manipulating data in a group of processing elements to transpose the data using a memory stack
A method for transposing data in a plurality of processing elements is comprised of a plurality of shifting operations and a plurality of storing operations. The...
US-7,263,022 No-precharge FAMOS cell and latch circuit in a memory device
The fuse and latch circuit has a Floating gate Avalanche injection Metal Oxide Semiconductor (FAMOS) transistor (fuse) that is coupled to a read circuit. The...
US-7,263,017 AC sensing for a resistive memory
Alternating current is used to sense a logic state of a memory cell that has a resistive memory element. The memory element can be in an array and a memory...
US-7,263,006 Memory block erasing in a flash memory device
The flash memory cell erase operation performs an erase operation at a first erase voltage for a first erase time. An erase verify read operation is then...
US-7,262,996 Programmable soft-start control for charge pump
A programmable soft-start control circuit having two memory registers for regulating the ramp-up time period of charging current in a charge pump of an...
US-7,262,780 Simple and robust color saturation adjustment for digital images
A method and system for adjusting saturation in digital images that operates as closely as possible to the long-, medium-, short-(LMS) cone spectral response...
US-7,262,641 Current differential buffer
The present technique relates to a method and apparatus for operating a differential buffer. In the differential buffer, a first stage may include a differential...
US-7,262,637 Output buffer and method having a supply voltage insensitive slew rate
An output buffer includes a final driver formed by first and second MOSFET transistors that alternately couple an output terminal to respective supply voltages....
US-7,262,612 Methods for evaluating characteristics of a plasma or the effects of a plasma on a substrate
A method for evaluating characteristics of a plasma or the effects of the plasma on a substrate includes introducing a plasma probe into a reaction chamber. The...
US-7,262,555 Method and system for discretely controllable plasma processing
A method and system for plasma generation and processing includes a plurality of beam generators each locally controllable and configured for operation upon a...
US-7,262,506 Stacked mass storage flash memory package
A stacked multiple offset chip device is formed of two or more dice of similar dimensions and bond pad arrangement, in which bond pads are located in fields...
US-7,262,505 Selective electroless-plated copper metallization
Structures and methods are provided which include a selective electroless copper metallization. The present invention includes a novel methodology for forming...
US-7,262,503 Semiconductor constructions
The invention encompasses methods of forming insulating materials between conductive elements. In one aspect, the invention includes a method of forming a...
US-7,262,499 Semiconductor packages
The invention includes semiconductor packages having a patterned substrate with openings extending therethrough, conductive circuit traces over the substrate and...
US-7,262,488 Substrate with enhanced properties for planarization
A method and intermediate structure for improving the thinning and planarity of a wafer back side utilizing planarization material applied to the back side prior...
US-7,262,487 Semiconductor devices and other electronic components including porous insulators created from "void" creating...
Semiconductor devices, other electronic components, and other articles of manufacture with porous insulator structures are disclosed. The insulative material of...
US-7,262,482 Open pattern inductor
The invention includes a stacked open pattern inductor fabricated above a semiconductor substrate. The stacked open pattern inductor includes a plurality of...
US-7,262,473 Metal to polysilicon contact in oxygen environment
A method for forming a contact capable of tolerating an O.sub.2 environment up to several hundred degrees Celsius for several hours is disclosed. To slow down...
US-7,262,428 Strained Si/SiGe/SOI islands and processes of making same
A process of making a strained silicon-on-insulator structure is disclosed. A recess is formed in a substrate to laterally isolate an active area. An...
US-7,262,405 Prefabricated housings for microelectronic imagers
Microelectronic imagers with prefabricated housings and methods of packaging microelectronic imagers are disclosed herein. In one embodiment, a microelectronic...
US-7,262,136 Modified facet etch to prevent blown gate oxide and increase etch chamber life
A modified facet etch is disclosed to prevent blown gate oxide and increase etch chamber life. The modified facet etch is a two-stage process. The first stage is...
US-7,262,135 Methods of forming layers
The invention includes methods of forming layers conformally over undulating surface topographies associated with semiconductor substrates. The undulating...
US-7,262,134 Microfeature workpieces and methods for forming interconnects in microfeature workpieces
Methods for forming interconnects in microfeature workpieces, and microfeature workpieces having such interconnects are disclosed herein. In one embodiment, a...
US-7,262,132 Metal plating using seed film
A seed film and methods incorporating the seed film in semiconductor applications is provided. The seed film includes one or more noble metal layers, where each...
US-7,262,130 Methods for making integrated-circuit wiring from copper, silver, gold, and other metals
Integrated circuits, the key components in thousands of electronic and computer products, include interconnected networks of electrical components. The...
US-7,262,123 Methods of forming wire bonds for semiconductor constructions
The invention includes a semiconductor construction having a wire bonding region associated with a metal-containing layer, and having radiation-imageable...
US-7,262,121 Integrated circuit and methods of redistributing bondpad locations
Integrated circuits and methods of redistributing bondpad locations are disclosed. In one implementation, a method of redistributing a bondpad location of an...
US-7,262,110 Trench isolation structure and method of formation
In general, the present invention discloses at least one trench isolation region formed in a semiconductor substrate to electrically and/or optically isolate at...
US-7,262,102 Reduction of field edge thinning in peripheral devices
A dielectric layer (e.g., an interpoly dielectric layer) is deposited over low and high voltage devices of a peripheral memory device. The dielectric behaves as...
US-7,262,099 Methods of forming field effect transistors
A mass of material is formed over a semiconductor substrate. Semiconductive material is formed laterally proximate the mass of material. A space is provided...
US-7,262,089 Methods of forming semiconductor structures
The invention includes semiconductor structures having buried silicide-containing bitlines. Vertical surround gate transistor structures can be formed over the...
US-7,262,074 Methods of fabricating underfilled, encapsulated semiconductor die assemblies
An apparatus and method may be used for packaging a semiconductor die and a carrier substrate to substantially prevent trapped moisture therebetween and provide...
US-7,262,053 Terraced film stack
A process and apparatus directed to forming a terraced film stack of a semiconductor device, for example, a DRAM memory device, is disclosed. The present...
US-7,261,835 Acid blend for removing etch residue
A method for removing organometallic and organosilicate residues remaining after a dry etch process from semiconductor substrates. The substrate is exposed to a...
US-7,261,832 Methods and apparatuses for monitoring and controlling mechanical or chemical-mechanical planarization of...
Methods and devices for mechanical and/or chemical-mechanical planarization of semiconductor wafers, field emission displays and other microelectronic substrate...
US-7,260,685 Memory hub and access method having internal prefetch buffers
A memory module includes a memory hub coupled to several memory devices. The memory hub includes history logic that predicts on the basis of read memory requests...
US-7,260,125 Method of forming mirrors by surface transformation of empty spaces in solid state materials
A multi-layered reflective mirror formed of spaced-apart plate-shaped empty space patterns formed within a substrate is disclosed. The plurality of plate-shaped...
US-7,260,015 Memory device and method having multiple internal data buses and memory bank interleaving
A memory device and method receives write data through a unidirectional downstream bus and outputs read data through a unidirectional upstream bus. The...
US-7,259,996 Flash memory
Flash memory supporting methods for erasing memory cells using a decrease in magnitude of a source voltage of a first polarity to increase the magnitude of a...
US-7,259,991 Operation of multiple select gate architecture
Methods of operating non-volatile memory devices including multiple series-coupled select gates on the drain and/or source ends of strings of non-volatile memory...
US-7,259,915 Microlens array sheet
Disclosed is a microlens array sheet capable of improving a viewing angle by maintaining a fill factor while reducing a radius of curvature of the microlens of...
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