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Patent # Description
US-7,239,552 Non-volatile one time programmable memory
A verify operation is performed on the one time programmable memory block to determine if it has been programmed. If any bits have been programmed, further...
US-7,239,381 Particle detection method
A method for detecting on a substrate used in the fabrication of integrated devices comprises the steps of (1) contacting the substrate with a monomer, wherein...
US-7,239,152 Methods for measuring parasitic capacitance and inductance of I/O leads on an electrical component using a...
Apparatus and methods are provided for measuring the potential for mutual coupling in an integrated circuit package of any type or configuration using a network...
US-7,239,075 Nitrogen and phosphorus doped amorphous silicon as resistor for field emission display device baseplate
Described herein is a resistor layer for use in field emission display devices and the like, and its method of manufacture. The resistor layer is an amorphous...
US-7,239,029 Packages for semiconductor die
A ball grid array assembly includes a package cover that encapsulates a die and a portion of a substrate to which the die is attached, including an edge of the...
US-7,239,025 Selective deposition of solder ball contacts
Methods of forming solder ball contacts having dimensions of approximately 2.5 microns in diameter for use in C4-type connections. The methods form solder ball...
US-7,239,015 Heat sinks including nonlinear passageways
A stereolithographically fabricated heat sink may include non-linear, or convoluted passageways therethrough, through which air can flow. The heat sink may also...
US-7,239,003 Isolation techniques for reducing dark current in CMOS image sensors
Isolation methods and devices for isolating regions of a semiconductor device. The isolation method and structure include forming an isolating trench in an...
US-7,238,981 Metal-poly integrated capacitor structure
A metal-poly integrated capacitor structure that may be used in a charge pump circuit of a non-volatile memory. In one embodiment, the capacitor comprises a poly...
US-7,238,977 Wide dynamic range sensor having a pinned diode with multiple pinned voltages
A pixel cell has controlled photosensor anti-blooming leakage by having dual pinned voltage regions, one of which is used to set the anti-blooming...
US-7,238,616 Photo-assisted method for semiconductor fabrication
The present invention provides a processing system comprising a remote plasma activation region for formation of active gas species, a transparent transfer tube...
US-7,238,613 Diffusion-enhanced crystallization of amorphous materials to improve surface roughness
Methods of forming a roughened surface through diffusion-enhanced crystallization of an amorphous material are disclosed. In one aspect, conductive hemispherical...
US-7,238,599 Multi-state NROM device
An array of NROM flash memory cells configured to store at least two bits per four F.sup.2. Split vertical channels are generated along each side of adjacent...
US-7,238,544 Imaging with gate controlled charge storage
A pixel cell comprises a photo-conversion device for generating charge and a gate controlled charge storage region for storing photo-generated charge under...
US-7,238,543 Methods for marking a bare semiconductor die including applying a tape having energy-markable properties
A method used for marking a semiconductor wafer or device. The method and apparatus have particular application to wafers or devices which have been subjected to...
US-7,237,172 Error detection and correction in a CAM
An error detection and correction circuit is connected to at least one memory bank of a CAM device. During background processing (i.e., when the CAM is not...
US-7,237,158 Intelligent binning for electrically repairable semiconductor chips
The present invention relates to a system and method for testing one or more semiconductor devices (e.g., packaged chips). Test equipment performs at least tests...
US-7,237,155 Testing method for permanent electrical removal of an intergrated circuit output after packaging
An apparatus and method of disconnecting or disabling an input/output terminal of an integrated circuit after packaging. Each input/output terminal of the...
US-7,237,136 Method and apparatus for providing symmetrical output data for a double data rate DRAM
An apparatus and method is disclosed to compensate for skew and asymmetry of a locally processed system clock used to synchronize an output signal, e.g., a data...
US-7,236,415 Sample and hold memory sense amplifier
A memory sense amplifier includes a sample and hold circuit followed by a differential amplifier. The sample and hold circuit samples a reference voltage on a...
US-7,236,407 Flash memory architecture for optimizing performance of memory having multi-level memory cells
A flash memory device having a pipelined RAS/CAS architecture is logically organized as an array of rows and columns of multi-bit flash memory cells each capable...
US-7,236,400 Erase verify for non-volatile memory using a bitline current-to-voltage converter
A memory device verify system determines a state of memory cells in a memory. The memory includes a memory array having a plurality of memory cells coupled to...
US-7,236,399 Method for erase-verifying a non-volatile memory capable of identifying over-erased and under-erased memory cells
A memory device verify system determines a state of memory cells in a memory. The memory includes a memory array having a plurality of memory cells coupled to...
US-7,236,387 Writing to ferroelectric memory devices
A ground potential is applied to a first word line coupled to a control gate of a selected ferroelectric memory cell in an array of ferroelectric memory cells. A...
US-7,236,385 Memory architecture
A DDR SDRAM where unidirectional row logic is associated with and connected to a single memory array instead of being associated with and connected to multiple...
US-7,236,019 Low current wide VREF range input buffer
A low-current input buffer is disclosed. The buffer uses self-biased N and P channel differential pairs with their outputs tied together. The self-biasing...
US-7,236,016 Low voltage comparator
An integrated circuit comparator comprises a differential amplifier, a source follower circuit coupled to a gate terminal of a first transistor in the...
US-7,235,872 Bow control in an electronic package
A package including a package substrate, a die-substrate assembly including a substrate including a plurality of layers including a layer having a mesh to...
US-7,235,871 Stacked microelectronic dies
An assembly of microelectronic devices and method for forming an assembly of microelectronic devices. In one embodiment, the method includes positioning a first...
US-7,235,865 Methods for making nearly planar dielectric films in integrated circuits
In the fabrication of integrated circuits, one specific technique for making surfaces flat is chemical-mechanical planarization. However, this technique is quite...
US-7,235,858 Edge intensive antifuse and method for making the same
An antifuse including a bottom plate having a plurality of longitudinal members arranged substantially parallel to a first axis, a dielectric layer formed on the...
US-7,235,856 Trench isolation for semiconductor devices
In etching trench isolation structures, a pad oxide or sacrificial oxide may be formed with substantially the same (or higher) etch rate as the trench filler....
US-7,235,854 Lanthanide doped TiO.sub.x dielectric films
A dielectric film containing lanthamide doped TiO.sub.x and a method of fabricating such a dielectric film produce a reliable gate dielectric having an...
US-7,235,837 Technique to control tunneling currents in DRAM capacitors, cells, and devices
Structures and methods are provided for the use with PMOS devices. Materials with large electron affinities or work functions are provided for structures such as...
US-7,235,501 Lanthanum hafnium oxide dielectrics
Dielectric layers containing a lanthanum hafnium oxide layer, where the lanthanum hafnium oxide layer is formed as a structure of one or more monolayers, and...
US-7,235,499 Semiconductor processing methods
In one aspect, the invention encompasses a semiconductor processing method. A layer of material is formed over a semiconductive wafer substrate. Some portions of...
US-7,235,498 Process for growing a dielectric layer on a silicon-containing surface using a mixture of N.sub.2O and O.sub.3
This invention is embodied in an improved process for growing high-quality silicon dioxide layers on silicon by subjecting it to a gaseous mixture of nitrous...
US-7,235,497 Selective oxidation methods and transistor fabrication methods
The invention includes selective oxidation methods and transistor fabrication methods. In one implementation, a selective oxidation method includes positioning a...
US-7,235,494 CMP cleaning composition with microbial inhibitor
An antimicrobial cleaning composition and methods for cleaning semiconductor substrates, particularly after chemical mechanical planarization or polishing, are...
US-7,235,493 Low-k dielectric process for multilevel interconnection using mircocavity engineering during electric circuit...
One embodiment of a method for forming a low-k dielectric for a semiconductor device assembly comprises forming a silicon dioxide layer, then forming a patterned...
US-7,235,488 In-situ chemical-mechanical planarization pad metrology using ultrasonic imaging
Chemical-mechanical planarization (CMP) apparatus and methods for detecting polishing pad properties using ultrasonic imaging is presented. An ultrasonic probe...
US-7,235,480 Semiconductor processing methods of forming integrated circuitry and semiconductor processing methods of...
Semiconductor processing methods of forming integrated circuitry, and in particular, dynamic random access memory (DRAM) circuitry are described. In one...
US-7,235,468 FinFET device with reduced DIBL
FinFET devices formed with a Silicon On Insulator (SOI) technology with reduced Drain Induced Barrier Lowering (DIBL) characteristics and methods for producing...
US-7,235,459 Methods of forming trench isolation in the fabrication of integrated circuitry, methods of fabricating memory...
The invention includes methods of forming trench isolation in the fabrication of integrated circuitry, methods of fabricating integrated circuitry including...
US-7,235,457 High permeability layered films to reduce noise in high speed interconnects
This invention provides a structure and method for improved transmission line operation on integrated circuits. One method of the invention includes forming...
US-7,235,448 Dielectric layer forming method and devices formed therewith
Embodiments in accordance with the present invention provide alternative materials, and methods of forming such materials, that are effective as dielectric...
US-7,235,446 Methods of forming silicon-doped aluminum oxide, and methods of forming transistors and memory devices
The invention encompasses a method of forming a silicon-doped aluminum oxide. Aluminum oxide and silicon monoxide are co-evaporated. Subsequently, at least some...
US-7,235,431 Methods for packaging a plurality of semiconductor dice using a flowable dielectric material
A method of packaging at least a portion of a semiconductor die or dice is disclosed. Uncured material may be disposed proximate at least the periphery of at...
US-7,235,419 Method of making a memory cell
An inverted PCRAM cell is formed by plating the bottom electrode, made of copper for example, with a conductive material, such as silver. Chalcogenide material...
US-7,235,409 Methods of forming semiconductor constructions
The invention includes a method of forming a semiconductor construction, such as an MRAM construction. A block is formed over a semiconductor substrate. First...
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