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Semiconductor component having stacked, encapsulated dice and method of
A semiconductor component includes a substrate and multiple stacked, encapsulated semiconductor dice on the substrate. A first die is back bonded to the...
Reduced leakage semiconductor device
The invention includes a semiconductor construction having a pair of channel regions that have sub-regions doped with indium and surrounded by boron. A pair of...
Method of improved high K dielectric--polysilicon interface for CMOS
Methods for forming dielectric layers over polysilicon substrates, useful in the construction of capacitors and other semiconductor circuit components are...
Wire bonders and methods of wire-bonding
Wire bonders and methods of wire-bonding are disclosed herein. In one embodiment, a method includes attaching a wire to a terminal of a microelectronic component...
Lightly doped drain MOS transistor
A method of forming a MOS transistor in an upper surface of a semiconductor substrate. A gate oxide layer covers the upper surface of the substrate. A gate stack...
Methods for removal of organic materials
The invention includes methods of forming capacitor structures and removing organic material. An organic material, such as a photoresist, is disposed on a...
Methods and apparatus for forming rhodium-containing layers
A method of forming a rhodium-containing layer on a substrate, such as a semiconductor wafer, using complexes of the formula L.sub.yRhY.sub.z is provided. Also...
Front-end processing of nickel plated bond pads
A front-end method of fabricating nickel plated caps over copper bond pads used in a memory device. The method provides protection of the bond pads from an...
Semiconductor constructions, and methods of forming capacitor devices
The invention includes semiconductor constructions, and also includes methods of forming pluralities of capacitor devices. An exemplary method of the invention...
A semiconductor package is provided which includes a semiconductor die which is formed in a die mounting area of a substrate. The die mounting area includes a...
Semiconductor devices and semiconductor device components with
peripherally located, castellated contacts,...
A multichip assembly includes semiconductor devices or semiconductor device components with outer connectors on peripheral edges thereof. The outer connectors...
Photodiode with ultra-shallow junction for high quantum efficiency CMOS
image sensor and method of formation
A pinned photodiode with an ultra-shallow highly-doped surface layer of a first conductivity type and a method of formation are disclosed. The ultra-shallow...
Methods for improving angled line feature accuracy and throughput using
electron beam lithography and electron...
Methods to reduce the write time for forming mask patterns having angled and non-angled features using electron beam lithography are disclosed. In one exemplary...
Multi-layer, attenuated phase-shifting mask
The present invention provides an attenuated phase shift mask ("APSM") that, in each embodiment, includes completely transmissive regions sized and shaped to...
Methods of printing structures
The invention encompasses a radiation-patterning tool. The tool is configured to be utilized to print a pair of structures in a radiation-sensitive material. The...
BIOS lock encode/decode driver
Systems and methods for preventing the unauthorized access to data stored on removable media, such as software, include storing a predetermined signature in the...
Multi-bank memory accesses using posted writes
Systems and methods for reducing delays between successive write and read accesses in multi-bank memory devices are provided. Computer circuits modify the...
Method and apparatus for accessing a dynamic memory device by providing at
least one of burst and latency...
A method and apparatus are provided for accessing a dynamic memory device. The method comprises receiving a command from a controller to access a memory,...
Methods for supporting substrates during fabrication of one or more
objects thereon by programmable material...
A programmed material consolidation apparatus includes a support with a surface that receives at least one substrate and prevents unconsolidated material from...
Multi-phase clock signal generator and method having inherently unlimited
A delay-lock loop includes several delay lines, all but the first of which is composed of at least one variable delay unit that provides a fixed delay and a...
Rewrite prevention in a variable resistance memory
A variable resistance memory cell is read by a sense amplifier but without rewriting the contents of the memory cell. If the memory cell has an access...
Non-skipping auto-refresh in a DRAM
In a dynamic random access memory device, an auto-refresh method comprises receiving a command for the memory device to operate in a half-density mode. This...
Detecting "almost match" in a CAM
An apparatus and method is disclosed for detecting CAM words having a "near match" condition, where "near match" is defined by a CAM word having one or more...
Wide dynamic range active pixel with knee response
A pixel circuit, and a method for operating a pixel circuit, to provide a multiple knee response characteristic. In one embodiment of the invention, one or more...
Plurality of semiconductor die in an assembly
The present invention provides methods and apparatus related to preventing adhesive contamination of the electrical contacts of a semiconductor device in a...
Contact/via force fill techniques and resulting structures
An improved method of forming a semiconductor device structure is disclosed, comprising insertion of a semiconductor wafer into a high-pressure heated chamber...
Semiconductor component having plate and stacked dice
A semiconductor component includes a base die and a secondary die stacked on and bonded to the base die. The base die includes conductive vias which form an...
Single transistor vertical memory gain cell
A high density vertical single transistor gain cell is realized for DRAM operation. The gain cell includes a vertical transistor having a source region, a drain...
Integrated circuit device having non-linear active area pillars
An integrated circuit device having non-linear active area pillars. More specifically, pillars are formed in a substrate such that sidewalls are exposed. The...
Method for forming a low leakage contact in a CMOS imager
An imaging device formed as a CMOS semiconductor integrated circuit includes a doped polysilicon contact line between the floating diffusion region and the gate...
Silicon on insulator read-write non-volatile memory comprising lateral
thyristor and trapping layer
Disclosed herein is an improved thyristor-based memory cell. In one embodiment, the cell is formed in a floating substrate using Silicon-On-Insulator (SOI)...
Image sensor, an image sensor pixel, and methods of forming the same
A semiconductor image sensor utilizing a metal mesh filter to transmit light of a specific wavelength to a photoconversion device, and method of making said...
Circuit and method for a folded bit line memory cell with vertical
transistor and trench capacitor
A memory cell for a memory array in a folded bit line configuration. The memory cell includes an access transistor formed in a pillar of single crystal...
Methods for forming backside alignment markers useable in semiconductor
Disclosed herein are methods for forming photolithography alignment markers on the back side of a substrate, such as a crystalline silicon substrate used in the...
Memory element and its method of formation
A method for controlling silver doping of a chalcogenide glass in a resistance variable memory element is disclosed herein. The method includes forming a thin...
Spacers for packaged microelectronic imagers and methods of making and
using spacers for wafer-level packaging...
Methods of packaging microelectronic imagers and packaged microelectronic imagers. An embodiment of such a method can include providing an imager workpiece...
Microfluidic channel network device
Described herein is microfluidic device for joining fluids and a related method for doing the same. The device according to the present invention includes a...
Planarizing solutions including abrasive elements, and methods for
manufacturing and using such planarizing...
A planarizing slurry for mechanical and/or chemical-mechanical polishing of microfeature workpieces. In one embodiment, the planarizing slurry comprises a liquid...
Method for forming and using planarizing pads for mechanical and
chemical-mechanical planarization of...
Methods and apparatuses for planarizing a microelectronic substrate. In one aspect of the invention, a first portion of an energy-sensitive, non-sacrificial...
Component transfer systems
A system for transferring electrical components. The system may comprise a plurality of electrical components. Each of the components may include leads and a...
Optimized container stacked capacitor DRAM cell utilizing sacrificial
oxide deposition and chemical mechanical...
An existing stacked capacitor fabrication process is modified to construct a three-dimensional stacked container capacitor. The present invention develops the...
System and method for communicating the synchronization status of memory
modules during initialization of the...
A memory system includes a memory hub controller coupled to a plurality of memory modules each of which includes a memory hub. The memory hub controller and the...
System and method for memory hub-based expansion bus
A system memory includes a memory hub controller, a memory module accessible by the memory hub controller, and an expansion module having a processor circuit...
Apparatus and method for direct memory access in a hub-based memory system
A memory hub for a memory module having a DMA engine for performing DMA operations in system memory. The memory hub includes a link interface for receiving...
Switched capacitor DRAM sense amplifier with immunity to mismatch and
A switched capacitor sense amplifier includes capacitively coupled input, feedback, and reset paths to provide immunity to the mismatches in transistor...
Defective block handling in a flash memory device
A method and circuit that remaps, to a single redundant memory block, defective rows from amongst a plurality of defective memory blocks. The circuit determines...
Ballistic direct injection flash memory cell on strained silicon
A flash memory cell comprising a silicon-germanium layer with a pair of source/drain regions. A strained silicon layer is formed over the silicon-germanium layer...
Non-volatile memory device with erase address register
A non-volatile memory device includes an array of non-volatile memory cells. The memory has control circuitry to erase the non-volatile memory cells and perform...
Multiple level programming in a non-volatile memory device
The programming method of the present invention minimizes program disturb by initially programming cells on the same wordline with the logical state having the...
Multiple level programming in a non-volatile memory device
The programming method of the present invention minimizes program disturb in a non-volatile memory device by initially programming a lower page of a memory...