Easy To Use Patents Search & Patent Lawyer Directory

At Patents you can conduct a Patent Search, File a Patent Application, find a Patent Attorney, or search available technology through our Patent Exchange. Patents are available using simple keyword or date criteria. If you are looking to hire a patent attorney, you've come to the right place. Protect your idea and hire a patent lawyer.

Searching: micron





Search by keyword, patent number, inventor, assignee, city or state:




Patent # Description
US-7,236,016 Low voltage comparator
An integrated circuit comparator comprises a differential amplifier, a source follower circuit coupled to a gate terminal of a first transistor in the...
US-7,235,872 Bow control in an electronic package
A package including a package substrate, a die-substrate assembly including a substrate including a plurality of layers including a layer having a mesh to...
US-7,235,871 Stacked microelectronic dies
An assembly of microelectronic devices and method for forming an assembly of microelectronic devices. In one embodiment, the method includes positioning a first...
US-7,235,865 Methods for making nearly planar dielectric films in integrated circuits
In the fabrication of integrated circuits, one specific technique for making surfaces flat is chemical-mechanical planarization. However, this technique is quite...
US-7,235,858 Edge intensive antifuse and method for making the same
An antifuse including a bottom plate having a plurality of longitudinal members arranged substantially parallel to a first axis, a dielectric layer formed on the...
US-7,235,856 Trench isolation for semiconductor devices
In etching trench isolation structures, a pad oxide or sacrificial oxide may be formed with substantially the same (or higher) etch rate as the trench filler....
US-7,235,854 Lanthanide doped TiO.sub.x dielectric films
A dielectric film containing lanthamide doped TiO.sub.x and a method of fabricating such a dielectric film produce a reliable gate dielectric having an...
US-7,235,837 Technique to control tunneling currents in DRAM capacitors, cells, and devices
Structures and methods are provided for the use with PMOS devices. Materials with large electron affinities or work functions are provided for structures such as...
US-7,235,501 Lanthanum hafnium oxide dielectrics
Dielectric layers containing a lanthanum hafnium oxide layer, where the lanthanum hafnium oxide layer is formed as a structure of one or more monolayers, and...
US-7,235,499 Semiconductor processing methods
In one aspect, the invention encompasses a semiconductor processing method. A layer of material is formed over a semiconductive wafer substrate. Some portions of...
US-7,235,498 Process for growing a dielectric layer on a silicon-containing surface using a mixture of N.sub.2O and O.sub.3
This invention is embodied in an improved process for growing high-quality silicon dioxide layers on silicon by subjecting it to a gaseous mixture of nitrous...
US-7,235,497 Selective oxidation methods and transistor fabrication methods
The invention includes selective oxidation methods and transistor fabrication methods. In one implementation, a selective oxidation method includes positioning a...
US-7,235,494 CMP cleaning composition with microbial inhibitor
An antimicrobial cleaning composition and methods for cleaning semiconductor substrates, particularly after chemical mechanical planarization or polishing, are...
US-7,235,493 Low-k dielectric process for multilevel interconnection using mircocavity engineering during electric circuit...
One embodiment of a method for forming a low-k dielectric for a semiconductor device assembly comprises forming a silicon dioxide layer, then forming a patterned...
US-7,235,488 In-situ chemical-mechanical planarization pad metrology using ultrasonic imaging
Chemical-mechanical planarization (CMP) apparatus and methods for detecting polishing pad properties using ultrasonic imaging is presented. An ultrasonic probe...
US-7,235,480 Semiconductor processing methods of forming integrated circuitry and semiconductor processing methods of...
Semiconductor processing methods of forming integrated circuitry, and in particular, dynamic random access memory (DRAM) circuitry are described. In one...
US-7,235,468 FinFET device with reduced DIBL
FinFET devices formed with a Silicon On Insulator (SOI) technology with reduced Drain Induced Barrier Lowering (DIBL) characteristics and methods for producing...
US-7,235,459 Methods of forming trench isolation in the fabrication of integrated circuitry, methods of fabricating memory...
The invention includes methods of forming trench isolation in the fabrication of integrated circuitry, methods of fabricating integrated circuitry including...
US-7,235,457 High permeability layered films to reduce noise in high speed interconnects
This invention provides a structure and method for improved transmission line operation on integrated circuits. One method of the invention includes forming...
US-7,235,448 Dielectric layer forming method and devices formed therewith
Embodiments in accordance with the present invention provide alternative materials, and methods of forming such materials, that are effective as dielectric...
US-7,235,446 Methods of forming silicon-doped aluminum oxide, and methods of forming transistors and memory devices
The invention encompasses a method of forming a silicon-doped aluminum oxide. Aluminum oxide and silicon monoxide are co-evaporated. Subsequently, at least some...
US-7,235,431 Methods for packaging a plurality of semiconductor dice using a flowable dielectric material
A method of packaging at least a portion of a semiconductor die or dice is disclosed. Uncured material may be disposed proximate at least the periphery of at...
US-7,235,419 Method of making a memory cell
An inverted PCRAM cell is formed by plating the bottom electrode, made of copper for example, with a conductive material, such as silver. Chalcogenide material...
US-7,235,409 Methods of forming semiconductor constructions
The invention includes a method of forming a semiconductor construction, such as an MRAM construction. A block is formed over a semiconductor substrate. First...
US-7,235,138 Microfeature workpiece processing apparatus and methods for batch deposition of materials on microfeature...
The present disclosure describes apparatus and methods for processing microfeature workpieces, e.g., by depositing material on a microelectronic semiconductor...
US-7,235,000 Methods and systems for conditioning planarizing pads used in planarizing substrates
Monitoring the process of planarizing a workpiece, e.g., conditioning a CMP pad, can present some difficulties. Aspects of this invention provide methods and...
US-7,234,412 Semiconductor substrate deposition processor chamber liner apparatus
A method includes removing at least a piece of a deposition chamber liner from a deposition chamber by passing it through a passageway to the deposition chamber...
US-7,234,070 System and method for using a learning sequence to establish communications on a high-speed nonsynchronous...
A memory system includes a memory hub controller that sends write data to a plurality of memory modules through a downstream data bus and receives read data from...
US-7,233,737 Fixed-focus camera module and associated method of assembly
A fixed-focus camera module includes an image sensor, a lens for focusing an image onto the image sensor, and a positioning structure for maintaining an...
US-7,233,525 Method of converting contents of flash memory cells in the presence of leakage
An erase operation in a flash memory device includes applying an erase pulse to memory cells of the flash memory device to convert the contents of the memory...
US-7,233,520 Process for erasing chalcogenide variable resistance memory bits
A method of erasing a chalcogenide variable resistance memory cell is provided. The chalcogenide variable resistance memory cell includes a p-doped substrate...
US-7,233,353 Image sensor having boosted reset
A power supply reset boosting element which boosts a level of the reset voltage to a level higher than the level of the power supply. The boosted voltage is...
US-7,233,201 Single-ended pseudo-differential output driver
A differential pair of transistors includes a first transistor and a second transistor having their sources coupled together. Their sources are further coupled...
US-7,233,180 Circuits and methods of temperature compensation for refresh oscillator
A memory device has refresh cycles to refresh memory cells of the memory device. The time interval between one refresh cycle to the next refresh cycle is a...
US-7,233,158 Air socket for testing integrated circuits
An electrical component testing device comprising a housing having at least one recess covered by a flexible membrane so as to form a chamber. A fluid passage...
US-7,233,064 Semiconductor BGA package having a segmented voltage plane and method of making
A semiconductor device assembly and method of making the devices are disclosed. The assembly comprises a semiconductor die attached to an electrically conductive...
US-7,233,056 Chip scale package with heat spreader
A dense semiconductor flip-chip device assembly is provided with a heat sink/spreading/dissipating member that is formed as a paddle of a metallic paddle frame...
US-7,233,047 Transistor with nitrogen-hardened gate oxide
An improved surface P-channel transistor includes providing a semiconductor substrate, forming a gate oxide layer over the semiconductor substrate, subjecting...
US-7,233,042 Method of forming inside rough and outside smooth HSG electrodes and capacitor structure
A container capacitor and method of forming the container capacitor are provided. The container capacitor comprises a lower electrode fabricated by forming a...
US-7,233,038 Self masking contact using an angled implant
A method of implanting, for example, a phosphorous plug over a charge collection region and a method of forming a contact over the phosphorous plug implant and...
US-7,232,754 Microelectronic devices and methods for forming interconnects in microelectronic devices
Microelectronic devices, methods for packaging microelectronic devices, and methods for forming interconnects in microelectronic devices are disclosed herein. In...
US-7,232,747 Method of wafer bumping for enabling a stitch wire bond in the absence of discrete bump formation
A method of bumping a wafer for facilitating bonding of bond wires to elevate the bond location above the passivation layer. The wafer is bumped by disposing the...
US-7,232,728 High quality oxide on an epitaxial layer
This invention improves the quality of gate oxide dielectric layers using a two-pronged approach, thus permitting the use of much thinner silicon dioxide gate...
US-7,232,721 Structures and methods for enhancing capacitors in integrated circuits
Systems, devices, structures, and methods are described that inhibit dielectric degradation at high temperatures. An enhanced capacitor is discussed. The...
US-7,232,713 Methods of forming interconnect lines
In one aspect, the invention provides a method of forming an electrical connection in an integrated circuitry device. According to one preferred implementation,...
US-7,232,198 Printer and print control method
In a printer, an MPU makes a flash ROM store a temperature read by a temperature sensor at the time of setting of a correction value and a misalignment...
US-7,231,537 Fast data access mode in a memory device
A fast data access circuit that has both a standard clock mode and a fast data access mode. The mode is selectable through a mode/configuration register. A...
US-7,230,855 Erase verify for non-volatile memory using bitline/reference current-to-voltage converters
A memory device verify system determines a state of memory cells in a memory. The memory includes a memory array having a plurality of memory cells coupled to...
US-7,230,850 User configurable commands for flash memory
A memory device includes a plurality of memory dies, each having an assigned address. A register on each die is reset on power-up. Boot data is loaded as part of...
US-7,230,848 Vertical NROM having a storage density of 1 bit per 1F2
The multiple bit, vertical memory cell includes a vertical metal oxide semiconductor field effect transistor (MOSFET) extending horizontally outward from a...
← Previous | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 | Next →

File A Patent Application

  • Protect your idea -- Don't let someone else file first. Learn more.

  • 3 Easy Steps -- Complete Form, application Review, and File. See our process.

  • Attorney Review -- Have your application reviewed by a Patent Attorney. See what's included.