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Patent # Description
US-7,253,064 Cascode I/O driver with improved ESD operation
A cascode I/O driver is described that includes a barrier formed in the shared region between the two transistors. The barrier region allows the I/O driver to be...
US-7,253,053 Methods of forming transistor devices and capacitor constructions
The invention includes methods of forming circuit devices. A metal-containing material comprising a thickness of no more than 20 .ANG. (or alternatively...
US-7,253,052 Method for forming a storage cell capacitor compatible with high dielectric constant materials
Described are integrated circuit electrodes and method for fabricating an electrode, which include, in an embodiment forming a silicon, first portion of the...
US-7,253,047 Semiconductor processing methods of forming transistors, semiconductor processing methods of forming dynamic...
Semiconductor processing methods of forming transistors, semiconductor processing methods of forming dynamic random access memory circuitry, and related...
US-7,253,025 Multiple substrate microelectronic devices and methods of manufacture
A microelectronic device and method for manufacture. In one embodiment, two microelectronic substrates are directly bonded to each other without an intermediate...
US-7,253,022 Method for fabricating semiconductor package with multi-layer metal bumps
A semiconductor package includes a substrate formed of a board material, a semiconductor die bonded to the substrate, and an encapsulant on the die. The package...
US-7,251,762 On-chip sampling circuit and method
Through addressing circuitry, a sampling circuit can choose a unique internal node/signal on an encapsulated/packaged chip to be output to one or more drivers....
US-7,251,715 Double data rate scheme for data output
Systems, devices, and methods for a double data rate memory device includes a storage element, a first pipeline, and a second pipeline. The pipelines are...
US-7,251,714 Method and system for capturing and bypassing memory transactions in a hub-based memory system
A memory hub includes a reception interface that receives data words and captures the data words in response to a first clock signal in a first time domain. The...
US-7,251,711 Apparatus and methods having a command sequence
Power consumption by a memory device is optimized by maintaining data input buffers in an off state until a command sequence containing a write command is...
US-7,251,618 Method and system for purchasing a memory upgrade for a computer system
One embodiment of the present invention provides a system that facilitates purchasing a memory upgrade for a computer system. This system operates by obtaining...
US-7,251,387 Optical integrated circuit and method for fabricating the same
The present technique relates to a method and apparatus for fabricating an optical integrated circuit amplifier with another type of optical integrated circuit....
US-7,251,194 Memory system and method for strobing data, command and address signals
A memory system couples command, address or write data signals from a memory controller to a memory device and read data signals from the memory device to the...
US-7,251,187 Memory system, method and predecoding circuit operable in different modes for selectively accessing multiple...
A memory system including a non-volatile flash memory and a method for simultaneously selecting a plurality of memory blocks are disclosed. The memory system is...
US-7,251,181 Techniques for storing accurate operating current values
Methods of manufacturing memory devices and memory modules comprising memory device. Specifically, respective operating current values may be measured and/or...
US-7,251,177 Skewed sense AMP for variable resistance memory sensing
A variable resistance memory sense amplifier has a built-in offset to assist in switching the sense amplifier when a resistive memory cell is in a low resistance...
US-7,251,173 Combination column redundancy system for a memory array
A column redundancy system combining at least two different redundancy systems to provide local redundant memory and shared redundant memory. The column...
US-7,251,154 Method and apparatus providing a cross-point memory array using a variable resistance memory cell and capacitance
The invention relates to a method and apparatus providing a memory cell array in which each resistance memory cell is connected in series to a capacitive...
US-7,250,798 Synchronous clock generator including duty cycle correction
A clock generator for generating an output clock signal synchronized with an input clock signal and having a corrected duty cycle. The clock generator includes...
US-7,250,789 Pseudo-CMOS dynamic logic with delayed clocks
Structures and methods for pseudo-CMOS dynamic logic with delayed clocks are provided. A pseudo-CMOS dynamic logic circuit with delayed clocks includes a dynamic...
US-7,250,780 Probe card for semiconductor wafers having mounting plate and socket
A probe card for testing semiconductor wafers, and a method and system for testing wafers using the probe card are provided. The probe card is configured for use...
US-7,250,687 Systems for degating packaged semiconductor devices with tape substrates
A system for degating a packaged semiconductor device that includes a tape substrate includes a first element and a second element. The first element of the...
US-7,250,680 Semiconductor circuitry constructions
The invention includes a method of forming semiconductor circuitry wherein a first semiconductor structure comprising a first monocrystalline semiconductor...
US-7,250,663 Frame scale package using contact lines through the elements
A package for an integrated circuit contacting device which is shaped like a frame. A portion of the contacting device may be bonded to the printed circuit...
US-7,250,647 Asymmetrical transistor for imager device
An imager device that has mitigated dark current leakage and punch-through protection. The transistor associated with the photoconversion device is formed with a...
US-7,250,628 Memory devices and electronic systems comprising thyristors
The invention includes SOI constructions containing one or more memory cells which include a transistor and a thyristor. In one aspect, a scalable GLTRAM cell...
US-7,250,591 Photonic crystal-based filter for use in an image sensor
The invention, in various exemplary embodiments, incorporates a photonic crystal filter into an image sensor. The photonic crystal filter comprises a substrate...
US-7,250,380 Method of depositing a silicon dioxide-comprising layer in the fabrication of integrated circuitry
This invention includes methods of depositing a silicon dioxide comprising layer in the fabrication of integrated circuitry, and to methods of forming trench...
US-7,250,378 Method of depositing a silicon dioxide-comprising layer in the fabrication of integrated circuitry
This invention includes methods of depositing a silicon dioxide comprising layer in the fabrication of integrated circuitry, and to methods of forming trench...
US-7,250,367 Deposition methods using heteroleptic precursors
An ALD method includes exposing a substrate to a first precursor including a plurality of different ligands, chemisorbing a precursor monolayer on the substrate,...
US-7,250,338 Scalable Flash/NV structures and devices with extended endurance
Devices and methods are provided with respect to a gate stack for a nonvolatile structure. According to one aspect, a gate stack is provided. One embodiment of...
US-7,250,328 Microelectronic component assemblies with recessed wire bonds and methods of making same
The present disclosure suggests various microelectronic component assembly designs and methods for manufacturing microelectronic component assemblies. In one...
US-7,250,321 Method of forming a photosensor
A trench photosensor for use in a CMOS imager having an improved charge capacity. The trench photosensor may be either a photogate or photodiode structure. The...
US-7,250,247 Photolithographic structures using multiple anti-reflecting coatings
A method for fabricating an integrated circuit using a photo-lithographic process includes the steps of placing at least two anti-reflective coating layers...
US-7,249,236 Method and system for controlling memory accesses to memory modules having a memory hub architecture
A computer system includes a memory hub controller coupled to a plurality of memory modules. The memory hub controller includes a memory request queue that...
US-7,248,532 Device, system and method for reducing power in a memory device during standby modes
A memory device responsive to standby mode commands for reducing internal operational power on a memory device is disclosed. The memory device includes a circuit...
US-7,248,521 Negative voltage discharge scheme to improve snapback in a non-volatile memory
Charge pump and discharge circuitry for a non-volatile memory device that splits up the discharge operation into two discharge periods. In a first discharge...
US-7,248,516 Data compression read mode for memory testing
Memory devices having a normal mode of operation and a test mode of operation are useful in quality programs. The test mode of operation includes a data...
US-7,248,515 Non-volatile memory with test rows for disturb detection
A non-volatile memory device has an array of memory cells arranged in rows and columns. The memory cells can be externally accessed for programming, erasing and...
US-7,248,499 Layout for NAND flash memory array having reduced word line impedance
A memory array including a first region in which a first memory sub-array is located and a second region separated from the first region in which a second memory...
US-7,248,498 Serial transistor-cell array architecture
A memory device having memory cells in which a single access transistor controls the grounding of at least four storage elements, such as resistive storage...
US-7,248,407 Microlens array sheet of projection screen, and method for manufacturing the same
The present invention discloses a microlens array sheet of a projection screen including a lens sheet having a predetermined area, microlenses arranged on one...
US-7,248,088 Devices and methods for controlling a slew rate of a signal line
In one aspect of the invention, a method of reducing intersymbol interference on a signal line is disclosed. A state machine records previous bits that were...
US-7,248,063 Plasma probe systems
A plasma probe system includes a plasma probe, at least one meter, and a diagnostic apparatus. The probe may include a substrate having substantially the same...
US-7,247,987 Rear plate for plasma display panel
Disclosed is a rear plate of a plasma display panel. In the rear plate, a dielectric layer or a barrier wall layer is formed by forming slurry in a tape of a...
US-7,247,944 Connector assembly
An apparatus and method for attaching a semiconductor die to a lead frame wherein the electric contact points of the semiconductor die are relocated to the...
US-7,247,927 Leadframe alteration to direct compound flow into package
A leadframe comprising a downset formed adjacent to an edge of the leadframe so as to direct the molding compound to flow evenly inside the mold cavity. The...
US-7,247,920 Method of composite gate formation
Methods for forming a nitride barrier film layer in semiconductor devices such as gate structures, and barrier layers, semiconductor devices and gate electrodes...
US-7,247,919 Method and device to reduce gate-induced drain leakage (GIDL) current in thin gate oxides MOSFETs
An integrated circuit which provides a FET device having reduced GIDL current is described. A semiconductor substrate is provided wherein active regions are...
US-7,247,836 Method and system for determining motion based on difference image correlation
An imager captures successive images of an object. One image is then subtracted from another image to generate difference images. Each difference image is then...
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