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Patent # Description
US-7,262,637 Output buffer and method having a supply voltage insensitive slew rate
An output buffer includes a final driver formed by first and second MOSFET transistors that alternately couple an output terminal to respective supply voltages....
US-7,262,612 Methods for evaluating characteristics of a plasma or the effects of a plasma on a substrate
A method for evaluating characteristics of a plasma or the effects of the plasma on a substrate includes introducing a plasma probe into a reaction chamber. The...
US-7,262,555 Method and system for discretely controllable plasma processing
A method and system for plasma generation and processing includes a plurality of beam generators each locally controllable and configured for operation upon a...
US-7,262,506 Stacked mass storage flash memory package
A stacked multiple offset chip device is formed of two or more dice of similar dimensions and bond pad arrangement, in which bond pads are located in fields...
US-7,262,505 Selective electroless-plated copper metallization
Structures and methods are provided which include a selective electroless copper metallization. The present invention includes a novel methodology for forming...
US-7,262,503 Semiconductor constructions
The invention encompasses methods of forming insulating materials between conductive elements. In one aspect, the invention includes a method of forming a...
US-7,262,499 Semiconductor packages
The invention includes semiconductor packages having a patterned substrate with openings extending therethrough, conductive circuit traces over the substrate and...
US-7,262,488 Substrate with enhanced properties for planarization
A method and intermediate structure for improving the thinning and planarity of a wafer back side utilizing planarization material applied to the back side prior...
US-7,262,487 Semiconductor devices and other electronic components including porous insulators created from "void" creating...
Semiconductor devices, other electronic components, and other articles of manufacture with porous insulator structures are disclosed. The insulative material of...
US-7,262,482 Open pattern inductor
The invention includes a stacked open pattern inductor fabricated above a semiconductor substrate. The stacked open pattern inductor includes a plurality of...
US-7,262,473 Metal to polysilicon contact in oxygen environment
A method for forming a contact capable of tolerating an O.sub.2 environment up to several hundred degrees Celsius for several hours is disclosed. To slow down...
US-7,262,428 Strained Si/SiGe/SOI islands and processes of making same
A process of making a strained silicon-on-insulator structure is disclosed. A recess is formed in a substrate to laterally isolate an active area. An...
US-7,262,405 Prefabricated housings for microelectronic imagers
Microelectronic imagers with prefabricated housings and methods of packaging microelectronic imagers are disclosed herein. In one embodiment, a microelectronic...
US-7,262,136 Modified facet etch to prevent blown gate oxide and increase etch chamber life
A modified facet etch is disclosed to prevent blown gate oxide and increase etch chamber life. The modified facet etch is a two-stage process. The first stage is...
US-7,262,135 Methods of forming layers
The invention includes methods of forming layers conformally over undulating surface topographies associated with semiconductor substrates. The undulating...
US-7,262,134 Microfeature workpieces and methods for forming interconnects in microfeature workpieces
Methods for forming interconnects in microfeature workpieces, and microfeature workpieces having such interconnects are disclosed herein. In one embodiment, a...
US-7,262,132 Metal plating using seed film
A seed film and methods incorporating the seed film in semiconductor applications is provided. The seed film includes one or more noble metal layers, where each...
US-7,262,130 Methods for making integrated-circuit wiring from copper, silver, gold, and other metals
Integrated circuits, the key components in thousands of electronic and computer products, include interconnected networks of electrical components. The...
US-7,262,123 Methods of forming wire bonds for semiconductor constructions
The invention includes a semiconductor construction having a wire bonding region associated with a metal-containing layer, and having radiation-imageable...
US-7,262,121 Integrated circuit and methods of redistributing bondpad locations
Integrated circuits and methods of redistributing bondpad locations are disclosed. In one implementation, a method of redistributing a bondpad location of an...
US-7,262,110 Trench isolation structure and method of formation
In general, the present invention discloses at least one trench isolation region formed in a semiconductor substrate to electrically and/or optically isolate at...
US-7,262,102 Reduction of field edge thinning in peripheral devices
A dielectric layer (e.g., an interpoly dielectric layer) is deposited over low and high voltage devices of a peripheral memory device. The dielectric behaves as...
US-7,262,099 Methods of forming field effect transistors
A mass of material is formed over a semiconductor substrate. Semiconductive material is formed laterally proximate the mass of material. A space is provided...
US-7,262,089 Methods of forming semiconductor structures
The invention includes semiconductor structures having buried silicide-containing bitlines. Vertical surround gate transistor structures can be formed over the...
US-7,262,074 Methods of fabricating underfilled, encapsulated semiconductor die assemblies
An apparatus and method may be used for packaging a semiconductor die and a carrier substrate to substantially prevent trapped moisture therebetween and provide...
US-7,262,053 Terraced film stack
A process and apparatus directed to forming a terraced film stack of a semiconductor device, for example, a DRAM memory device, is disclosed. The present...
US-7,261,835 Acid blend for removing etch residue
A method for removing organometallic and organosilicate residues remaining after a dry etch process from semiconductor substrates. The substrate is exposed to a...
US-7,261,832 Methods and apparatuses for monitoring and controlling mechanical or chemical-mechanical planarization of...
Methods and devices for mechanical and/or chemical-mechanical planarization of semiconductor wafers, field emission displays and other microelectronic substrate...
US-7,260,685 Memory hub and access method having internal prefetch buffers
A memory module includes a memory hub coupled to several memory devices. The memory hub includes history logic that predicts on the basis of read memory requests...
US-7,260,125 Method of forming mirrors by surface transformation of empty spaces in solid state materials
A multi-layered reflective mirror formed of spaced-apart plate-shaped empty space patterns formed within a substrate is disclosed. The plurality of plate-shaped...
US-7,260,015 Memory device and method having multiple internal data buses and memory bank interleaving
A memory device and method receives write data through a unidirectional downstream bus and outputs read data through a unidirectional upstream bus. The...
US-7,259,996 Flash memory
Flash memory supporting methods for erasing memory cells using a decrease in magnitude of a source voltage of a first polarity to increase the magnitude of a...
US-7,259,991 Operation of multiple select gate architecture
Methods of operating non-volatile memory devices including multiple series-coupled select gates on the drain and/or source ends of strings of non-volatile memory...
US-7,259,915 Microlens array sheet
Disclosed is a microlens array sheet capable of improving a viewing angle by maintaining a fill factor while reducing a radius of curvature of the microlens of...
US-7,259,608 System and method for open-loop synthesis of output clock signals having a selected phase relative to an input...
Delay circuits are used in a manner similar to a synchronized mirror delay circuit to generate a quadrature clock signal from an input clock signal. The input...
US-7,259,604 Initialization scheme for a reduced-frequency, fifty percent duty cycle corrector
A reduced-frequency, 50% duty cycle corrector (DCC) circuit may be used in an electronic device (e.g., a memory chip) to generate output clocks with 50% duty...
US-7,259,601 Apparatus and method for suppressing jitter within a clock signal generator
A clock synchronization circuit (200, FIG. 2) includes a signal selector (202), phase detector (204), and delay line (206). The signal selector compares an...
US-7,259,581 Method for testing semiconductor components
A method for testing a semiconductor component includes the steps of bonding an interconnect to the component to form bonded electrical connections, applying...
US-7,259,578 System for testing semiconductor components having interconnect with variable flexure contacts
A test system for testing semiconductor components includes an interconnect having a substrate and contacts on the substrate for electrically engaging terminal...
US-7,259,464 Vertical twist scheme for high-density DRAMs
An interconnection array subunit and method for forming the interconnection array subunit are provided, the interconnection array subunit including a first pair...
US-7,259,451 Invertible microfeature device packages
Invertible microfeature device packages and associated methods for manufacture and use are disclosed. A package in accordance with one embodiment includes a...
US-7,259,450 Double-packaged multi-chip semiconductor module
A plurality of semiconductor die is packaged into one component. The inventive design comprises devices which have been singularized, packaged and thoroughly...
US-7,259,442 Selectively doped trench device isolation
A selectively doped trench isolation device is provided. The trench isolation device of the preferred embodiment includes a semiconductor substrate having a...
US-7,259,435 Intermediate semiconductor device having nitrogen concentration profile
A method for reducing the effective thickness of a gate oxide using nitrogen implantation and anneal subsequent to dopant implantation and activation is...
US-7,259,434 Highly reliable amorphous high-k gate oxide ZrO2
A gate oxide and method of fabricating a gate oxide that produces a more reliable and thinner equivalent oxide thickness than conventional SiO.sub.2 gate oxides...
US-7,259,415 Long retention time single transistor vertical memory gain cell
A single transistor vertical memory gain cell with long data retention times. The memory cell is formed from a silicon carbide substrate to take advantage of the...
US-7,259,413 High dynamic range image sensor
A pixel cell with controlled leakage is formed by modifying the location and gate profile of a high dynamic range (HDR) transistor. The HDR transistor may have a...
US-7,259,093 Methods of forming a conductive contact through a dielectric
A dielectric is formed over a node location on a semiconductor substrate. The dielectric comprises an insulative material over the node location, an insulative...
US-7,259,079 Methods for filling high aspect ratio trenches in semiconductor layers
Methods of filling high aspect ratio trenches in semiconductor layers are provided. The methods utilize HDP-CVD processes to fill trenches with trench filling...
US-7,259,066 One-transistor composite-gate memory
One-transistor memory devices facilitate nonvolatile data storage through the manipulation of oxygen vacancies within a trapping layer of a field-effect...
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