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Patent # Description
US-7,229,724 Reticles and methods of forming and using the same
Reticles having reticle patterns suitable for reducing edge of array effects are provided. The reticle patterns have unresolvable patterns formed in the...
US-7,229,666 Chemical vapor deposition method
Methods of chemical vapor deposition include providing a deposition chamber defined at least in part by at least one of a chamber sidewall and a chamber base...
US-7,229,338 Apparatuses and methods for in-situ optical endpointing on web-format planarizing machines in mechanical or...
Planarizing machines, planarizing pads, and methods for planarizing or endpointing mechanical and/or chemical-mechanical planarization of microelectronic...
US-7,229,336 Apparatus and method for conditioning and monitoring media used for chemical-mechanical planarization
A method and apparatus for conditioning and monitoring a planarizing medium used for planarizing a microelectronic substrate. In one embodiment, the apparatus...
US-7,227,812 Write address synchronization useful for a DDR prefetch SDRAM
Disclosed herein are exemplary embodiments of an improved write address shift register structure useful for example in a DDR3 DRAM having read/write latency. The...
US-7,227,809 Clock generator having a delay locked loop and duty cycle correction circuit in a parallel configuration
A clock generator having a delay locked loop and a duty cycle correction circuit. The delay locked loop adjusts a first adjustable delay circuit to generate a...
US-7,227,806 High speed wordline decoder for driving a long wordline
A method and apparatus for improving the performance of a memory wordline decoder is disclosed. A decoder latch is attached to an inverter which drives the...
US-7,227,800 Noise suppression in memory device sensing
NAND memory devices utilize sensing devices for sensing a programmed state of a nonvolatile memory cell or writing a data value to a nonvolatile memory cell....
US-7,227,793 Voltage translator for multiple voltage operations
A method and apparatus is provided for a voltage translator for performing a voltage-level translation of a signal. The voltage translator of the present...
US-7,227,789 Method and apparatus for filtering output data
Apparatus and methods for filtering spurious output transitions with an adaptive filtering circuit which tracks the memory architecture and form factors with a...
US-7,227,787 Method for erasing an NROM cell
An operation to erase a nitride read only memory (NROM) memory block starts by erasing the memory block. An erase verify operation can then be performed to...
US-7,227,777 Mode selection in a flash memory device
A single flash memory device has selectable read modes for either a segment mode or a page mode. The desired mode is selected by writing a control word to a mode...
US-7,227,774 MRAM integrated circuits, MRAM circuits, and systems for testing MRAM integrated circuits
An integrated circuit includes operational circuitry; a sensor configured to sense an environmental parameter; and adjustment circuitry coupled to the sensor and...
US-7,227,692 Method and apparatus for balancing color response of imagers
A micro-lens array with reduced or no empty space between individual micro-lenses and a method for forming same. The micro-lens array is formed by patterning a...
US-7,227,402 System and method for controlling input buffer biasing current
A system and method for controlling input buffer biasing current include an input buffer circuit with an input current detector circuit configured to generate a...
US-7,227,373 On-chip substrate regulator test mode
An on-chip circuit for defect testing with the ability to maintain a substrate voltage at a level more positive or more negative than a normal negative operating...
US-7,227,261 Vertical surface mount assembly and methods
A vertically mountable semiconductor device assembly including a semiconductor device and a mechanism for attaching the semiconductor device to a carrier...
US-7,227,252 Semiconductor component having stacked, encapsulated dice and method of fabrication
A semiconductor component includes a substrate and multiple stacked, encapsulated semiconductor dice on the substrate. A first die is back bonded to the...
US-7,227,227 Reduced leakage semiconductor device
The invention includes a semiconductor construction having a pair of channel regions that have sub-regions doped with indium and surrounded by boron. A pair of...
US-7,227,209 Method of improved high K dielectric--polysilicon interface for CMOS devices
Methods for forming dielectric layers over polysilicon substrates, useful in the construction of capacitors and other semiconductor circuit components are...
US-7,227,095 Wire bonders and methods of wire-bonding
Wire bonders and methods of wire-bonding are disclosed herein. In one embodiment, a method includes attaching a wire to a terminal of a microelectronic component...
US-7,226,872 Lightly doped drain MOS transistor
A method of forming a MOS transistor in an upper surface of a semiconductor substrate. A gate oxide layer covers the upper surface of the substrate. A gate stack...
US-7,226,863 Methods for removal of organic materials
The invention includes methods of forming capacitor structures and removing organic material. An organic material, such as a photoresist, is disposed on a...
US-7,226,861 Methods and apparatus for forming rhodium-containing layers
A method of forming a rhodium-containing layer on a substrate, such as a semiconductor wafer, using complexes of the formula L.sub.yRhY.sub.z is provided. Also...
US-7,226,857 Front-end processing of nickel plated bond pads
A front-end method of fabricating nickel plated caps over copper bond pads used in a memory device. The method provides protection of the bond pads from an...
US-7,226,845 Semiconductor constructions, and methods of forming capacitor devices
The invention includes semiconductor constructions, and also includes methods of forming pluralities of capacitor devices. An exemplary method of the invention...
US-7,226,813 Semiconductor package
A semiconductor package is provided which includes a semiconductor die which is formed in a die mounting area of a substrate. The die mounting area includes a...
US-7,226,809 Semiconductor devices and semiconductor device components with peripherally located, castellated contacts,...
A multichip assembly includes semiconductor devices or semiconductor device components with outer connectors on peripheral edges thereof. The outer connectors...
US-7,226,803 Photodiode with ultra-shallow junction for high quantum efficiency CMOS image sensor and method of formation
A pinned photodiode with an ultra-shallow highly-doped surface layer of a first conductivity type and a method of formation are disclosed. The ultra-shallow...
US-7,226,723 Methods for improving angled line feature accuracy and throughput using electron beam lithography and electron...
Methods to reduce the write time for forming mask patterns having angled and non-angled features using electron beam lithography are disclosed. In one exemplary...
US-7,226,708 Multi-layer, attenuated phase-shifting mask
The present invention provides an attenuated phase shift mask ("APSM") that, in each embodiment, includes completely transmissive regions sized and shaped to...
US-7,226,707 Methods of printing structures
The invention encompasses a radiation-patterning tool. The tool is configured to be utilized to print a pair of structures in a radiation-sensitive material. The...
US-7,225,469 BIOS lock encode/decode driver
Systems and methods for preventing the unauthorized access to data stored on removable media, such as software, include storing a predetermined signature in the...
US-7,225,312 Multi-bank memory accesses using posted writes
Systems and methods for reducing delays between successive write and read accesses in multi-bank memory devices are provided. Computer circuits modify the...
US-7,225,303 Method and apparatus for accessing a dynamic memory device by providing at least one of burst and latency...
A method and apparatus are provided for accessing a dynamic memory device. The method comprises receiving a command from a controller to access a memory,...
US-7,225,044 Methods for supporting substrates during fabrication of one or more objects thereon by programmable material...
A programmed material consolidation apparatus includes a support with a surface that receives at least one substrate and prevents unconsolidated material from...
US-7,224,639 Multi-phase clock signal generator and method having inherently unlimited frequency capability
A delay-lock loop includes several delay lines, all but the first of which is composed of at least one variable delay unit that provides a fixed delay and a...
US-7,224,632 Rewrite prevention in a variable resistance memory
A variable resistance memory cell is read by a sense amplifier but without rewriting the contents of the memory cell. If the memory cell has an access...
US-7,224,631 Non-skipping auto-refresh in a DRAM
In a dynamic random access memory device, an auto-refresh method comprises receiving a command for the memory device to operate in a half-density mode. This...
US-7,224,593 Detecting "almost match" in a CAM
An apparatus and method is disclosed for detecting CAM words having a "near match" condition, where "near match" is defined by a CAM word having one or more...
US-7,224,388 Wide dynamic range active pixel with knee response
A pixel circuit, and a method for operating a pixel circuit, to provide a multiple knee response characteristic. In one embodiment of the invention, one or more...
US-7,224,070 Plurality of semiconductor die in an assembly
The present invention provides methods and apparatus related to preventing adhesive contamination of the electrical contacts of a semiconductor device in a...
US-7,224,065 Contact/via force fill techniques and resulting structures
An improved method of forming a semiconductor device structure is disclosed, comprising insertion of a semiconductor wafer into a high-pressure heated chamber...
US-7,224,051 Semiconductor component having plate and stacked dice
A semiconductor component includes a base die and a secondary die stacked on and bonded to the base die. The base die includes conductive vias which form an...
US-7,224,024 Single transistor vertical memory gain cell
A high density vertical single transistor gain cell is realized for DRAM operation. The gain cell includes a vertical transistor having a source region, a drain...
US-7,224,020 Integrated circuit device having non-linear active area pillars
An integrated circuit device having non-linear active area pillars. More specifically, pillars are formed in a substrate such that sidewalls are exposed. The...
US-7,224,009 Method for forming a low leakage contact in a CMOS imager
An imaging device formed as a CMOS semiconductor integrated circuit includes a doped polysilicon contact line between the floating diffusion region and the gate...
US-7,224,002 Silicon on insulator read-write non-volatile memory comprising lateral thyristor and trapping layer
Disclosed herein is an improved thyristor-based memory cell. In one embodiment, the cell is formed in a floating substrate using Silicon-On-Insulator (SOI)...
US-7,223,960 Image sensor, an image sensor pixel, and methods of forming the same
A semiconductor image sensor utilizing a metal mesh filter to transmit light of a specific wavelength to a photoconversion device, and method of making said...
US-7,223,678 Circuit and method for a folded bit line memory cell with vertical transistor and trench capacitor
A memory cell for a memory array in a folded bit line configuration. The memory cell includes an access transistor formed in a pillar of single crystal...
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