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Patent # Description
US-7,217,913 Method and system for wavelength-dependent imaging and detection using a hybrid filter
An object to be imaged or detected is illuminated by a single broadband light source or multiple light sources emitting light at different wavelengths. The light...
US-7,217,661 Small grain size, conformal aluminum interconnects and method for their formation
A first layer of titanium nitride (TiN) is formed on a semiconductor structure, such as an interconnect via. Then, a second layer of TiN is formed on the first...
US-7,217,634 Methods of forming integrated circuitry
The invention includes methods of forming integrated circuitry. In one implementation, a method of forming an integrated circuit includes forming a plurality of...
US-7,217,630 Methods of forming hafnium oxide
The invention includes methods of forming hafnium-containing materials, such as, for example, hafnium oxide. In one aspect, a semiconductor substrate is...
US-7,217,617 Methods of forming a capacitor
A method of forming a capacitor having a capacitor dielectric layer comprising ABO.sub.3, where "A" is selected from the group consisting of Group IIA and Group...
US-7,217,615 Capacitor fabrication methods including forming a conductive layer
A capacitor fabrication method may include atomic layer depositing a conductive barrier layer to oxygen diffusion over the first electrode. A method may instead...
US-7,217,614 Methods to form electronic devices and methods to form a material over a semiconductive substrate
A first electrode and a doped oxide layer laterally proximate thereof are provided over a substrate. A silicon nitride layer is formed over both the doped oxide...
US-7,217,606 Method of forming vertical sub-micron CMOS transistors on (110), (111), (311), (511), and higher order surfaces...
A method for forming NMOS and PMOS transistors that includes cutting a substrate along a higher order orientation and fabricating deep sub-micron NMOS and PMOS...
US-7,217,597 Die stacking scheme
An improved semiconductor die stacking scheme is provided. In accordance with one embodiment of the present invention, a method of stacking a plurality of...
US-7,217,596 Stacked die module and techniques for forming a stacked die module
A technique for forming die stacks. Specifically, a stacking tip is provided to facilitate the stacking of die in a desired configuration. A first die is picked...
US-7,217,589 Deep photodiode isolation process
A barrier implanted region of a first conductivity type located below an isolation region of a pixel sensor cell and spaced from a doped region of a second...
US-7,216,425 Method of forming a non-continuous conductive layer for laminated substrates
A method of fabricating a circuit board is provided that includes forming a first layer of conductive material over an insulating layer, removing portions of the...
US-7,216,196 Memory hub and method for memory system performance monitoring
A memory module includes a memory hub coupled to several memory devices. The memory hub includes at least one performance counter that tracks one or more system...
US-7,216,009 Machine vision systems for use with programmable material consolidation system and associated methods and...
Programmable material consolidation systems employing a machine vision system in combination with a 3-D printing system for accurately locating a position over a...
US-7,215,838 Resistive heater for thermo optic device
Resistive heaters formed in two mask counts on a surface of a grating of a thermo optic device thereby eliminating one mask count from prior art manufacturing...
US-7,215,586 Apparatus and method for repairing a semiconductor memory
An apparatus and method for repairing a semiconductor memory device includes a first memory cell array, a first redundant cell array and a repair circuit...
US-7,215,585 Method and apparatus for synchronizing data from memory arrays
According to one embodiment, a combination is comprised of a plurality of sense amps, each having an input for receiving a clock signal. A data bus is for...
US-7,215,582 Controlling multiple signal polarity in a semiconductor device
A method and apparatus for controlling multiple signal polarity in a memory device. A desired active state signal polarity of at least one signal pad of a device...
US-7,215,579 System and method for mode register control of data bus operating mode and impedance
A DRAM device includes a mode register that is programmed to select one of two modes for operating data bus terminals in the device. A timing circuit generates...
US-7,215,572 Methods for neutralizing holes in tunnel oxides of floating-gate memory cells and devices
Methods for neutralizing holes in tunnel oxides of floating-gate memory cells and devices using a decrease in magnitude of a source voltage of a first polarity...
US-7,215,571 Method for reducing drain disturb in programming
For a multi-sectored flash memory array with bitlines spanning multiple erase blocks, a bias scheme for programming an address in any erase sector while...
US-7,215,479 Integrated lens system for image sensor and method for manufacturing the same
A lens system including a first substantially hemispherical lens, a second spherical lens and a third substantially hemispherical lens. The lenses are held...
US-7,215,409 Image forming method and apparatus
The present invention relates to an apparatus for forming a pattern on a radiation sensitive material comprising a source to form a radiation beam, a scanning...
US-7,215,374 Camera module having geared lens barrel
A camera having a housing, an imaging array positioned in said housing, and a lens assembly is disclosed. The lens assembly includes a fixed portion attached to...
US-7,215,369 Compact pixel reset circuits using reversed current readout
Compact CMOS pixel sensors containing three or four total transistors and four or five control lines provide a high percentage of sensor area for the photodiode...
US-7,215,361 Method for automated testing of the modulation transfer function in image sensors
A method for automatically measuring the modulation transfer function of an imager is disclosed. A opaque mask is placed over selected columns and rows of the...
US-7,215,134 Apparatus for determining burn-in reliability from wafer level burn-in
A method, circuit and system for determining burn-in reliability from wafer level burn-in are disclosed. The method according to the present invention includes...
US-7,215,027 Electrical coupling stack and processes for making same
A process of making an electrical coupling stack is disclosed. A conductive structure is coupled to a substrate. The coupling includes a crystalline salicide...
US-7,215,015 Imaging system
A semiconductor package includes a substrate, and a semiconductor die flip chip mounted to the substrate. The package also includes substrate circuitry on a...
US-7,214,994 Self aligned metal gates on high-k dielectrics
A method for forming a transistor including a self aligned metal gate is provided. According to various method embodiments, a high-k gate dielectric is formed on...
US-7,214,981 Semiconductor devices having double-sided hemispherical silicon grain electrodes
Semiconductor devices are provided with double-sided hemispherical silicon grain (HSG) electrodes for container capacitors. In an embodiment, container...
US-7,214,979 Selectively deposited silicon oxide layers on a silicon substrate
A process for selectively depositing a silicon oxide layer onto silicon substrates of different conductivity types is disclosed. The silicon oxide layer is...
US-7,214,978 Semiconductor fabrication that includes surface tension control
In one embodiment, a method includes providing a semiconductor substrate that includes a memory container having a double-sided capacitor. The method also...
US-7,214,962 Apparatus and methods of testing and assembling bumped devices using an anisotropically conductive layer
The present invention is directed toward apparatus and methods of testing and assembling bumped die and bumped devices using an anisotropically conductive layer....
US-7,214,926 Imaging systems and methods
Imaging systems and methods are provided. One exemplary system incorporates multiple lenses that are individually configured to receive multi-wavelength light...
US-7,214,920 Pixel with spatially varying metal route positions
An image sensor including an array of pixels having an optical center, the array including a first pixel substantially at a first distance from the optical...
US-7,214,919 Microelectronic imaging units and methods of manufacturing microelectronic imaging units
Microelectronic imaging units and methods for manufacturing the microelectronic imaging units. In one embodiment, an imaging unit includes a support member, an...
US-7,214,621 Methods of forming devices associated with semiconductor constructions
The invention includes methods of forming devices associated with semiconductor constructions. In exemplary methods, common processing steps are utilized to form...
US-7,214,618 Technique for high efficiency metalorganic chemical vapor deposition
A technique for more efficiently forming conductive elements, such as conductive layers and electrodes, using chemical vapor deposition. A conductive precursor...
US-7,214,616 Homojunction semiconductor devices with low barrier tunnel oxide contacts
A homojunction bipolar transistor with performance characteristics similar to more costly heterojunction or retrograde base transistors. The high emitter...
US-7,214,614 System for controlling metal formation processes using ion implantation
The present invention is generally directed to various methods of using ion implantation techniques to control various metal formation processes. In one...
US-7,214,613 Cross diffusion barrier layer in polysilicon
A semiconductor device includes a cross diffusion barrier layer sandwiched between a gate layer and an electrode layer. The gate layer has a first gate portion...
US-7,214,602 Method of forming a conductive structure
A method of forming a conductive structure is disclosed. The method includes forming an interconnect in a substrate, and forming a layer of iridium on the...
US-7,214,575 Method and apparatus providing CMOS imager device pixel with transistor having lower threshold voltage than...
A transistor of a pixel cell for use in a CMOS imager with a low threshold voltage of about 0.3 V to less than about 0.7 V is disclosed. The transistor is...
US-7,214,566 Semiconductor device package and method
A method of making semiconductor device packages includes the steps of attaching a wafer to a dielectric layer, testing semiconductor devices in the wafer, and...
US-7,214,547 Methods of forming semiconductor constructions
The invention includes a method of forming a semiconductor construction, such as an MRAM construction. A block is formed over a semiconductor substrate. First...
US-7,214,125 Method for controlling pH during planarization and cleaning of microelectronic substrates
A method and apparatus for processing a microelectronic substrate. In one embodiment, the method can include planarizing the microelectronic substrate with a...
US-7,213,447 Method and apparatus for detecting topographical features of microelectronic substrates
An apparatus and method for detecting characteristics of a microelectronic substrate. The microelectronic substrate can have a first surface with first...
US-7,213,331 Method for forming stencil
A method of forming a stencil for the manufacture of semiconductor devices includes defining a plurality of slightly spaced segmental annular openings in a...
US-7,213,330 Method of fabricating an electronic device
A plurality of electrical interconnections may be formed in an electrical device including a first component having a plurality of contact pads and a second...
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