Easy To Use Patents Search & Patent Lawyer Directory

At Patents you can conduct a Patent Search, File a Patent Application, find a Patent Attorney, or search available technology through our Patent Exchange. Patents are available using simple keyword or date criteria. If you are looking to hire a patent attorney, you've come to the right place. Protect your idea and hire a patent lawyer.

Searching: micron





Search by keyword, patent number, inventor, assignee, city or state:




Patent # Description
US-7,200,738 Reducing data hazards in pipelined processors to provide high processor utilization
A pipelined computer processor is presented that reduces data hazards such that high processor utilization is attained. The processor restructures a set of...
US-7,200,736 Method and system for substantially registerless processing
A simple instruction set processor preferably utilizes six primary components: a fetch unit, and instruction and address register, a controller/decoder, an...
US-7,200,693 Memory system and method having unidirectional data buses
A memory system and method includes a unidirectional downstream bus coupling write data from a memory controller to several memory devices, and a unidirectional...
US-7,200,063 Circuitry for a programmable element
As part of anti-fuse circuitry for a memory device, a preferred exemplary embodiment of the current invention provides a direct connection between an anti-fuse...
US-7,200,062 Method and system for reducing the peak current in refreshing dynamic random access memory devices
A dynamic random access memory device includes a mode register that is programmed with a delay value. In some embodiments, a offset code is also stored in the...
US-7,200,053 Level shifter for low voltage operation
A voltage level translator boosts the gate voltage of a transistor, and increases the gate to source voltage, to allow operation over a wider range of supply...
US-7,200,052 Apparatus and methods for regulated voltage
An electronic system according to various aspects of the present invention includes a memory and a supply regulation circuit having a regulated output to provide...
US-7,200,048 Flash memory
Flash memory supporting methods for erasing memory cells using a decrease in magnitude of a source voltage of a first polarity to increase the magnitude of a...
US-7,200,047 High voltage positive and negative two-phase discharge system and method for channel erase in flash memory devices
An erase discharge circuit in a flash memory is coupled to an array source and a p-well drive and receives first and second discharge signals. The erase...
US-7,200,046 Low power NROM memory devices
A buried bipolar junction is provided in a charge trapping transistor memory device. During a write operation electrons are injected into a surface depletion...
US-7,200,041 Sensing scheme for low-voltage flash memory
Single-ended sensing devices for sensing a programmed state of a floating-gate memory cell are adapted for use in low-voltage memory devices. The sensing device...
US-7,200,035 Magneto-resistive memory cell structures with improved selectivity
A magneto-resistive memory comprising magneto-resistive memory cells is disclosed, comprising two pinned magnetic layers on one side of a free magnetic layer....
US-7,200,024 System and method for optically interconnecting memory devices
A memory device includes a semiconductor substrate in which memory circuitry has been fabricated. An address converter and a control signal converter are coupled...
US-7,200,022 Apparatus and method for mounting microelectronic devices on a mirrored board assembly
The present invention is directed to a system, a module, and an apparatus and method for forming a microelectronic memory device. In one embodiment, a system...
US-7,199,931 Gapless microlens array and method of fabrication
A microlens array with reduced or no empty space between individual microlenses and a method for forming the same. The microlens array is formed by patterning a...
US-7,199,593 Apparatus and methods for measuring parasitic capacitance and inductance of I/O leads on an electrical...
Apparatus and methods are provided for measuring the potential for mutual coupling in an integrated circuit package of any type or configuration using a network...
US-7,199,464 Semiconductor device structures including protective layers formed from healable materials
Semiconductor device structures include protective layers that are formed from healable or healed materials. The healable materials are configured to eliminate...
US-7,199,463 Method and structure for manufacturing improved yield semiconductor packaged devices
A semiconductor package structure for a ball grid array type package using a plurality of pieces of adhesive elastomer film to attach a semiconductor die to a...
US-7,199,449 Wafer backside removal to complete through-holes and provide wafer singulation during the formation of a...
A method used to form a semiconductor device comprises processing a semiconductor wafer to include one or more vias or through-holes only partially etched into...
US-7,199,447 Angled implant to improve high current operation of bipolar transistors
Method and apparatus for improving the high current operation of bipolar transistors while minimizing adverse affects on high frequency response are disclosed. A...
US-7,199,444 Memory device, programmable resistance memory cell and memory array
A method of metal doping a chalcogenide material includes forming a metal over a substrate. A chalcogenide material is formed on the metal. Irradiating is...
US-7,199,439 Microelectronic imagers and methods of packaging microelectronic imagers
Microelectronic imagers and methods for packaging microelectronic imagers are disclosed herein. In one embodiment, a microelectronic imaging unit can include a...
US-7,199,422 Contactless uniform-tunneling separate P-well (CUSP) non-volatile memory array architecture, fabrication and...
Floating-gate field-effect transistors or memory cells formed in isolated wells are useful in the fabrication of non-volatile memory arrays and devices. A column...
US-7,199,419 Memory structure for reduced floating body effect
Methods of reducing the floating body effect in vertical transistors are disclosed. The floating body effect occurs when an active region in a pillar is cut off...
US-7,199,417 Merged MOS-bipolar capacitor memory cell
A high density vertical merged MOS-bipolar-capacitor gain cell is realized for DRAM operation. The gain cell includes a vertical MOS transistor having a source...
US-7,199,415 Conductive container structures having a dielectric cap
Container structures for use in integrated circuits and methods of their manufacture. The container structures have a dielectric cap on the top of a conductive...
US-7,199,413 Junction-isolated depletion mode ferroelectric memory devices and systems
Depletion-mode ferroelectric transistors are adapted for use as non-volatile memory cells for memory devices and electronic systems. Various embodiments are...
US-7,199,405 Pixel cell with high storage capacitance for a CMOS imager
A pixel sensor cell for use in a CMOS imager exhibiting improved storage capacitance. The source follower transistor is formed with a large gate that has an area...
US-7,199,349 Amplification with feedback capacitance for photodetector signals
Signals from an imager pixel photodetector are received by an amplifier having capacitive feedback, such as a capacitive transimpedance amplifier (CTIA). The...
US-7,199,347 Layered microlens structures and devices
A microlens structure includes lower lens layers on a substrate. A sputtered layer of glass, such as silicon oxide, is applied over the lower lens layers at an...
US-7,199,050 Pass through via technology for use during the manufacture of a semiconductor device
A method for forming vias which pass through a semiconductor wafer substrate assembly such as a semiconductor die or wafer allows two different types of...
US-7,199,037 Microfeature devices and methods for manufacturing microfeature devices
Microfeature devices, microfeature workpieces, and methods for manufacturing microfeature devices and microfeature workpieces are disclosed herein. The...
US-7,199,023 Atomic layer deposited HfSiON dielectric films wherein each precursor is independendently pulsed
A dielectric film containing atomic layer deposited HfSiON and a method of fabricating such a dielectric film produce a reliable dielectric layer having an...
US-7,199,017 Methods of forming semiconductor circuitry
The invention includes a method of forming semiconductor circuitry. A monocrystalline silicon substrate is provided, and a mask is formed which covers a first...
US-7,199,005 Methods of forming pluralities of capacitors
The invention comprises methods of forming pluralities of capacitors. In one implementation, metal is formed over individual capacitor storage node locations on...
US-7,198,999 Flash memory device having a graded composition, high dielectric constant gate insulator
A graded composition, high dielectric constant gate insulator is deposited between a substrate and floating gate in a flash memory cell transistor. If the...
US-7,198,980 Methods for assembling multiple semiconductor devices
A multidie semiconductor device (MDSCD) package includes a generally planar interposer comprising a substrate with a central receptacle, upper surface...
US-7,198,974 Micro-mechanically strained semiconductor film
One aspect of the present subject matter relates to a method for forming strained semiconductor film. In various embodiments, a single crystalline semiconductor...
US-7,198,693 Microelectronic device having a plurality of stacked dies and methods for manufacturing such microelectronic...
Systems and methods for assembling microelectronic devices that have a base die and a conventional wire-bond die stacked on the base die. In one embodiment of a...
US-RE39,547 Method and apparatus for endpointing mechanical and chemical-mechanical polishing of substrates
An apparatus and method for stopping mechanical and chemical-mechanical polishing of a substrate at a desired endpoint. In one embodiment, a polishing machine...
US-7,197,674 Method and apparatus for conditioning of a digital pulse
An integrated circuit includes a first external pin and an input buffer connected to the first external pin. The input buffer includes an output terminal and a...
US-7,197,607 Non-volatile memory with concurrent write and read operation to differing banks
A synchronous flash memory includes an array of non-volatile memory cells. The memory array is arranged in rows and columns, and can be further arranged in...
US-7,197,603 Method and apparatus for high performance branching in pipelined microsystems
A pipelined processor includes a branch acceleration technique which is based on an improved branch cache. The improved branch cache minimizes or eliminates...
US-7,196,964 Selectable memory word line deactivation
Circuitry and methods allow selected memory word lines (WLs) to be deactivated without using a global deactivate signal. All active WLs do not therefore have to...
US-7,196,958 Power efficient memory and cards
A memory with an internal detection mechanism to detect the presence of either an external component of an external voltage on some no connect pins, allowing a...
US-7,196,936 Ballistic injection NROM flash memory
A split NROM flash memory cell is comprised of source/drain regions in a substrate. The split nitride charge storage regions are insulated from the substrate by...
US-7,196,935 Ballistic injection NROM flash memory
A split NROM flash memory cell is comprised of source/drain regions in a substrate. The split nitride charge storage regions are insulated from the substrate by...
US-7,196,934 Non-volatile memory with erase verify circuit having comparators indicating under-erasure, erasure, and...
A memory device verify system determines a state of memory cells in a memory. The memory includes a memory array having a plurality of memory cells coupled to...
US-7,196,930 Flash memory programming to reduce program disturb
The method for reducing program disturb in a flash memory array biases a selected wordline at a programming voltage. One of the unselected wordlines, closer to...
US-7,196,929 Method for operating a memory device having an amorphous silicon carbide gate insulator
A floating gate transistor has a reduced barrier energy at an interface with an adjacent amorphous silicon carbide (a-SiC) gate insulator, allowing faster charge...
← Previous | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 | Next →

File A Patent Application

  • Protect your idea -- Don't let someone else file first. Learn more.

  • 3 Easy Steps -- Complete Form, application Review, and File. See our process.

  • Attorney Review -- Have your application reviewed by a Patent Attorney. See what's included.