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Patent # Description
US-7,206,243 Method of rewriting a logic state of a memory cell
A method of operating a dynamic random access memory cell is disclosed. The true logic state of a stored bit is rewritten to a first storage node of the memory...
US-7,206,240 Fast sensing scheme for floating-gate memory cells
Sensing circuits are adapted for faster sensing of a programmed state of a floating-gate memory cell. The sensing circuits include a first precharging path for...
US-7,206,234 Input buffer for low voltage operation
Some embodiments of the invention include an input buffer having multiple differential amplifiers for receiving input signals to generate an output signal. The...
US-7,206,215 Antifuse having tantalum oxynitride film and method for making same
A capacitor has a tantalum oxynitride film. One method for making the film comprises forming a bottom plate electrode and then forming a tantalum oxide film on...
US-7,205,996 Full-scene anti-aliasing method and system
A method and system for performing full-scene anti-aliasing for an image through a technique of rotating and unrotating rasterization of a scene and rendering a...
US-7,205,661 Projected contact structures for engaging bumped semiconductor devices and methods of making the same
A bumped semiconductor device contact structure is disclosed including at least one non-planar contact pad having a plurality of projections extending therefrom...
US-7,205,656 Stacked device package for peripheral and center device pad layout device
An assembly method is disclosed that includes providing a substrate, securing a first semiconductor device on a first surface thereof, and superimposing at least...
US-7,205,654 Programmed material consolidation methods for fabricating heat sinks
Programmed material consolidation processes for fabricating heat sinks include the selective consolidation of previously unconsolidated material. The heat...
US-7,205,633 Capacitor layout orientation
The disclosed embodiments relate to a plurality of capacitive memory elements disposed on a substrate. The substrate may comprise a processor, a memory device or...
US-7,205,620 Highly reliable amorphous high-k gate dielectric ZrO.sub.xN.sub.y
A gate dielectric and method of fabricating a gate dielectric that produces a more reliable and thinner equivalent oxide thickness than conventional SiO.sub.2...
US-7,205,606 DRAM access transistor
Self-aligned recessed gate structures and method of formation are disclosed. Field oxide areas for isolation are first formed in a semiconductor substrate. A...
US-7,205,600 Capacitor constructions with a barrier layer to threshold voltage shift inducing material
A capacitor forming method can include forming an insulation layer over a substrate and forming a barrier layer to threshold voltage shift inducing material over...
US-7,205,599 Devices having improved capacitance
A capacitor formed by a process using only two deposition steps and a dielectric formed by oxidizing a metal layer in an electrolytic solution. The capacitor has...
US-7,205,598 Random access memory device utilizing a vertically oriented select transistor
A memory structure has a vertically oriented access transistor with an annular gate region. A transistor is fabricated such that the channel of the transistor...
US-7,205,584 Image sensor for reduced dark current
A method and structure for reducing dark current in an image sensor includes preventing unwanted electrons from being collected in the photosensitive region of...
US-7,205,526 Methods of fabricating layered lens structures
A microlens structure includes lower lens layers on a substrate. A sputtered layer of glass, such as silicon oxide, is applied over the lower lens layers at an...
US-7,205,248 Method of eliminating residual carbon from flowable oxide fill
Methods of forming an oxide layer such as high aspect ratio trench isolations, and treating the oxide substrate to remove carbon, structures formed by the...
US-7,205,245 Method of forming trench isolation within a semiconductor substrate
A method of etching silicon nitride substantially selectively relative to an oxide of aluminum includes providing a substrate comprising silicon nitride and an...
US-7,205,229 Interconnect alloys and methods and apparatus using same
Integrated circuit interconnect alloys having copper, silver or gold as the major constituent element. The resulting reduction in melting temperature allows for...
US-7,205,227 Methods of forming CMOS constructions
The invention includes methods for forming electrical connections associated with semiconductor constructions. A semiconductor substrate is provided which has a...
US-7,205,223 Method of forming an interconnect structure for a semiconductor device
A copper interconnect structure is disclosed as comprising a copper layer and an aluminum nitride layer formed over the copper layer. The aluminum nitride layer...
US-7,205,221 Under bump metallization pad and solder bump connections
The present invention relates to an improved method of forming and structure for under bump metallurgy ("UBM") pads for a flip chip which reduces the number of...
US-7,205,218 Method including forming gate dielectrics having multiple lanthanide oxide layers
A dielectric film having a layer of a lanthanide oxide and a layer of another lanthanide oxide, and a method of fabricating such a dielectric film produce a...
US-7,204,889 Method of reducing water spotting and oxide growth on a semiconductor structure
The present invention relates to a method of cleaning and drying a semiconductor structure in a modified conventional gas etch/rinse or dryer vessel.
US-7,204,885 Deposition system to provide preheating of chemical vapor deposition precursors
Chemical vapor deposition systems include elements to preheat reactant gases prior to reacting the gases to form layers of a material on a substrate, which...
US-7,203,874 Error detection, documentation, and correction in a flash memory device
A memory device has an error documentation memory array that is separate from the primary memory array. The error documentation memory array stores data relating...
US-7,203,124 System and method for negative word line driver circuit
A negative word line driver employs devices to maintain the potential difference between the active word line signal and the inactive word line signal while...
US-7,203,122 User selectable banks for DRAM
A memory device includes a configurable array of memory cells. A number of array banks is configured based upon data stored in a mode register or decoded by...
US-7,203,098 Methods of erasing flash memory
Methods for erasing flash memory using a decrease in magnitude of a source voltage of a first polarity to increase the magnitude of a control gate voltage of a...
US-7,203,093 Method and apparatus for reading NAND flash memory array
The method for reading/verifying a NAND flash memory device alternates the select gate biasing in response to the position of the cell to be read. If the cell is...
US-7,203,092 Flash memory array using adjacent bit line as source
A memory array having a plurality of flash memory cells arranged in rows and columns. A plurality of bit lines couple the columns such that alternate bit lines...
US-7,203,083 Longest match detection in a CAM
An apparatus and method for a CAM priority match detection circuit that identifies one or more CAM words from a group of CAM words having a "longest match" that...
US-7,202,894 Method and apparatus for real time identification and correction of pixel defects for image sensor arrays
An image processing system and method compares each pixel of an image obtained from an image sensor array with at least eight surrounding pixels of the same...
US-7,202,739 CMOS amplifiers with frequency compensating capacitors
The frequency and transient responses of a CMOS differential amplifier are improved by employing one or more compensating capacitors. A compensating capacitor...
US-7,202,681 Motherboard memory slot ribbon cable and apparatus
A testing apparatus, system and method for testing computer memory modules are disclosed. The apparatus includes a motherboard having a processor and at least...
US-7,202,562 Integrated circuit cooling system and method
A system and method for cooling an integrated circuit is provided. One aspect of this disclosure relates to a cooling system that utilizes sound waves to cool a...
US-7,202,556 Semiconductor package having substrate with multi-layer metal bumps
A semiconductor package includes a substrate formed of a board material, a semiconductor die bonded to the substrate, and an encapsulant on the die. The package...
US-7,202,543 Method and structure to reduce optical crosstalk in a solid state imager
Methods and structures to reduce optical crosstalk in solid state imager arrays. Sections of pixel material layers that previously would have been etched away...
US-7,202,530 Micro-mechanically strained semiconductor film
One aspect of the present subject matter relates to a method for forming strained semiconductor film. In various embodiments, a single crystalline semiconductor...
US-7,202,523 NROM flash memory devices on ultrathin silicon
An NROM flash memory cell is implemented in an ultra-thin silicon-on-insulator structure. In a planar device, the channel between the source/drain areas is...
US-7,202,520 Multiple data state memory cell
A programmable multiple data state memory cell including a first electrode layer formed from a first conductive material, a second electrode layer formed from a...
US-7,202,519 Memory cells having an access transistor with a source/drain region coupled to a capacitor through an extension
Fabrication of memory cell capacitors in an over/under configuration facilitates increased capacitance values for a given die area. A pair of memory cells...
US-7,202,183 Method of filling gaps and methods of depositing materials using high density plasma chemical vapor deposition
The invention includes a method of filling gaps in a semiconductor substrate. A substrate and a gas mixture containing at least one heavy-hydrogen compound are...
US-7,202,171 Method for forming a contact opening in a semiconductor device
A method of forming a self-aligned contact opening in an insulative layer formed over a substrate in a semiconductor device involves etching the insulative layer...
US-7,202,138 Spin coating for maximum fill characteristic yielding a planarized thin film surface
A method for spinning a material onto a semiconductor device structure so as to substantially fill recesses formed in a surface of the semiconductor device...
US-7,202,129 Source lines for NAND memory devices
A source line is formed by forming a source slot in a bulk insulation layer overlying a substrate to expose a portion of a substrate within the source slot,...
US-7,202,127 Methods of forming a plurality of capacitors
A plurality of capacitor electrode openings is formed within capacitor electrode-forming material. A first set of the openings is formed to a depth which is...
US-7,202,104 Co-sputter deposition of metal-doped chalcogenides
The present invention is related to methods and apparatus that allow a chalcogenide glass such as germanium selenide (Ge.sub.xSe.sub.1-x) to be doped with a...
US-7,202,098 Method and structure to reduce optical crosstalk in a solid state imager
Methods and structures to reduce optical crosstalk in solid state imager arrays. Sections of pixel material layers that previously would have been etched away...
US-7,201,635 Methods and systems for conditioning planarizing pads used in planarizing substrates
Monitoring the process of planarizing a workpiece, e.g., conditioning a CMP pad, can present some difficulties. Aspects of this invention provide methods and...
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