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Patent # Description
US-7,209,405 Memory device and method having multiple internal data buses and memory bank interleaving
A memory device and method receives write data through a unidirectional downstream bus and outputs read data through a unidirectional upstream bus. The...
US-7,209,403 Enhanced fuse configurations for low-voltage flash memories
An enhanced fuse circuit is discussed that advances redundancy techniques in integrated circuits. The enhanced fuse circuit uses a single nonvolatile fuse and a...
US-7,209,387 Non-volatile programmable fuse apparatus in a flash memory with pairs of supercells programmed in a...
The non-volatile, programmable fuse apparatus has a pair of p-channel transistors coupled in a latch configuration. A supercell is coupled between each...
US-7,209,378 Columnar 1T-N memory cell structure
A memory array architecture incorporates certain advantages from both cross-point and 1T-1Cell architectures during reading operations. The fast read-time and...
US-7,209,359 Universal memory module/PCB storage, transport, automation handling tray
An adjustable tray for a semiconductor device, and method of using the tray for handling the device, are provided. Each tray comprises a front frame segment and...
US-7,209,173 Methods of operating photodiode-type pixel and imager device
Operation for global electronic shutter photodiode-type pixels. In a first mode of operation, lag is reduced through global reset of the photodiode array and...
US-7,209,168 Defective pixel correction method and system
A defective pixel detection and correction mechanism for use in an image sensor integrated circuit determines whether a current pixel is a defective pixel in a...
US-7,209,166 Wide dynamic range operation for CMOS sensor with freeze-frame shutter
Wide dynamic range operation is used to write a signal in a freeze-frame pixel into the memory twice, first after short integration and then after long...
US-7,208,989 Synchronous clock generator including duty cycle correction
A clock generator for generating an output clock signal synchronized with an input clock signal and having a corrected duty cycle. The clock generator includes...
US-7,208,986 Measure-controlled delay circuits with reduced phase error
Measure-controlled delay (MCD) circuits are provided for synchronizing an output clock to an input clock. In response to triggering of a measure circuit, sample...
US-7,208,959 Methods for measuring parasitic capacitance and inductance of I/O leads on an electrical component using a...
Methods are provided for measuring the potential for mutual coupling in an integrated circuit package of any type or configuration using a network analyzer in...
US-7,208,935 Apparatus for measuring parasitic capacitance and inductance of I/O leads on an electrical component using a...
Apparatus and methods are provided for measuring the potential for mutual coupling in an integrated circuit package of any type or configuration using a network...
US-7,208,839 Semiconductor component assemblies having interconnects
Methods relating to forming interconnects through injection of conductive materials, to fabricating semiconductor component assemblies, and to resulting...
US-7,208,836 Integrated circuitry and a semiconductor processing method of forming a series of conductive lines
A semiconductor processing method of forming a plurality of conductive lines includes, a) providing a substrate; b) providing a first conductive material layer...
US-7,208,828 Semiconductor package with wire bonded stacked dice and multi-layer metal bumps
A semiconductor package includes a substrate formed of a board material, a semiconductor die bonded to the substrate, and an encapsulant on the die. The package...
US-7,208,813 Capacitor layout orientation
The disclosed embodiments relate to a plurality of capacitive memory elements disposed on a substrate. The substrate may comprise a processor, a memory device or...
US-7,208,805 Structures comprising a layer free of nitrogen between silicon nitride and photoresist
The invention includes a semiconductor processing method. A first material comprising silicon and nitrogen is formed. A second material is formed over the first...
US-7,208,804 Crystalline or amorphous medium-K gate oxides, Y.sub.20.sub.3 and Gd.sub.20.sub.3
A gate oxide and method of fabricating a gate oxide that produces a more reliable and thinner equivalent oxide thickness than conventional SiO.sub.2 gate oxides...
US-7,208,793 Scalable integrated logic and non-volatile memory
A scalable, logic transistor has a pair of doped regions for the drain and source. A gate insulator layer is formed over the substrate and between the drain and...
US-7,208,783 Optical enhancement of integrated circuit photodetectors
A semiconductor integrated circuit structure and method for fabricating. The semiconductor integrated circuit structure includes a light sensitive device...
US-7,208,758 Dynamic integrated circuit clusters, modules including same and methods of fabricating
A semiconductor wafer or other bulk semiconductor substrate having a plurality of dice thereon is manufactured using conventional processing techniques. The...
US-7,208,412 Method of forming metal oxide and semimetal oxide
The invention includes methods of forming metal oxide and/or semimetal oxide. The invention can include formation of at least one metal-and-halogen-containing...
US-7,208,410 Methods relating to forming interconnects
Methods relating to forming interconnects through injection of conductive materials, to fabricating semiconductor component assemblies, and to resulting...
US-7,208,407 Flash memory cells with reduced distances between cell elements
An anti-reflective coating (ARC) is formed over the various layers involved in a cell fabrication process. The ARC is selectively etched such that the edges of...
US-7,208,368 Methods of forming spaced conductive regions, and methods of forming capacitor constructions
The invention includes a method of forming spaced conductive regions. A construction is formed which includes a first electrically conductive material over a...
US-7,208,335 Castellated chip-scale packages and methods for fabricating the same
A method for fabricating a chip-scale package includes securing a device substrate that carries at least two adjacent semiconductor devices to a sacrificial...
US-7,208,323 Method for forming magneto-resistive memory cells with shape anisotropy
A magneto-resistive memory comprising magneto-resistive memory cells is disclosed, comprising a pinned magnetic layer and a free magnetic layer. The two magnetic...
US-7,208,198 Chemical vapor deposition methods of forming barium strontium titanate comprising dielectric layers, including...
The invention includes a chemical vapor deposition method of forming a barium strontium titanate comprising dielectric layer having a varied concentration of...
US-7,206,956 Duty cycle distortion compensation for the data output of a memory device
A technique for compensating for duty cycle distortion in an output data signal generated by a synchronous dynamic random access memory device (SDRAM) is...
US-7,206,909 Host memory interface for a parallel processor
A memory interface for a parallel processor which has an array of processing elements and can receive a memory address and supply the memory address to a memory...
US-7,206,887 System and method for memory hub-based expansion bus
A system memory includes a memory hub controller, a memory module accessible by the memory hub controller, and an expansion module having a processor circuit...
US-7,206,800 Overflow detection and clamping with parallel operand processing for fixed-point multipliers
A method and apparatus for overflow detection and clamping with parallel operand processing for fixed-point multipliers is disclosed. The invention predicts when...
US-7,206,447 Image sensing system with histogram modification
A histogram is modified by using an adaptive system. Two different thresholds are set: a threshold of a number of pixels which can be changed, and another...
US-7,206,243 Method of rewriting a logic state of a memory cell
A method of operating a dynamic random access memory cell is disclosed. The true logic state of a stored bit is rewritten to a first storage node of the memory...
US-7,206,240 Fast sensing scheme for floating-gate memory cells
Sensing circuits are adapted for faster sensing of a programmed state of a floating-gate memory cell. The sensing circuits include a first precharging path for...
US-7,206,234 Input buffer for low voltage operation
Some embodiments of the invention include an input buffer having multiple differential amplifiers for receiving input signals to generate an output signal. The...
US-7,206,215 Antifuse having tantalum oxynitride film and method for making same
A capacitor has a tantalum oxynitride film. One method for making the film comprises forming a bottom plate electrode and then forming a tantalum oxide film on...
US-7,205,996 Full-scene anti-aliasing method and system
A method and system for performing full-scene anti-aliasing for an image through a technique of rotating and unrotating rasterization of a scene and rendering a...
US-7,205,661 Projected contact structures for engaging bumped semiconductor devices and methods of making the same
A bumped semiconductor device contact structure is disclosed including at least one non-planar contact pad having a plurality of projections extending therefrom...
US-7,205,656 Stacked device package for peripheral and center device pad layout device
An assembly method is disclosed that includes providing a substrate, securing a first semiconductor device on a first surface thereof, and superimposing at least...
US-7,205,654 Programmed material consolidation methods for fabricating heat sinks
Programmed material consolidation processes for fabricating heat sinks include the selective consolidation of previously unconsolidated material. The heat...
US-7,205,633 Capacitor layout orientation
The disclosed embodiments relate to a plurality of capacitive memory elements disposed on a substrate. The substrate may comprise a processor, a memory device or...
US-7,205,620 Highly reliable amorphous high-k gate dielectric ZrO.sub.xN.sub.y
A gate dielectric and method of fabricating a gate dielectric that produces a more reliable and thinner equivalent oxide thickness than conventional SiO.sub.2...
US-7,205,606 DRAM access transistor
Self-aligned recessed gate structures and method of formation are disclosed. Field oxide areas for isolation are first formed in a semiconductor substrate. A...
US-7,205,600 Capacitor constructions with a barrier layer to threshold voltage shift inducing material
A capacitor forming method can include forming an insulation layer over a substrate and forming a barrier layer to threshold voltage shift inducing material over...
US-7,205,599 Devices having improved capacitance
A capacitor formed by a process using only two deposition steps and a dielectric formed by oxidizing a metal layer in an electrolytic solution. The capacitor has...
US-7,205,598 Random access memory device utilizing a vertically oriented select transistor
A memory structure has a vertically oriented access transistor with an annular gate region. A transistor is fabricated such that the channel of the transistor...
US-7,205,584 Image sensor for reduced dark current
A method and structure for reducing dark current in an image sensor includes preventing unwanted electrons from being collected in the photosensitive region of...
US-7,205,526 Methods of fabricating layered lens structures
A microlens structure includes lower lens layers on a substrate. A sputtered layer of glass, such as silicon oxide, is applied over the lower lens layers at an...
US-7,205,248 Method of eliminating residual carbon from flowable oxide fill
Methods of forming an oxide layer such as high aspect ratio trench isolations, and treating the oxide substrate to remove carbon, structures formed by the...
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