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Patent # Description
US-7,196,882 Magnetic tunnel junction device and its method of fabrication
The present invention provides a magnetic tunnel junction memory element comprising two pinned ferromagnetic layers having magnetic orientations pointing in...
US-7,196,829 Digital image system and method for combining sensing and image processing on sensor with two-color photo-detector
A digital image system is disclosed having a sensor with an elevated two-color photo-detector for sensing two different color values in combination with a...
US-7,196,544 Communication device for a logic circuit
A circuit is provided to isolate a contact pad from a logic circuit of a die once the contact pad is no longer needed. This circuit can take many forms including...
US-7,196,394 Method and apparatus for a deposited fill layer
A method of forming a semiconducting wafer is provided that utilizes fewer processing operations, reduces process variation, and lowers cost as well as...
US-7,196,304 Row driver for selectively supplying operating power to imager pixel
An imaging system includes a pixel that does not require a row select transistor. Instead, an operating voltage is selectively provided to the pixel's readout...
US-7,196,020 Method for PECVD deposition of selected material films
A process for PECVD of selected material films on a substrate comprising the steps of placing a substrate in a PECVD chamber and maintaining the chamber under...
US-7,196,007 Systems and methods of forming refractory metal nitride layers using disilazanes
A method of forming (and apparatus for forming) refractory metal nitride layers (including silicon nitride layers), such as a tantalum (silicon) nitride barrier...
US-7,195,999 Metal-substituted transistor gates
One aspect of this disclosure relates to a method for forming a transistor. According to various method embodiments, a gate dielectric is formed on a substrate,...
US-7,195,995 Method of manufacturing a multilayered doped conductor for a contact in an integrated circuit device
A method of manufacturing a memory device addressing reliability and refresh characteristics through the use of a multilayered doped conductor, and a method...
US-7,195,957 Packaged microelectronic components
A microelectronic component package includes a plurality of electrical leads which are coupled to a microelectronic component and which have exposed lengths...
US-7,195,947 Photodiode with self-aligned implants for high quantum efficiency and method of formation
A pinned photodiode with a pinned surface layer formed by a self-aligned angled implant is disclosed. The angle of the implant may be tailored to provide an...
US-7,195,940 Methods for packaging image sensitive electronic devices
The invention provides methods for packaging for electronic devices that are light or other radiation-sensitive, such as image sensors including CCD or CMOS...
US-7,194,667 System for storing device test information on a semiconductor device using on-device logic for determination of...
A system for testing a semiconductor device and storing device test results in nonvolatile memory elements on the tested device, in which the semiconductor...
US-7,194,593 Memory hub with integrated non-volatile memory
A memory hub having an integrated non-volatile memory for storing configuration information is provided. The memory hub includes a high-speed interface for...
US-7,193,927 Memory device and method having banks of different sizes
A memory device, such as a synchronous random access memory device, includes four banks of memory cells arranged in rows and columns. Different numbers of...
US-7,193,914 Open digit line array architecture for a memory array
A system and method for sensing a data state stored by a memory cell that includes coupling a first digit line and a second digit line to a precharge voltage and...
US-7,193,910 Adjustable timing circuit of an integrated circuit
An adjustable timing circuit includes non-volatile programmable fuses and adjustable delay elements. A propagation time of the delay element is selected with the...
US-7,193,899 Erase block data splitting
A Flash memory device, system, and data handling routine is detailed with a distributed erase block sector user/overhead data scheme that splits the user data...
US-7,193,893 Write once read only memory employing floating gates
Structures and methods for write once read only memory employing floating gates are provided. The write once read only memory cell includes a floating gate...
US-7,193,312 Castellation wafer level packaging of integrated circuit chips
Systems and methods for packaging integrated circuit chips in castellation wafer level packaging are provided. The active circuit areas of the chips are coupled...
US-7,193,306 Semiconductor structure having stacked semiconductor devices
A semiconductor structure includes flip chips or other semiconductor devices that are mounted on printed circuit boards. The printed circuit boards are stacked...
US-7,193,285 Tilted array geometry for improved MRAM switching
An array of conductive lines for MRAM circuits wherein at least one set of mutually parallel conductive traces is tilted with respect to being perpendicular with...
US-7,193,273 Method for enhancing vertical growth during the selective formation of silicon, and structures formed using same
A method of selectively forming contact regions on a substrate having a plurality of exposed regions includes selectively forming a contact region on each of the...
US-7,193,266 Strapping word lines of NAND memory devices
Apparatus and methods are provided. Conductive straps are connected to a subset of word lines of a memory device. Alternatively, first conductive straps are...
US-7,192,893 Use of linear injectors to deposit uniform selective ozone TEOS oxide film by pulsing reactants on and off
A process for enhanced selective deposition of a silicon oxide onto a substrate by pulsing delivery of the reactants through a linear injector is disclosed. The...
US-7,192,892 Atomic layer deposited dielectric layers
An atomic layer deposited dielectric layer and a method of fabricating such a dielectric layer produce a reliable dielectric layer having an equivalent oxide...
US-7,192,889 Methods for forming a high dielectric film
A method of forming a high dielectric oxide film conventionally formed using a post formation oxygen anneal to reduce the leakage current of such film includes...
US-7,192,888 Low selectivity deposition methods
A deposition method includes forming a nucleation layer over a substrate, forming a layer of a first substance at least one monolayer thick chemisorbed on the...
US-7,192,829 Methods of forming floating gate transistors
Floating gate transistors and methods of forming the same are described. In one implementation, a floating gate is formed over a substrate. The floating gate has...
US-7,192,828 Capacitor with high dielectric constant materials and method of making
A stabilized capacitor using non-oxide electrodes and high dielectric constant oxide dielectric materials and methods of making such capacitors and their...
US-7,192,827 Methods of forming capacitor structures
The invention includes a method of forming a capacitor structure. A first electrical node is formed, and a layer of metallic aluminum is formed over the first...
US-7,192,824 Lanthanide oxide / hafnium oxide dielectric layers
Dielectric layers containing an atomic layer deposited hafnium oxide and an electron beam evaporated lanthanide oxide and a method of fabricating such a...
US-7,192,806 Method of establishing non-permanent electrical connection between an integrated circuit device lead element...
A spring contact for establishing electrical contact between a lead element of an IC device and a substrate. The spring contact generally comprises a contact...
US-7,192,495 Intermediate anneal for metal deposition
The present teachings and illustrations describe a process for forming a plurality of conductive structures in or on a substrate. In one embodiment, the process...
US-7,192,487 Semiconductor substrate processing chamber and accessory attachment interfacial structure
A semiconductor substrate processor includes a substrate transfer chamber and a plurality of substrate processing chambers connected therewith. An interfacial...
US-7,192,336 Method and apparatus for forming and using planarizing pads for mechanical and chemical-mechanical...
Methods and apparatuses for planarizing a microelectronic substrate. In one aspect of the invention, a first portion of an energy-sensitive, non-sacrificial...
US-7,192,335 Method and apparatus for chemically, mechanically, and/or electrolytically removing material from...
Method and apparatus for chemically, mechanically and/or electrolytically removing material from microelectronic substrates. A polishing medium for removing...
US-7,192,311 Apparatus for forming modular sockets using flexible interconnects and resulting structures
A modular bare die socket assembly is provided for attaching a plurality of miniature semiconductor dice to a substrate. The socket assembly is comprised of a...
US-7,191,409 Method and apparatus for programming hot keys based on user interests
A system is provided that configures a computer keyboard hot key based upon user interests. The system determines a profile of interests for a user, selects a...
US-7,191,345 BIOS lock encode/decode driver
Systems and methods for preventing the unauthorized access to data stored on removable media, such as software, include storing a predetermined signature in the...
US-7,190,736 Technique to simultaneously distribute clock signals and data on integrated circuits, interposers, and circuit...
A technique is described for simultaneously and synchronously transmitting digital data and a clock signal in a digital integrated circuit, circuit board, or...
US-7,190,629 Circuit and method for reading an antifuse
An antifuse circuit and antifuse reading method for determining whether an antifuse is programmed or un-programmed. An antifuse circuit includes a sensing...
US-7,190,625 Method and apparatus for data compression in memory devices
A test circuit for a memory device having a pair of arrays each of which includes a plurality of memory cells arranged in rows and columns. A pair of...
US-7,190,622 Method and architecture to calibrate read operations in synchronous flash memory
Architecture to calibrate read operations in non-volatile memory devices. In one embodiment, a synchronous flash memory is disclosed. The synchronous flash...
US-7,190,616 In-service reconfigurable DRAM and flash memory device
A memory cell that has both a DRAM cell and a non-volatile memory cell. The non-volatile memory cell might include a flash memory or an NROM cell. The memory...
US-7,190,610 Latch-up prevention for memory cells
An SRAM memory cell is provided having a pair of cross-coupled CMOS inverters. The sources of the pull-up transistors forming each of the CMOS inverters are...
US-7,190,608 Sensing of resistance variable memory devices
A resistance variable memory device such as e.g., a PCRAM memory device, with either a 4T (transistor) or 2T memory cell configuration and either a dual cell...
US-7,190,397 CMOS imager decoder structure
A decoder apparatus for selecting column lines of a CMOS imager pixel array is disclosed. The decoder apparatus is made up of at least one first decoder and at...
US-7,190,394 Method for statistical analysis of images for automatic white balance of color channel gains for image sensors
A process for performing white balancing of an image is performed by subdividing an image into a plurality of subframes, and then analyzing each subframe to...
US-7,190,081 Mold gates and tape substrates including the mold gates
A mold gate of a tape substrate includes an aperture formed in the flexible dielectric film of the tape substrate and a support element which is carried by a...
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