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Patent # Description
US-7,208,783 Optical enhancement of integrated circuit photodetectors
A semiconductor integrated circuit structure and method for fabricating. The semiconductor integrated circuit structure includes a light sensitive device...
US-7,208,758 Dynamic integrated circuit clusters, modules including same and methods of fabricating
A semiconductor wafer or other bulk semiconductor substrate having a plurality of dice thereon is manufactured using conventional processing techniques. The...
US-7,208,412 Method of forming metal oxide and semimetal oxide
The invention includes methods of forming metal oxide and/or semimetal oxide. The invention can include formation of at least one metal-and-halogen-containing...
US-7,208,410 Methods relating to forming interconnects
Methods relating to forming interconnects through injection of conductive materials, to fabricating semiconductor component assemblies, and to resulting...
US-7,208,407 Flash memory cells with reduced distances between cell elements
An anti-reflective coating (ARC) is formed over the various layers involved in a cell fabrication process. The ARC is selectively etched such that the edges of...
US-7,208,368 Methods of forming spaced conductive regions, and methods of forming capacitor constructions
The invention includes a method of forming spaced conductive regions. A construction is formed which includes a first electrically conductive material over a...
US-7,208,335 Castellated chip-scale packages and methods for fabricating the same
A method for fabricating a chip-scale package includes securing a device substrate that carries at least two adjacent semiconductor devices to a sacrificial...
US-7,208,323 Method for forming magneto-resistive memory cells with shape anisotropy
A magneto-resistive memory comprising magneto-resistive memory cells is disclosed, comprising a pinned magnetic layer and a free magnetic layer. The two magnetic...
US-7,208,198 Chemical vapor deposition methods of forming barium strontium titanate comprising dielectric layers, including...
The invention includes a chemical vapor deposition method of forming a barium strontium titanate comprising dielectric layer having a varied concentration of...
US-7,206,956 Duty cycle distortion compensation for the data output of a memory device
A technique for compensating for duty cycle distortion in an output data signal generated by a synchronous dynamic random access memory device (SDRAM) is...
US-7,206,909 Host memory interface for a parallel processor
A memory interface for a parallel processor which has an array of processing elements and can receive a memory address and supply the memory address to a memory...
US-7,206,887 System and method for memory hub-based expansion bus
A system memory includes a memory hub controller, a memory module accessible by the memory hub controller, and an expansion module having a processor circuit...
US-7,206,800 Overflow detection and clamping with parallel operand processing for fixed-point multipliers
A method and apparatus for overflow detection and clamping with parallel operand processing for fixed-point multipliers is disclosed. The invention predicts when...
US-7,206,447 Image sensing system with histogram modification
A histogram is modified by using an adaptive system. Two different thresholds are set: a threshold of a number of pixels which can be changed, and another...
US-7,206,243 Method of rewriting a logic state of a memory cell
A method of operating a dynamic random access memory cell is disclosed. The true logic state of a stored bit is rewritten to a first storage node of the memory...
US-7,206,240 Fast sensing scheme for floating-gate memory cells
Sensing circuits are adapted for faster sensing of a programmed state of a floating-gate memory cell. The sensing circuits include a first precharging path for...
US-7,206,234 Input buffer for low voltage operation
Some embodiments of the invention include an input buffer having multiple differential amplifiers for receiving input signals to generate an output signal. The...
US-7,206,215 Antifuse having tantalum oxynitride film and method for making same
A capacitor has a tantalum oxynitride film. One method for making the film comprises forming a bottom plate electrode and then forming a tantalum oxide film on...
US-7,205,996 Full-scene anti-aliasing method and system
A method and system for performing full-scene anti-aliasing for an image through a technique of rotating and unrotating rasterization of a scene and rendering a...
US-7,205,661 Projected contact structures for engaging bumped semiconductor devices and methods of making the same
A bumped semiconductor device contact structure is disclosed including at least one non-planar contact pad having a plurality of projections extending therefrom...
US-7,205,656 Stacked device package for peripheral and center device pad layout device
An assembly method is disclosed that includes providing a substrate, securing a first semiconductor device on a first surface thereof, and superimposing at least...
US-7,205,654 Programmed material consolidation methods for fabricating heat sinks
Programmed material consolidation processes for fabricating heat sinks include the selective consolidation of previously unconsolidated material. The heat...
US-7,205,633 Capacitor layout orientation
The disclosed embodiments relate to a plurality of capacitive memory elements disposed on a substrate. The substrate may comprise a processor, a memory device or...
US-7,205,620 Highly reliable amorphous high-k gate dielectric ZrO.sub.xN.sub.y
A gate dielectric and method of fabricating a gate dielectric that produces a more reliable and thinner equivalent oxide thickness than conventional SiO.sub.2...
US-7,205,606 DRAM access transistor
Self-aligned recessed gate structures and method of formation are disclosed. Field oxide areas for isolation are first formed in a semiconductor substrate. A...
US-7,205,600 Capacitor constructions with a barrier layer to threshold voltage shift inducing material
A capacitor forming method can include forming an insulation layer over a substrate and forming a barrier layer to threshold voltage shift inducing material over...
US-7,205,599 Devices having improved capacitance
A capacitor formed by a process using only two deposition steps and a dielectric formed by oxidizing a metal layer in an electrolytic solution. The capacitor has...
US-7,205,598 Random access memory device utilizing a vertically oriented select transistor
A memory structure has a vertically oriented access transistor with an annular gate region. A transistor is fabricated such that the channel of the transistor...
US-7,205,584 Image sensor for reduced dark current
A method and structure for reducing dark current in an image sensor includes preventing unwanted electrons from being collected in the photosensitive region of...
US-7,205,526 Methods of fabricating layered lens structures
A microlens structure includes lower lens layers on a substrate. A sputtered layer of glass, such as silicon oxide, is applied over the lower lens layers at an...
US-7,205,248 Method of eliminating residual carbon from flowable oxide fill
Methods of forming an oxide layer such as high aspect ratio trench isolations, and treating the oxide substrate to remove carbon, structures formed by the...
US-7,205,245 Method of forming trench isolation within a semiconductor substrate
A method of etching silicon nitride substantially selectively relative to an oxide of aluminum includes providing a substrate comprising silicon nitride and an...
US-7,205,229 Interconnect alloys and methods and apparatus using same
Integrated circuit interconnect alloys having copper, silver or gold as the major constituent element. The resulting reduction in melting temperature allows for...
US-7,205,227 Methods of forming CMOS constructions
The invention includes methods for forming electrical connections associated with semiconductor constructions. A semiconductor substrate is provided which has a...
US-7,205,223 Method of forming an interconnect structure for a semiconductor device
A copper interconnect structure is disclosed as comprising a copper layer and an aluminum nitride layer formed over the copper layer. The aluminum nitride layer...
US-7,205,221 Under bump metallization pad and solder bump connections
The present invention relates to an improved method of forming and structure for under bump metallurgy ("UBM") pads for a flip chip which reduces the number of...
US-7,205,218 Method including forming gate dielectrics having multiple lanthanide oxide layers
A dielectric film having a layer of a lanthanide oxide and a layer of another lanthanide oxide, and a method of fabricating such a dielectric film produce a...
US-7,204,889 Method of reducing water spotting and oxide growth on a semiconductor structure
The present invention relates to a method of cleaning and drying a semiconductor structure in a modified conventional gas etch/rinse or dryer vessel.
US-7,204,885 Deposition system to provide preheating of chemical vapor deposition precursors
Chemical vapor deposition systems include elements to preheat reactant gases prior to reacting the gases to form layers of a material on a substrate, which...
US-7,203,874 Error detection, documentation, and correction in a flash memory device
A memory device has an error documentation memory array that is separate from the primary memory array. The error documentation memory array stores data relating...
US-7,203,124 System and method for negative word line driver circuit
A negative word line driver employs devices to maintain the potential difference between the active word line signal and the inactive word line signal while...
US-7,203,122 User selectable banks for DRAM
A memory device includes a configurable array of memory cells. A number of array banks is configured based upon data stored in a mode register or decoded by...
US-7,203,098 Methods of erasing flash memory
Methods for erasing flash memory using a decrease in magnitude of a source voltage of a first polarity to increase the magnitude of a control gate voltage of a...
US-7,203,093 Method and apparatus for reading NAND flash memory array
The method for reading/verifying a NAND flash memory device alternates the select gate biasing in response to the position of the cell to be read. If the cell is...
US-7,203,092 Flash memory array using adjacent bit line as source
A memory array having a plurality of flash memory cells arranged in rows and columns. A plurality of bit lines couple the columns such that alternate bit lines...
US-7,203,083 Longest match detection in a CAM
An apparatus and method for a CAM priority match detection circuit that identifies one or more CAM words from a group of CAM words having a "longest match" that...
US-7,202,894 Method and apparatus for real time identification and correction of pixel defects for image sensor arrays
An image processing system and method compares each pixel of an image obtained from an image sensor array with at least eight surrounding pixels of the same...
US-7,202,739 CMOS amplifiers with frequency compensating capacitors
The frequency and transient responses of a CMOS differential amplifier are improved by employing one or more compensating capacitors. A compensating capacitor...
US-7,202,681 Motherboard memory slot ribbon cable and apparatus
A testing apparatus, system and method for testing computer memory modules are disclosed. The apparatus includes a motherboard having a processor and at least...
US-7,202,562 Integrated circuit cooling system and method
A system and method for cooling an integrated circuit is provided. One aspect of this disclosure relates to a cooling system that utilizes sound waves to cool a...
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