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Magnetic tunnel junction device and its method of fabrication
The present invention provides a magnetic tunnel junction memory element comprising two pinned ferromagnetic layers having magnetic orientations pointing in...
Digital image system and method for combining sensing and image processing
on sensor with two-color photo-detector
A digital image system is disclosed having a sensor with an elevated two-color photo-detector for sensing two different color values in combination with a...
Communication device for a logic circuit
A circuit is provided to isolate a contact pad from a logic circuit of a die once the contact pad is no longer needed. This circuit can take many forms including...
Method and apparatus for a deposited fill layer
A method of forming a semiconducting wafer is provided that utilizes fewer processing operations, reduces process variation, and lowers cost as well as...
Row driver for selectively supplying operating power to imager pixel
An imaging system includes a pixel that does not require a row select transistor. Instead, an operating voltage is selectively provided to the pixel's readout...
Method for PECVD deposition of selected material films
A process for PECVD of selected material films on a substrate comprising the steps of placing a substrate in a PECVD chamber and maintaining the chamber under...
Systems and methods of forming refractory metal nitride layers using
A method of forming (and apparatus for forming) refractory metal nitride layers (including silicon nitride layers), such as a tantalum (silicon) nitride barrier...
Metal-substituted transistor gates
One aspect of this disclosure relates to a method for forming a transistor. According to various method embodiments, a gate dielectric is formed on a substrate,...
Method of manufacturing a multilayered doped conductor for a contact in an
integrated circuit device
A method of manufacturing a memory device addressing reliability and refresh characteristics through the use of a multilayered doped conductor, and a method...
Packaged microelectronic components
A microelectronic component package includes a plurality of electrical leads which are coupled to a microelectronic component and which have exposed lengths...
Photodiode with self-aligned implants for high quantum efficiency and
method of formation
A pinned photodiode with a pinned surface layer formed by a self-aligned angled implant is disclosed. The angle of the implant may be tailored to provide an...
Methods for packaging image sensitive electronic devices
The invention provides methods for packaging for electronic devices that are light or other radiation-sensitive, such as image sensors including CCD or CMOS...
System for storing device test information on a semiconductor device using
on-device logic for determination of...
A system for testing a semiconductor device and storing device test results in nonvolatile memory elements on the tested device, in which the semiconductor...
Memory hub with integrated non-volatile memory
A memory hub having an integrated non-volatile memory for storing configuration information is provided. The memory hub includes a high-speed interface for...
Memory device and method having banks of different sizes
A memory device, such as a synchronous random access memory device, includes four banks of memory cells arranged in rows and columns. Different numbers of...
Open digit line array architecture for a memory array
A system and method for sensing a data state stored by a memory cell that includes coupling a first digit line and a second digit line to a precharge voltage and...
Adjustable timing circuit of an integrated circuit
An adjustable timing circuit includes non-volatile programmable fuses and adjustable delay elements. A propagation time of the delay element is selected with the...
Erase block data splitting
A Flash memory device, system, and data handling routine is detailed with a distributed erase block sector user/overhead data scheme that splits the user data...
Write once read only memory employing floating gates
Structures and methods for write once read only memory employing floating gates are provided. The write once read only memory cell includes a floating gate...
Castellation wafer level packaging of integrated circuit chips
Systems and methods for packaging integrated circuit chips in castellation wafer level packaging are provided. The active circuit areas of the chips are coupled...
Semiconductor structure having stacked semiconductor devices
A semiconductor structure includes flip chips or other semiconductor devices that are mounted on printed circuit boards. The printed circuit boards are stacked...
Tilted array geometry for improved MRAM switching
An array of conductive lines for MRAM circuits wherein at least one set of mutually parallel conductive traces is tilted with respect to being perpendicular with...
Method for enhancing vertical growth during the selective formation of
silicon, and structures formed using same
A method of selectively forming contact regions on a substrate having a plurality of exposed regions includes selectively forming a contact region on each of the...
Strapping word lines of NAND memory devices
Apparatus and methods are provided. Conductive straps are connected to a subset of word lines of a memory device. Alternatively, first conductive straps are...
Use of linear injectors to deposit uniform selective ozone TEOS oxide film
by pulsing reactants on and off
A process for enhanced selective deposition of a silicon oxide onto a substrate by pulsing delivery of the reactants through a linear injector is disclosed. The...
Atomic layer deposited dielectric layers
An atomic layer deposited dielectric layer and a method of fabricating such a dielectric layer produce a reliable dielectric layer having an equivalent oxide...
Methods for forming a high dielectric film
A method of forming a high dielectric oxide film conventionally formed using a post formation oxygen anneal to reduce the leakage current of such film includes...
Low selectivity deposition methods
A deposition method includes forming a nucleation layer over a substrate, forming a layer of a first substance at least one monolayer thick chemisorbed on the...
Methods of forming floating gate transistors
Floating gate transistors and methods of forming the same are described. In one implementation, a floating gate is formed over a substrate. The floating gate has...
Capacitor with high dielectric constant materials and method of making
A stabilized capacitor using non-oxide electrodes and high dielectric constant oxide dielectric materials and methods of making such capacitors and their...
Methods of forming capacitor structures
The invention includes a method of forming a capacitor structure. A first electrical node is formed, and a layer of metallic aluminum is formed over the first...
Lanthanide oxide / hafnium oxide dielectric layers
Dielectric layers containing an atomic layer deposited hafnium oxide and an electron beam evaporated lanthanide oxide and a method of fabricating such a...
Method of establishing non-permanent electrical connection between an
integrated circuit device lead element...
A spring contact for establishing electrical contact between a lead element of an IC device and a substrate. The spring contact generally comprises a contact...
Intermediate anneal for metal deposition
The present teachings and illustrations describe a process for forming a plurality of conductive structures in or on a substrate. In one embodiment, the process...
Semiconductor substrate processing chamber and accessory attachment
A semiconductor substrate processor includes a substrate transfer chamber and a plurality of substrate processing chambers connected therewith. An interfacial...
Method and apparatus for forming and using planarizing pads for mechanical
Methods and apparatuses for planarizing a microelectronic substrate. In one aspect of the invention, a first portion of an energy-sensitive, non-sacrificial...
Method and apparatus for chemically, mechanically, and/or electrolytically
removing material from...
Method and apparatus for chemically, mechanically and/or electrolytically removing material from microelectronic substrates. A polishing medium for removing...
Apparatus for forming modular sockets using flexible interconnects and
A modular bare die socket assembly is provided for attaching a plurality of miniature semiconductor dice to a substrate. The socket assembly is comprised of a...
Method and apparatus for programming hot keys based on user interests
A system is provided that configures a computer keyboard hot key based upon user interests. The system determines a profile of interests for a user, selects a...
BIOS lock encode/decode driver
Systems and methods for preventing the unauthorized access to data stored on removable media, such as software, include storing a predetermined signature in the...
Technique to simultaneously distribute clock signals and data on
integrated circuits, interposers, and circuit...
A technique is described for simultaneously and synchronously transmitting digital data and a clock signal in a digital integrated circuit, circuit board, or...
Circuit and method for reading an antifuse
An antifuse circuit and antifuse reading method for determining whether an antifuse is programmed or un-programmed. An antifuse circuit includes a sensing...
Method and apparatus for data compression in memory devices
A test circuit for a memory device having a pair of arrays each of which includes a plurality of memory cells arranged in rows and columns. A pair of...
Method and architecture to calibrate read operations in synchronous flash
Architecture to calibrate read operations in non-volatile memory devices. In one embodiment, a synchronous flash memory is disclosed. The synchronous flash...
In-service reconfigurable DRAM and flash memory device
A memory cell that has both a DRAM cell and a non-volatile memory cell. The non-volatile memory cell might include a flash memory or an NROM cell. The memory...
Latch-up prevention for memory cells
An SRAM memory cell is provided having a pair of cross-coupled CMOS inverters. The sources of the pull-up transistors forming each of the CMOS inverters are...
Sensing of resistance variable memory devices
A resistance variable memory device such as e.g., a PCRAM memory device, with either a 4T (transistor) or 2T memory cell configuration and either a dual cell...
CMOS imager decoder structure
A decoder apparatus for selecting column lines of a CMOS imager pixel array is disclosed. The decoder apparatus is made up of at least one first decoder and at...
Method for statistical analysis of images for automatic white balance of
color channel gains for image sensors
A process for performing white balancing of an image is performed by subdividing an image into a plurality of subframes, and then analyzing each subframe to...
Mold gates and tape substrates including the mold gates
A mold gate of a tape substrate includes an aperture formed in the flexible dielectric film of the tape substrate and a support element which is carried by a...