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Patent # Description
US-9,324,423 Apparatuses and methods for bi-directional access of cross-point arrays
The disclosed technology generally relates to apparatuses and methods of operating the same, and more particularly to cross point memory arrays and methods of...
US-9,324,410 Semiconductor memory device having an output buffer controller
A device includes a data output terminal, an output buffer including n first transistors (n is a natural number greater than 1) connected in parallel with the...
US-9,324,398 Apparatuses and methods for targeted refreshing of memory
Apparatuses and methods for targeted row refreshes are disclosed herein. In an example apparatus, a predecoder receives a target row address and determines...
US-9,324,391 Dual event command
A technique to increase transfer rate of command and address signals via a given number of command and address pins in each of one or more integrated circuit...
US-9,323,994 Multi-level hierarchical routing matrices for pattern-recognition processors
Multi-level hierarchical routing matrices for pattern-recognition processors are provided. One such routing matrix may include one or more programmable and/or...
US-9,323,608 Integrity of a data bus
A method for improving data bus integrity includes a selectable data bus integrity feature that can improve the integrity of a data bus in a memory system. An...
US-9,319,349 Encapsulation enabled PCIE virtualisation
There is herein described a method for transmitting data packets from a first device through a switch to a second device. The method is performed at an...
US-9,318,699 Resistive memory cell structures and methods
Resistive memory cell structures and methods are described herein. One or more memory cell structures comprise a first resistive memory cell comprising a first...
US-9,318,493 Memory arrays, semiconductor constructions, and methods of forming semiconductor constructions
Some embodiments include memory arrays. The memory arrays may have digit lines under vertically-oriented transistors, with the digit lines interconnecting...
US-9,318,438 Semiconductor structures comprising at least one through-substrate via filled with conductive materials
A method for selectively removing material from a substrate without damage to copper filling a via and extending at least partially through the substrate. The...
US-9,318,430 Stack of horizontally extending and vertically overlapping features, methods of forming circuitry components,...
A method of forming circuitry components includes forming a stack of horizontally extending and vertically overlapping features. The stack has a primary portion...
US-9,318,416 Semiconductor device including conductive layer with conductive plug
Some embodiments include a semiconductor device which includes a first conductive layer formed on the semiconductor substrate and a first contact plug connected...
US-9,318,394 Apparatus and methods for through substrate via test
A stack of vertically-connected, horizontally-oriented integrated circuits (ICs) may have electrical connections from the front side of one IC to the back side...
US-9,318,321 Methods of fabricating memory devices having charged species
Methods for fabricating memory devices having charged species. In one such method, a dielectric material is formed adjacent to a semiconductor. A charged...
US-9,318,220 Memory cell coupling compensation
Methods for memory cell coupling compensation and apparatuses configured to perform the same are described. One or more methods for memory cell coupling...
US-9,318,211 Apparatuses and methods including memory array data line selection
Some embodiments include an apparatus having data lines coupled to memory cell strings and a selector configured to selectively couple one of the data lines to...
US-9,318,205 Mapping between program states and data patterns
The present disclosure includes methods and apparatuses for mapping between program states and data patterns. One method includes: programming a group of G...
US-9,318,200 Methods and apparatuses including a string of memory cells having a first select transistor coupled to a second...
Generally discussed herein are apparatuses and methods. One such apparatus includes a data line, a first memory cell and a first select transistor. The first...
US-9,318,199 Partial page memory operations
Apparatuses may include a memory block with strings of memory cells formed in a plurality of tiers. The apparatus may further comprise access lines and data...
US-9,318,187 Method and apparatus for sensing in a memory
A method and a memory for sensing a state of a memory cell while the memory cell capacitor is isolated from a data line are described. An activation device of...
US-9,318,173 Apparatuses and methods for measuring an electrical characteristic of a model signal line and providing...
Apparatuses and methods for measuring an electrical characteristic of a model signal line and providing measurement information based at least in part on the...
US-9,318,157 Stacked device detection and identification
Various embodiments include apparatus and methods having circuitry to detect and/or assign identification information to dice arranged in a stack and coupled by...
US-9,317,459 Memory device distributed controller system
A memory device distributed controller circuit distributes memory control functions amongst a plurality of memory controllers. A master controller receives an...
US-9,317,450 Security protection for memory content of processor main memory
Subject matter disclosed herein relates to memory devices and security of same.
US-9,315,609 Thermal anneal of block copolymer films with top interface constrained to wet both blocks with equal preference
Methods for fabricating sub-lithographic, nanoscale microstructures utilizing self-assembling block copolymers, and films and devices formed from these methods...
US-9,313,902 Conductive structures for microfeature devices and methods for fabricating microfeature devices
Methods for fabricating conductive structures on and/or in interposing devices and microfeature devices that are formed using such methods are disclosed herein....
US-9,312,481 Memory arrays and methods of forming memory arrays
Some embodiments include memory arrays having a plurality of memory cells vertically between bitlines and wordlines. The memory cells contain phase change...
US-9,312,480 Memory cells
Some embodiments include a memory cell having a data storage region between a pair of conductive structures. The data storage region is configured to support a...
US-9,312,266 Memories with memory arrays extending in opposite directions from a semiconductor and their formation
Memories and their formation are disclosed. One such memory has a first array of first memory cells extending in a first direction from a first surface of a...
US-9,312,023 Devices and methods of programming memory cells
Devices and methods of programming memory cells, both SLC and MLC, such as to reduce charge-storage structure to charge-storage structure coupling, are shown...
US-9,312,022 Memory timing self-calibration
Methods for memory input timing self-calibration, apparatuses for input timing self-calibration, and systems are disclosed. One such method includes...
US-9,312,020 Methods of operating memory devices
Methods of operating a memory device include applying an increasing sense voltage to a plurality of memory cells, wherein memory cells of the plurality of...
US-9,312,007 Memory device and method having charge level assignments selected to minimize signal coupling
A non-volatile memory device programs memory cells in each row in a manner that minimizes the coupling of spurious signals. A control logic unit programs the...
US-9,312,005 Accessing memory cells in parallel in a cross-point array
Methods and structures for accessing memory cells in parallel in a cross-point array include accessing in parallel a first memory cell disposed between a first...
US-9,311,999 Memory sense amplifiers and memory verification methods
Memory sense amplifiers and memory verification methods are described. According to one aspect, a memory sense amplifier includes a first input coupled with a...
US-9,310,552 Methods and apparatus providing thermal isolation of photonic devices
Described embodiments include photonic integrated circuits and systems with photonic devices, including thermal isolation regions for the photonic devices....
US-9,306,600 Read threshold calibration for LDPC
Apparatuses and methods for soft read threshold location calibration are provided. One example method can include selecting read threshold sets (RTSs), and...
US-9,306,579 Output driver robust to data dependent noise
Techniques for controlling a driver to reduce data dependent noise, such as simultaneous switching effects and cross-talk effects. A plurality of drivers may...
US-9,306,518 Voltage regulators, amplifiers, memory devices and methods
Circuits, devices and methods are provided, such as an amplifier (e.g., a voltage regulator) that includes a feedback circuit that supplies negative feedback...
US-9,306,165 Replacement materials processes for forming cross point memory
Methods of forming memory cells comprising phase change and/or chalcogenide materials are disclosed. In one aspect, the method includes providing a lower line...
US-9,306,159 Phase change memory stack with treated sidewalls
Memory devices and methods for fabricating memory devices have been disclosed. One such method includes forming the memory stack out of a plurality of elements....
US-9,305,938 Methods of fabricating integrated structures, and methods of forming vertically-stacked memory cells
Some embodiments include a method of fabricating integrated structures. A metal-containing material is formed over a stack of alternating first and second...
US-9,305,929 Memory cells
A memory cell includes a select device and a capacitor electrically coupled in series with the select device. The capacitor includes two conductive capacitor...
US-9,305,905 Apparatuses and related methods for staggering power-up of a stack of semiconductor dies
An apparatus including semiconductor dies in a stack. The semiconductor dies are configured to power-up in a staggered manner. Methods for powering up an...
US-9,305,865 Devices, systems and methods for manufacturing through-substrate vias and front-side structures
Methods of manufacturing semiconductor devices and semiconductor devices with through-substrate vias (TSVs). One embodiment of a method of manufacturing a...
US-9,305,861 Method and system for electrically coupling a chip to chip package
A chip and a chip package can transmit information to each other by using a set of converters capable of communicating with each other through the emission and...
US-9,305,844 Method of making a semiconductor device
Some embodiments include a semiconductor device having a stack structure including a plurality of alternating tiers of dielectric material and poly-silicon...
US-9,305,826 Semiconductor substrate for photonic and electronic structures and method of manufacture
A method of forming a substrate with isolation areas suitable for integration of electronic and photonic devices is provided. A common reticle and...
US-9,305,782 Pitch reduction technology using alternating spacer depositions during the formation of a semiconductor device...
A method for patterning a layer increases the density of features formed over an initial patterning layer using a series of self-aligned spacers. A layer to be...
US-9,305,660 Page buffer connections and determining pass/fail condition of memories
Apparatus and methods for determining pass/fail condition of memories facilitate array efficiencies. In at least one embodiment, a set of common lines, one for...
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