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Semiconductor devices and methods for backside photo alignment
Various embodiments of microelectronic devices and methods of manufacturing are described herein. In one embodiment, a method for aligning an electronic feature...
Methods and apparatus for sensing a memory cell
Methods of operating a memory include selectively discharging a data line through a memory cell selected for sensing, discharging a sense node to the data line...
Dynamic data caches, decoders and decoding methods
Examples described include dynamic data caches (DDCs), decoders and decoding methods that may fit into a smaller width area. The DDCs, decoders and decoding...
Programming and/or erasing a memory device in response to its program
and/or erase history
For one embodiment, a programming method includes programming one or more memory cells of a memory device during a programming operation, determining, internal...
Methods and apparatuses including a variable termination impedance ratio
Methods of changing a centerline voltage of a data signal are described, along with apparatuses to change the centerline voltage. In one such method, portions...
Erasable block segmentation for memory
Various embodiments comprise apparatuses such as those having a block of memory divided into sub-blocks that share a common data line. Each of the sub-blocks of...
Apparatuses and methods including memory write operation
Some embodiments include apparatuses and methods having memory cells and access lines coupled to the memory cells. In one such apparatus, the access lines...
Optical interconnect in high-speed memory systems
A optical link for achieving electrical isolation between a controller and a memory device is disclosed. The optical link increases the noise immunity of...
Semiconductor device having a reduced footprint of wires connecting a DLL
circuit with an input/output buffer
An apparatus includes a clock terminal configured to receive an external clock signal, a clock generator configured to generate an internal clock signal in...
Apparatuses and methods for providing word line voltages during standby
Apparatuses and methods of providing word line voltages include an example apparatus including a voltage driver and a word line driver. The voltage driver is...
Methods for sensing memory elements in semiconductor devices
A memory device that, in certain embodiments, includes a plurality of memory elements connected to a bit-line and a delta-sigma modulator with a digital output...
Data protection across multiple memory blocks
Data protection across multiple memory blocks can include writing a first portion of a codeword in a first location of a first memory block and writing a second...
Unrolling quantifications to control in-degree and/or out-degree of
Apparatus, systems, and methods for a compiler are disclosed. One such compiler parses a human readable expression into a syntax tree and converts the syntax...
Methods of providing access to I/O devices
A method of providing one or more computing devices with access to a plurality of resources. The plurality of resources are provided by at least one physical...
External transmit modulator for an implantable neural stimulator
External transit modulator for implantable neural stimulator
Delay line off-state control with power reduction
A method and apparatus is provided for controlling a delay line for achieving power reduction. The device comprises a delay lock loop to provide an output...
Apparatuses and methods for input buffer having combined output
Apparatuses and methods are disclosed, including an apparatus that includes a first differential amplifier to amplify a difference between an input signal and a...
Semiconductor device and method for adjusting impedance of output circuit
An impedance adjustment circuit includes a counter circuit outputting a count value thereof as a plurality of first impedance adjustment signals, a mode...
Solid-state light emitters having substrates with thermal and electrical
conductivity enhancements and method...
Solid-state lighting devices (SSLDs) including a carrier substrate with conductors and methods of manufacturing SSLDs. The conductors can provide (a) improved...
Vertical solid-state transducers and high voltage solid-state transducers
having buried contacts and associated...
Solid-state transducers ("SSTs") and vertical high voltage SSTs having buried contacts are disclosed herein. An SST die in accordance with a particular...
Self-identifying solid-state transducer modules and associated systems and
Self-identifying solid-state transducer (SST) modules and associated systems and methods are disclosed herein. In several embodiments, for example, an SST...
Conductive interconnect structures and formation methods using
Conductive interconnect structures and formation methods using supercritical fluids are disclosed. A method in accordance with one embodiment of the invention...
Patterned bases, and patterning methods
Some embodiments include methods of patterning a base. First and second masking features are formed over the base. The first and second masking features include...
Semiconductor device structures comprising a polymer bonded to a base
material and methods of fabrication
Methods for adhering materials and methods for enhancing adhesion between materials are disclosed. In some embodiments, a polymer brush material is bonded to a...
Removal of metal
Methods of removing metal from a portion of a substrate are useful in integrated circuit fabrication. Methods include exposing the substrate to an oxidizing...
Determining and using soft data in memory devices and systems
The present disclosure includes methods, devices, and systems for determining and using soft data in memory devices and systems. One or more embodiments include...
Sensing data stored in memory
The present disclosure includes apparatuses and methods for sensing data stored in memory. A number of embodiments include an array of memory cells, and a...
Memory cells, memory systems, and memory programming methods
Memory cells, memory systems and methods are described. In one embodiment, a memory cell includes electrodes and a memory element, and a first electrically...
Apparatuses and methods for multi-memory array accesses
Methods and apparatuses are disclosed for multi-memory array access. One example apparatus includes a pair of input/output lines, and a first array coupled to...
Apparatus including a capacitor-less memory cell and related methods
A capacitor-less memory cell, memory device, system and process of forming the capacitor-less memory cell include forming the capacitor-less memory cell in an...
Methods, and apparatus configured to perform such methods, providing peak power management are useful in mitigating excessive current levels within a multi-die...
Configurable bandwidth memory devices and methods
Memory devices and methods are described, such as those that include a stack of memory dies and an attached logic die. Method and devices described provide for...
Multilevel encoding with error correction
Embodiments of the present disclosure provide methods, systems, and apparatuses related to multilevel encoding with error correction. In some embodiments, a...
Codewords that span pages of memory
The present disclosure includes apparatuses and methods for codewords that span pages of memory. A number of methods include writing a first portion of a...
Methods for forming resist features and arrays of aligned, elongate resist
Methods of forming resist features, resist patterns, and arrays of aligned, elongate resist features are disclosed. The methods include addition of a compound,...
Methods and apparatus for sorting and/or depositing nanotubes
Methods and apparatus for forming devices using nanotubes. In one embodiment, an apparatus for depositing nanotubes onto a workpiece comprises a vessel...
Flexible input/output transceiver
An I/O transceiver includes a driver with a feedback circuit having a mode select signal input, a serial data signal input, and a driver output signal input....
Resistance variable memory cell structures and methods
Resistance variable memory cell structures and methods are described herein. One or more resistance variable memory cell structures include a first electrode...
Memory cells and methods of forming memory cells
Some embodiments include a memory cell having an electrode and a switching material over the electrode. The electrode is a first composition which includes a...
Solid state lighting devices with dielectric insulation and methods of
Solid state lighting devices and associated methods of manufacturing are disclosed herein. In one embodiment, a solid state lighting device includes a first...
Some embodiments include a memory array which has a stack of alternating first and second levels. Channel material pillars extend through the stack, and...
Semiconductor field-effect transistor, memory cell and memory device
Semiconductor device formed by a first conductive strip of semiconductor material; a control gate region of semiconductor material, facing a channel portion of...
Some embodiments include methods of forming flash memory cells and semiconductor constructions, and some embodiments include semiconductor constructions. Some...
Vertical transistor devices, memory arrays, and methods of forming
vertical transistor devices
A vertical transistor device includes a line of active area adjacent a line of dielectric isolation. A buried data/sense line obliquely angles relative to the...
Transistors having one or more dummy lines with different collective
widths coupled thereto
In an embodiment, an array of transistors has a first line coupled to a first transistor. The first line extends over a second transistor that is successively...
Stacked semiconductor die assemblies with thermal spacers and associated
systems and methods
Stacked semiconductor die assemblies with thermal spacers and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die...
Methods for forming conductive vias in semiconductor device components
A method for forming conductive vias in a substrate of a semiconductor device component includes forming one or more holes, or apertures or cavities, in the...
Apparatuses and methods for die seal crack detection
Apparatuses and methods can include a die seal between an integrated circuit region of a die and a periphery of the die. A via chain(s) may be arranged around...
A semiconductor device including: a resistive memory element; a data line electrically coupled to the resistive memory element; a control line; a power supply...