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Chemically sensitive warning apparatus and method
A chemically sensitive warning apparatus capable of changing colors upon contact with a chemical is disclosed. The apparatus preferably comprises an elongated...
Column address path circuit and method for memory devices having a burst
Column addresses are generated by a burst controller that includes respective latches for the three low-order bits of a column address. The two higher order bits...
Single segment data object management
A single segment data structure and method for storing data objects employing a single segment data object having a header and a data record. The header includes...
Public key cryptography using matrices
The invention provides techniques for secure messages transmission using a public key system to exchange secret keys. A first entity creates public and private...
Memory system and method using ECC to achieve low power refresh
Rows of DRAM memory cells are refreshed at either a relatively high rate during normal operation or a relatively slow rate in a reduced power refresh mode. Prior...
Alignment of memory read data and clocking
Circuits and methods are provided for aligning data read from a memory with an output clock signal when the memory is operated at very high clock frequencies. To...
System and method for enhanced mode register definitions
Apparatus and methods for increasing a number of selectable options for an operating mode. A number of selectable options for an operating mode is increased by...
NROM flash memory with self-aligned structural charge separation
A nitride read only memory (NROM) cell has a nitride layer that is not located under the center of the transistor. The gate insulator layer, with the nitride...
One transistor SOI non-volatile random access memory cell
One aspect of the present subject matter relates to a memory cell, or more specifically, to a one-transistor SOI non-volatile memory cell. In various...
High speed data bus
The invention comprises data processing systems and components thereof. Such systems may include a memory controller, a plurality of memory devices, a data bus...
Closed-loop high voltage booster
A voltage boosting circuit with a closed-loop control mechanism and a controllable slew rate. A tracking capacitor and a control current form the closed-loop and...
Pattern generator diffractive mirror methods and systems
The present invention relates to an apparatus for creating a pattern on a workpiece sensitive to radiation, such as a photomask a display panel or a microoptical...
Method and system for detecting a mode of operation of an integrated
circuit, and a memory device including same
A threshold detection circuit for developing a mode trigger signal includes an input that receives an input signal. In response to the input signal having...
System and method for testing devices utilizing capacitively coupled
An apparatus and method for testing a semiconductor device in an AC test regime. The test apparatus includes a test plate capacitively couple to the signal...
MRAM memory cell having an electroplated bottom layer
The present invention provides a method of forming an MRAM cell which minimizes the occurrence of electrical shorts during fabrication. A first conductor in a...
SRAM constructions, and electronic systems comprising SRAM constructions
The invention includes SRAM constructions comprising at least one transistor device having an active region extending into a crystalline layer comprising Si/Ge....
Amplification with feedback capacitance for photodetector signals
Signals from an imager pixel photodetector are received by an amplifier having capacitive feedback, such as a capacitive transimpedance amplifier (CTIA). The...
Microelectronic component assemblies having lead frames adapted to reduce
The present disclosure suggests various microelectronic component assembly designs and methods for manufacturing microelectronic component assemblies. In one...
Plasma etching methods
A plasma etching method includes forming a polymer comprising carbon and a halogen over at least some internal surfaces of a plasma etch chamber. After forming...
Methods for treating pluralities of discrete semiconductor substrates
The invention includes a method for treating a plurality of discrete semiconductor substrates. The discrete semiconductor substrates are placed within a reactor...
Method of forming socket contacts
In a socket used to house semiconductor die during testing, a recessed socket contact and methods of making the same are provided that avoid pinching the die's...
Method for fabricating a chip scale package using wafer level processing
Channels are formed that pass through an active surface of a semiconductor substrate to provide isolation between adjacent active surface regions defining...
Methods of forming transistor gates; and methods of forming programmable
read-only memory constructions
The invention includes a method of forming a transistor gate. One or more conductive materials are formed over a semiconductor substrate, and a block is formed...
Methods of reducing floating body effect
Methods of reducing the floating body effect in vertical transistors are disclosed. The floating body effect occurs when an active region in a pillar is cut off...
Method and apparatus for decoupling conductive portions of a
microelectronic device package
A method and apparatus for decoupling conductive portions of a microelectronic device package. In one embodiment, the package can include a microelectronic...
Ultrathin leadframe BGA circuit package
A circuit package is formed using a leadframe. The leadframe is formed or etched to align a plurality of bond pad structures above a reference plane while...
Microelectronic devices with improved heat dissipation and methods for
cooling microelectronic devices
Microelectronic devices with improved heat dissipation, methods of making microelectronic devices, and methods of cooling microelectronic devices are disclosed...
High efficiency method for performing a chemical vapordeposition utilizing
a nonvolatile precursor
A method directed to the use of a nonvolatile precursor, either a solid or liquid precursor, suitable for CVD, including liquid source CVD (LSCVD). Using the...
Methods and systems for planarizing workpieces, e.g., microelectronic
Planarizing workpieces, e.g., microelectronic workpieces, can employ a process indicator that is adapted to change an optical property in response to a...
Methods for analyzing and controlling performance parameters in mechanical
Methods and apparatuses for analyzing and controlling performance parameters in planarization of microelectronic substrates. In one embodiment, a planarizing...
Multi-functional solder and articles made therewith, such as
Aspects of the invention provide solder compositions which include two different fluxing agents. One of the fluxing agents promotes melting of a metal of the...
Plating buss and a method of use thereof
The present invention relates generally to a plating buss design and method for minimizing short circuit problems in PCB panel singulation. More particularly,...
Active memory command engine and method
A command engine for an active memory receives high level tasks from a host and generates corresponding sets of either DCU commands to a DRAM control unit or ACU...
Dynamic command and/or address mirroring system and method for memory
A memory module includes a memory hub that couples signals to memory devices mounted on opposite first and second surfaces of a memory module substrate. The...
Scratch control memory array in a flash memory device
A memory device has a scratch control array of non-volatile memory cells that is separate from the primary array of memory cells. The scratch control array...
Data compression read mode for memory testing
Memory devices having a normal mode of operation and a test mode of operation are useful in quality programs. The test mode of operation includes a data...
Method of stress-testing an isolation gate in a dynamic random access
The present invention includes a DRAM array. The DRAM array includes a first memory cell, a second memory cell and an isolation gate formed between the first and...
Reduced power registered memory module and method
A registered memory module includes a plurality of flip-flops having respective data terminals, respective clock terminals receiving a clock signal and output...
Flash with consistent latency for read operations
A synchronous flash memory includes an array of non-volatile memory cells. The memory device has a package configuration that is compatible with an SDRAM. The...
Memory block erasing in a flash memory device
An erase pulse is applied to the memory block to be erased. An erase verification operation is performed to verify that each memory cell of the memory block is...
Semiconductor processors, sensors, semiconductor processing systems,
semiconductor workpiece processing...
Semiconductor processors, sensors, semiconductor processing systems, semiconductor workpiece processing methods, and turbidity monitoring methods are provided....
Apparatus and method for distributed memory control in a graphics
A distributed memory controller memory system for a graphics processing system having addressable memory areas each coupled to a respective memory controller....
Variable resistance circuit
A method of finding an unknown value from within a range of values is disclosed that divides the range into weighted subranges and then, beginning with an...
CMOS amplifiers with frequency compensating capacitors
The frequency and transient responses of a CMOS differential amplifier are improved by employing one or more compensating capacitors. A compensating capacitor...
Abberation mark and method for estimating overlay error and optical
An aberration mark for use in an optical photolithography system, and a method for estimating overlay errors and optical aberrations. The aberration mark...
Tape substrate and method for fabricating the same
A tape substrate including an insulating film, a copper foil pattern formed on the insulating film at one side of the insulating film, and provided with a...
Semiconductor damascene trench and methods thereof
A memory device cell layout, a computer system comprising a memory device having a particular cell layout, and methods of fabricating static memory cells and...
Methods of forming integrated circuit devices
Forming an integrated circuit device includes forming a hard mask layer overlying a semiconductor substrate. The hard mask layer is patterned to expose portions...
Method of forming a metal-containing layer over selected regions of a
The invention includes methods of electrochemically treating semiconductor substrates. The invention includes a method of electroplating a substance. A substrate...
Permeable capacitor electrode
The present teachings describe a container capacitor that utilizes an etchant permeable lower electrode for the formation of single or double-sided capacitors...