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Patent # Description
US-7,191,409 Method and apparatus for programming hot keys based on user interests
A system is provided that configures a computer keyboard hot key based upon user interests. The system determines a profile of interests for a user, selects a...
US-7,191,345 BIOS lock encode/decode driver
Systems and methods for preventing the unauthorized access to data stored on removable media, such as software, include storing a predetermined signature in the...
US-7,190,736 Technique to simultaneously distribute clock signals and data on integrated circuits, interposers, and circuit...
A technique is described for simultaneously and synchronously transmitting digital data and a clock signal in a digital integrated circuit, circuit board, or...
US-7,190,629 Circuit and method for reading an antifuse
An antifuse circuit and antifuse reading method for determining whether an antifuse is programmed or un-programmed. An antifuse circuit includes a sensing...
US-7,190,625 Method and apparatus for data compression in memory devices
A test circuit for a memory device having a pair of arrays each of which includes a plurality of memory cells arranged in rows and columns. A pair of...
US-7,190,622 Method and architecture to calibrate read operations in synchronous flash memory
Architecture to calibrate read operations in non-volatile memory devices. In one embodiment, a synchronous flash memory is disclosed. The synchronous flash...
US-7,190,616 In-service reconfigurable DRAM and flash memory device
A memory cell that has both a DRAM cell and a non-volatile memory cell. The non-volatile memory cell might include a flash memory or an NROM cell. The memory...
US-7,190,610 Latch-up prevention for memory cells
An SRAM memory cell is provided having a pair of cross-coupled CMOS inverters. The sources of the pull-up transistors forming each of the CMOS inverters are...
US-7,190,608 Sensing of resistance variable memory devices
A resistance variable memory device such as e.g., a PCRAM memory device, with either a 4T (transistor) or 2T memory cell configuration and either a dual cell...
US-7,190,397 CMOS imager decoder structure
A decoder apparatus for selecting column lines of a CMOS imager pixel array is disclosed. The decoder apparatus is made up of at least one first decoder and at...
US-7,190,394 Method for statistical analysis of images for automatic white balance of color channel gains for image sensors
A process for performing white balancing of an image is performed by subdividing an image into a plurality of subframes, and then analyzing each subframe to...
US-7,190,081 Mold gates and tape substrates including the mold gates
A mold gate of a tape substrate includes an aperture formed in the flexible dielectric film of the tape substrate and a support element which is carried by a...
US-7,190,074 Reconstructed semiconductor wafers including alignment droplets contacting alignment vias
Apparatus, systems and methods relating to the reconstruction of semiconductor wafers for wafer-level processing are disclosed. Selected semiconductor dice...
US-7,190,052 Semiconductor devices with oxide coatings selectively positioned over exposed features including semiconductor...
A semiconductor device structure includes a passivation layer through which only non-silicon-comprising structures are exposed. The semiconductor device...
US-7,190,048 Resistance variable memory device and method of fabrication
Methods and apparatus for providing a resistance variable memory device with agglomeration prevention and thermal stability. According to one embodiment, a...
US-7,190,043 Techniques to create low K ILD for beol
One aspect of the present subject matter relates to a method for forming an interlayer dielectric (ILD). In various embodiments of the method, an insulator layer...
US-7,190,041 Well for CMOS imager
A well region of a first conductivity type located in a substrate of the first conductivity type and below about half the channel length of an electrically...
US-7,190,039 Microelectronic imagers with shaped image sensors and methods for manufacturing microelectronic imagers
Microelectronic imagers with shaped image sensors and methods for manufacturing curved image sensors. In one embodiment, a microelectronic imager device...
US-7,190,028 Semiconductor-on-insulator constructions
The invention includes semiconductor constructions having a thin film stacked resistor in electrical connection with a source/drain region of a transistor...
US-7,190,020 Non-planar flash memory having shielding between floating gates
A first plurality of memory cells is formed on pillars in a first column of the array. A second plurality of memory cells is formed in a first set of trenches in...
US-7,189,954 Microelectronic imagers with optical devices and methods of manufacturing such microelectronic imagers
Microelectronic imager assemblies comprising a workpiece including a substrate and a plurality of imaging dies on and/or in the substrate. The substrate includes...
US-7,189,662 Methods of forming semiconductor constructions
The invention includes methods of forming and/or passivating semiconductor constructions. In particular aspects, various oxides of a semiconductor substrate can...
US-7,189,642 Methods of fabricating interconnects including depositing a first material in the interconnect with a thickness...
In one aspect, the invention encompasses a method of fabricating an interconnect for a semiconductor component. A semiconductor substrate is provided, and an...
US-7,189,634 Edge intensive antifuse
An antifuse including a bottom plate having a plurality of longitudinal members arranged substantially parallel to a first axis, a dielectric layer formed on the...
US-7,189,626 Electroless plating of metal caps for chalcogenide-based memory devices
A method of forming a metal cap over a conductive interconnect in a chalcogenide-based memory device is provided and includes, forming a layer of a first...
US-7,189,623 Semiconductor processing method and field effect transistor
A method of forming a transistor gate includes forming a gate oxide layer over a semiconductive substrate. Chlorine is provided within the gate oxide layer. A...
US-7,189,611 Metal plating using seed film
A seed film and methods incorporating the seed film in semiconductor applications is provided. The seed film includes one or more noble metal layers, where each...
US-7,189,607 Formation of standard voltage threshold and low voltage threshold MOSFET devices
Wells are formed in a substrate where standard Vt and low Vt devices of both a first and second type are to be fabricated. Wells defining the locations of first...
US-7,189,606 Method of forming fully-depleted (FD) SOI MOSFET access transistor
A fully-depleted (FD) Silicon-on-Insulator (SOI) MOSFET access transistor comprising a gate electrode of a conductivity type which is opposite the conductivity...
US-7,189,602 Method and apparatus for reducing substrate bias voltage drop
A semiconductor device is provided with a conductive layer provided on a backside of a semiconductor substrate. The conductive layer helps maintain a uniform...
US-7,189,600 Methods for fabricating stiffeners for flexible substrates
Methods for fabricating stiffeners for flexible substrates, including, but not limited to, tapes, films, or other connective structures, which are configured to...
US-7,189,593 Elimination of RDL using tape base flip chip on flex for die stacking
A flexible film interposer for stacking a flip chip semiconductor die onto a second (bottom) semiconductor die, semiconductor devices and stacked die assemblies...
US-7,189,583 Method for production of MRAM elements
Magneto-resistive random access memory elements include a ferromagnetic layer having uniaxial anisotropy provided by elongate structures formed in the...
US-7,189,333 End effectors and methods for manufacturing end effectors with contact elements to condition polishing pads...
End effectors, apparatuses including end effectors for conditioning planarizing pads, and methods for manufacturing end effectors with contact elements to...
US-7,189,317 Semiconductor manufacturing system for forming metallization layer
A method for forming a metallization layer. A first layer is formed outwardly from a semiconductor substrate. Contact vias are formed through the first layer to...
US-7,189,305 Gas-assist systems for applying and moving ozonated resist stripper to resist-bearing surfaces of substrates
A method for moving resist stripper across the surface of a semiconductor substrate that includes applying a wet chemical resist stripper, such as an organic or...
US-7,189,287 Atomic layer deposition using electron bombardment
Formation of a layer of material on a surface by atomic layer deposition methods and systems includes using electron bombardment of the chemisorbed precursor.
US-7,189,153 Retaining rings, planarizing apparatuses including retaining rings, and methods for planarizing micro-device...
Retaining rings, planarizing apparatuses including retaining rings, and methods for mechanical and/or chemical-mechanical planarization of micro-device...
US-7,188,219 Buffer control system and method for a memory system having outstanding read and write request buffers
A memory controller and method for managing the issuance of read and write requests to a system memory is provided. The number of outstanding read requests and...
US-7,188,217 Embedded DRAM cache memory and method having reduced latency
A computer system includes a processor, a system memory, and an integrated circuit system controller coupled to the processor and the system memory. The system...
US-7,188,036 Internal bias measure with onboard ADC for electronic devices
An apparatus and method for on-chip bias measurement of an analog signals on an integrated circuit with a switchable analog-to-digital converter capable of...
US-7,187,617 Memory system and method for strobing data, command and address signals
A memory system couples command, address or write data signals from a memory controller to a memory device and read data signals from the memory device to the...
US-7,187,601 Active termination circuit and method for controlling the impedance of external integrated circuit terminals
An active termination circuit is used to set the input impedance of a plurality of input terminals. Each of the input terminals is coupled to a supply voltage...
US-7,187,587 Programmable memory address and decode circuits with low tunnel barrier interpoly insulators
Structures and methods for programmable memory address and decode circuits with low tunnel barrier interpoly insulators are provided. The decoder for a memory...
US-7,187,574 High speed data bus
The invention comprises data processing systems and components thereof. Such systems may include a memory controller, a plurality of memory devices, a data bus...
US-7,187,219 Power-on-reset circuit based on the threshold levels and quadratic I-V behavior of MOS transistors
A system and method for providing a clock-independent reset signal based on supply voltage threshold levels is described. The trip points or predefined voltage...
US-7,187,190 Contact pad arrangement on a die
An integrated device includes a redundant bond pad for accessing internal circuitry in the event that the main bond pad for that circuitry is difficult to access...
US-7,187,049 Data download to imager chip using image sensor as a receptor
An imaging device having a CMOS photosensor array for capturing images is described in which the array is also used to input programming and/or data used to...
US-7,187,047 Method and structure for reducing resistance of a semiconductor device feature
A method used to form a semiconductor device comprises forming a polysilicon layer, forming a conductive barrier layer on the polysilicon layer, then forming a...
US-7,187,018 Reduced barrier photodiode/transfer gate device structure of high efficiency charge transfer and reduced lag...
A pixel cell having a reduced potential barrier near a region where a gate and a photodiode are in close proximity to one another, and a method for forming the...
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