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Patent # Description
US-7,214,978 Semiconductor fabrication that includes surface tension control
In one embodiment, a method includes providing a semiconductor substrate that includes a memory container having a double-sided capacitor. The method also...
US-7,214,962 Apparatus and methods of testing and assembling bumped devices using an anisotropically conductive layer
The present invention is directed toward apparatus and methods of testing and assembling bumped die and bumped devices using an anisotropically conductive layer....
US-7,214,926 Imaging systems and methods
Imaging systems and methods are provided. One exemplary system incorporates multiple lenses that are individually configured to receive multi-wavelength light...
US-7,214,920 Pixel with spatially varying metal route positions
An image sensor including an array of pixels having an optical center, the array including a first pixel substantially at a first distance from the optical...
US-7,214,919 Microelectronic imaging units and methods of manufacturing microelectronic imaging units
Microelectronic imaging units and methods for manufacturing the microelectronic imaging units. In one embodiment, an imaging unit includes a support member, an...
US-7,214,621 Methods of forming devices associated with semiconductor constructions
The invention includes methods of forming devices associated with semiconductor constructions. In exemplary methods, common processing steps are utilized to form...
US-7,214,618 Technique for high efficiency metalorganic chemical vapor deposition
A technique for more efficiently forming conductive elements, such as conductive layers and electrodes, using chemical vapor deposition. A conductive precursor...
US-7,214,616 Homojunction semiconductor devices with low barrier tunnel oxide contacts
A homojunction bipolar transistor with performance characteristics similar to more costly heterojunction or retrograde base transistors. The high emitter...
US-7,214,614 System for controlling metal formation processes using ion implantation
The present invention is generally directed to various methods of using ion implantation techniques to control various metal formation processes. In one...
US-7,214,613 Cross diffusion barrier layer in polysilicon
A semiconductor device includes a cross diffusion barrier layer sandwiched between a gate layer and an electrode layer. The gate layer has a first gate portion...
US-7,214,602 Method of forming a conductive structure
A method of forming a conductive structure is disclosed. The method includes forming an interconnect in a substrate, and forming a layer of iridium on the...
US-7,214,575 Method and apparatus providing CMOS imager device pixel with transistor having lower threshold voltage than...
A transistor of a pixel cell for use in a CMOS imager with a low threshold voltage of about 0.3 V to less than about 0.7 V is disclosed. The transistor is...
US-7,214,566 Semiconductor device package and method
A method of making semiconductor device packages includes the steps of attaching a wafer to a dielectric layer, testing semiconductor devices in the wafer, and...
US-7,214,547 Methods of forming semiconductor constructions
The invention includes a method of forming a semiconductor construction, such as an MRAM construction. A block is formed over a semiconductor substrate. First...
US-7,214,125 Method for controlling pH during planarization and cleaning of microelectronic substrates
A method and apparatus for processing a microelectronic substrate. In one embodiment, the method can include planarizing the microelectronic substrate with a...
US-7,213,447 Method and apparatus for detecting topographical features of microelectronic substrates
An apparatus and method for detecting characteristics of a microelectronic substrate. The microelectronic substrate can have a first surface with first...
US-7,213,331 Method for forming stencil
A method of forming a stencil for the manufacture of semiconductor devices includes defining a plurality of slightly spaced segmental annular openings in a...
US-7,213,330 Method of fabricating an electronic device
A plurality of electrical interconnections may be formed in an electrical device including a first component having a plurality of contact pads and a second...
US-7,213,188 Accessing test modes using command sequences
An integrated circuit device receives a sequence of commands and enables a test mode of the integrated circuit device in response to the command sequence when...
US-7,213,082 Memory hub and method for providing memory sequencing hints
A memory module includes a memory hub coupled to several memory devices. The memory hub is also coupled to receive a memory packet from a system controller...
US-7,212,460 Line amplifier to supplement line driver in an integrated circuit
A method and circuitry for boosting a driven signal along a circuit line so as to reduce RC delays is disclosed. In one embodiment, the circuitry includes a line...
US-7,212,456 Apparatus for dynamically repairing a semiconductor memory
An architecture for dynamically repairing a semiconductor memory, such as a Dynamic Random Access Memory (DRAM), includes circuitry for dynamically storing...
US-7,212,447 NAND flash memory cell programming
A flash memory device, such as a NAND flash, having an array of floating gate transistor memory cells arranged in a first and second addressable blocks. A...
US-7,212,436 Multiple level programming in a non-volatile memory device
The programming method of the present invention minimizes program disturb in a non-volatile memory device by initially programming a lower page of a memory...
US-7,212,435 Minimizing adjacent wordline disturb in a memory device
A selected wordline that is coupled to cells for programming is biased with a programming voltage. The unselected wordlines that are adjacent to the selected...
US-7,212,394 Apparatus and method for banding the interior substrate of a tubular device and the products formed therefrom
Apparatus and method for depositing a banding material on the interior substrate of a tubular device, and the products formed therefrom. The tubular device is,...
US-7,212,057 Measure-controlled circuit with frequency control
A delay locked circuit has multiple paths for receiving an external signal. One path measures a timing of the external signal during a measurement. Another path...
US-7,212,053 Measure-initialized delay locked loop with live measurement
A method of operating a delay locked loop is comprised of producing a first output signal in response to a first lock point. A new lock point is measured, or...
US-7,212,020 Device and method for isolating a short-circuited integrated circuit (IC) from other ICs on a semiconductor wafer
A circuit for isolating a short-circuited integrated circuit (IC) formed on the surface of a semiconductor wafer from other ICs formed on the wafer that are...
US-7,212,013 Apparatus for measuring parasitic capacitance and inductance of I/O leads on an electrical component using a...
Apparatus and methods are provided for measuring the potential for mutual coupling in an integrated circuit package of any type or configuration using a network...
US-7,211,997 Planarity diagnostic system, E.G., for microelectronic component test systems
Methods of verifying planarity of a microelectronic component support of a microelectronic component test system with respect to a head of the test system are...
US-7,211,855 Intermediate semiconductor device structure including multiple photoresist layers
The present invention prevents cross-linking between multiple resists that are used in the fabrication of a semiconductor device. In order to prevent resists in...
US-7,211,849 Protective layers for MRAM devices
A method of forming a magnetic random access memory (MRAM) using a sacrificial cap layer on top of the memory cells and the structure resulting therefrom are...
US-7,211,848 Masked spacer etching for imagers
The invention relates to a dual masked spacer etch for improved dark current performance in imagers. After deposition of spacer material such as oxide, N-channel...
US-7,211,512 Selective electroless-plated copper metallization
Structures and methods are provided which include a selective electroless copper metallization. The present invention includes a novel methodology for forming...
US-7,211,499 Methods of forming silicon dioxide layers, and methods of forming trench isolation regions
A method of forming a silicon dioxide layer includes forming a high density plasma proximate a substrate, the plasma comprising silicon dioxide precursors;...
US-7,211,492 Self aligned metal gates on high-k dielectrics
A method for forming a transistor including a self aligned metal gate is provided. According to various method embodiments, a high-k gate dielectric is formed on...
US-7,211,479 Silicon rich barrier layers for integrated circuit devices
Semiconductor devices and memory cells are formed using silicon rich barrier layers to prevent diffusion of dopants from differently doped polysilicon films to...
US-7,211,453 Method and apparatus for personalization of semiconductor
A system for making small modifications to the pattern in standard processed semiconductor devices. The modifications are made to create a small variable part of...
US-7,211,200 Manufacture and cleaning of a semiconductor
Metal nitride and metal oxynitride extrusions often form on metal silicides. These extrusions can cause short circuits and degrade processing yields. The present...
US-7,210,989 Planarizing machines and methods for dispensing planarizing solutions in the processing of microelectronic...
Machines with solution dispensers and methods of using such machines for chemical-mechanical planarization and/or electrochemical-mechanical ...
US-7,210,985 Shaped polishing pads for beveling microfeature workpiece edges, and associated systems and methods
Systems and methods for beveling microfeature workpiece edges are disclosed. A system in accordance with one embodiment is configured to remove material from a...
US-7,210,984 Shaped polishing pads for beveling microfeature workpiece edges, and associated systems and methods
Systems and methods for beveling microfeature workpiece edges are disclosed. A system in accordance with one embodiment is configured to remove material from a...
US-7,210,581 Apparatus for magnetically separating integrated circuit devices
A method and apparatus of separating integrated circuit (IC) devices according to magnetic properties of the devices is disclosed. A plurality of IC devices are...
US-7,210,224 Method for forming an antifuse
An antifuse including a bottom plate having a plurality of longitudinal members arranged substantially parallel to a first axis, a dielectric layer formed on the...
US-7,210,110 Method for determining a matched routing arrangement for semiconductor devices
The present invention relates to a method for determining a matched routing netlist for a semiconductor device. In a particular embodiment, a topological plan...
US-7,210,059 System and method for on-board diagnostics of memory modules
A memory hub includes an on-board diagnostic engine through which diagnostic testing and evaluation of the memory system can be performed. The memory hub...
US-7,210,020 Continuous interleave burst access
A system is described which uses a burst access memory and a memory controller to anticipate the memory address to be used in future data read operations as...
US-7,209,794 Controller with interface attachment
A controller with attachments for controlling specific electronic circuits is disclosed. Each attachment has a connector connectable to the electronic circuit to...
US-7,209,405 Memory device and method having multiple internal data buses and memory bank interleaving
A memory device and method receives write data through a unidirectional downstream bus and outputs read data through a unidirectional upstream bus. The...
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