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Patent # Description
US-7,247,987 Rear plate for plasma display panel
Disclosed is a rear plate of a plasma display panel. In the rear plate, a dielectric layer or a barrier wall layer is formed by forming slurry in a tape of a...
US-7,247,944 Connector assembly
An apparatus and method for attaching a semiconductor die to a lead frame wherein the electric contact points of the semiconductor die are relocated to the...
US-7,247,927 Leadframe alteration to direct compound flow into package
A leadframe comprising a downset formed adjacent to an edge of the leadframe so as to direct the molding compound to flow evenly inside the mold cavity. The...
US-7,247,920 Method of composite gate formation
Methods for forming a nitride barrier film layer in semiconductor devices such as gate structures, and barrier layers, semiconductor devices and gate electrodes...
US-7,247,919 Method and device to reduce gate-induced drain leakage (GIDL) current in thin gate oxides MOSFETs
An integrated circuit which provides a FET device having reduced GIDL current is described. A semiconductor substrate is provided wherein active regions are...
US-7,247,836 Method and system for determining motion based on difference image correlation
An imager captures successive images of an object. One image is then subtracted from another image to generate difference images. Each difference image is then...
US-7,247,831 Reduction in size of column sample and hold circuitry in a CMOS imager
Improved column sample-and-hold (CSH) circuitry particularly useful in a CMOS imager is disclosed. In the improved circuitry layout, the overall column height of...
US-7,247,584 System and method for selectively increasing surface temperature of an object
A system and method for selectively increasing the thermal effect of a radiant energy source to the surface of an object relative to the substrate is described...
US-7,247,581 Methods for treating pluralities of discrete semiconductor substrates
The invention includes a method for treating a plurality of discrete semiconductor substrates. The discrete semiconductor substrates are placed within a reactor...
US-7,247,570 Silicon pillars for vertical transistors
In order to form a more stable silicon pillar which can be used for the formation of vertical transistors in DRAM cells, a multi-step masking process is used. In...
US-7,247,561 Method of removing residual contaminants from an environment
A method of reducing the amount of halogenated materials in a halogen-containing environment. The method comprises introducing an aluminum compound into the...
US-7,247,521 Semiconductor assembly encapsulation mold and method for forming same
An encapsulation mold for forming an encapsulation layer over a semiconductor assembly is disclosed. A semiconductor assembly with multiple semiconductor dies...
US-7,247,520 Microelectronic component assemblies and microelectronic component lead frame structures
The present invention provides microelectronic component assemblies and lead frame structures that may be useful in such assemblies. For example, one such lead...
US-7,247,492 Method for observing chemical substances
An apparatus and method for observing a chemical substance. In one embodiment, the apparatus includes a vessel having a base portion and an at least partially...
US-7,247,227 Buffer layer in flat panel display
In devices such as flat panel displays, an aluminum oxide layer is provided between an aluminum layer and an ITO layer when such materials would otherwise be in...
US-D547,305 Speaker for vehicle
US-7,245,785 Suppression of ringing artifacts during image resizing
An economical method of detecting and suppressing ringing artifacts during digital image resizing is presented. The economical method substitutes costly division...
US-7,245,553 Memory system and method for strobing data, command and address signals
A memory system couples command, address or write data signals from a memory controller to a memory device and read data signals from the memory device to the...
US-7,245,551 Read command triggered synchronization circuitry
A memory READ command triggered clock synchronization mode turns on a clock synchronization circuit only for memory READ operations. The clock synchronization...
US-7,245,550 Memory array decoder
An apparatus and method for selecting a storage location in a memory device including receiving at least one of a pre-decoded location address signal, a match...
US-7,245,548 Techniques for reducing leakage current in memory devices
Techniques for reducing gate induced drain leakage (GIDL) in memory devices utilizing negative wordline architectures. More specifically, a method and apparatus...
US-7,245,541 Active termination control
A method and apparatus are provided for active termination control in a memory by an module register providing an active termination control signal to the...
US-7,245,540 Controller for delay locked loop circuits
A method of controlling a delay locked loop (DLL) in a memory device is provided. The DLL generates an internal clock signal based on an external clock signal....
US-7,245,538 High voltage generation and regulation circuit in a memory device
An auxiliary voltage generation circuit is part of a high voltage generation and regulation circuit. The auxiliary voltage generation circuit generates an...
US-7,245,321 Readout circuit with gain and analog-to-digital conversion for image sensor
A CMOS imager includes an array of active pixel sensors, wherein each pixel is associated with a respective column in the array. The imager also includes...
US-7,245,320 Method and apparatus for automatic gain and exposure control for maintaining target image brightness in video...
In an image processing system, the imager gain and the exposure time are adjusted based on a predefined stepping sequence using a stepping table designed to...
US-7,245,300 Architecture for real-time texture look-up's for volume rendering
A slice plane, oriented parallel to a viewing plane, is passed through a cuboidal dataset at regular intervals. The intersection of the slice plane with the...
US-7,245,145 Memory module and method having improved signal routing topology
A registered memory module includes several memory devices coupled to a register through a plurality of transmission lines forming a symmetrical tree topology....
US-7,245,136 Methods of processing a workpiece, methods of communicating signals with respect to a wafer, and methods of...
An electronic device workpiece processing apparatus and method of communicating signals within an electronic device workpiece processing apparatus are provided....
US-7,245,010 System and device including a barrier layer
Systems and devices are disclosed utilizing a silicon-containing barrier layer. A semiconductor device is disclosed and includes a substrate, a gate oxide, a...
US-7,244,987 NROM flash memory devices on ultrathin silicon
An NROM flash memory cell is implemented in an ultra-thin silicon-on-insulator structure. In a planar device, the channel between the source/drain areas is...
US-7,244,981 Scalable high performance non-volatile memory cells using multi-mechanism carrier transport
A plurality of select gates are formed over a substrate. In one embodiment, the select gates are formed vertically on the sidewalls of trenches. The substrate...
US-7,244,918 Method and apparatus providing a two-way shared storage gate on a four-way shared pixel
A method of operating a pixel array includes activating a global storage signal to store a photosensor charge in a first storage region of each pixel, activating...
US-7,244,682 Methods of removing metal-containing materials
Various methods for selectively etching metal-containing materials (such as, for example, metal nitrides, which can include, for example, titanium nitride)...
US-7,244,681 Methods for selective removal of material from wafer alignment marks
A process and apparatus for locally removing any material, such as a refractory metal, in particular tungsten, from any desired area of a wafer, such as an...
US-7,244,678 Methods for planarization of Group VIII metal-containing surfaces using complexing agents
A planarization method includes providing a second and/or third row Group VIII metal-containing surface (preferably, a platinum-containing surface) and...
US-7,244,665 Wafer edge ring structures and methods of formation
An elevated containment structure in the shape of a wafer edge ring surrounding a surface of a semiconductor wafer is disclosed, as well as methods of forming...
US-7,244,663 Wafer reinforcement structure and methods of fabrication
A method of fabricating a thinned, reinforced semiconductor wafer is disclosed. Particularly, a semiconductor wafer may be provided and a plurality of separate...
US-7,244,659 Integrated circuits and methods of forming a field effect transistor
Integrated circuits and methods of forming field effect transistors are disclosed. In one aspect, an integrated circuit includes a semiconductor substrate...
US-7,244,648 Methods of forming semiconductor constructions
The invention encompasses a method of forming a silicon nitride layer. A substrate is provided which comprises a first mass and a second mass. The first mass...
US-7,244,646 Pixel design to improve photodiode capacitance and method of forming same
A CMOS imager with two adjacent pixel active area regions without the presence of an intervening trench isolation region that typically separates two adjacent...
US-7,244,637 Chip on board and heat sink attachment methods
A process for forming a thermally enhanced Chip On Board semiconductor device with a heat sink is described. In one aspect, a thermally conductive-filled gel...
US-7,243,290 Data encoding for fast CAM and TCAM access times
A method and apparatus for operating a content addressable memory (CAM) and a ternary CAM (TCAM) are described including an encoding circuit for encoding an...
US-7,242,603 Method of operating a complementary bit resistance memory sensor
The present invention relates to a method and apparatus for sensing the resistance state of a programmable resistance memory, using complementary memory...
US-7,242,332 Column-parallel sigma-delta analog-to-digital conversion with gain and offset control
A sigma-delta modulation sensing circuit and an analog-to-digital converter for an imager that eliminate the erroneous conversion of non-zero analog voltages to...
US-7,242,213 Memory module and method having improved signal routing topology
A registered memory module includes several memory devices coupled to a register through a plurality of transmission lines forming a symmetrical tree topology....
US-7,242,067 MRAM sense layer isolation
A process for forming an MRAM element. The process comprises patterning a globally deposited sense layer and then forming a spacer about the patterned sense...
US-7,242,057 Vertical transistor structures having vertical-surrounding-gates with self-aligned features
The present inventions include a vertical transistor formed by defining a channel length of the vertical-surrounding-gate field effect transistor with...
US-7,242,049 Memory device
A floating gate transistor has a reduced barrier energy at an interface with an adjacent gate insulator, allowing faster charge transfer across the gate...
US-7,241,705 Methods of forming conductive contacts to source/drain regions and methods of forming local interconnects
The invention comprises methods of forming a conductive contact to a source/drain region of a field effect transistor, and methods of forming local...
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