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Method of forming shallow doped junctions having a variable profile
gradation of dopants
Disclosed are methods for forming a shallow junction with a variable concentration profile gradation of dopants. The process of the present invention includes...
Techniques for packaging multiple device components
Techniques for fabricating multiple device components. Specifically, techniques for fabricating a stacked package comprising at least one I/C module and a...
Method of forming a mass over a semiconductor substrate
The invention includes methods of electrochemically treating semiconductor substrates. The invention includes a method of electroplating a substance. A substrate...
Top/bottom symmetrical protection scheme for flash
A synchronous flash memory includes an array of non-volatile memory cells. The memory device has a package configuration that is compatible with an SDRAM. The...
Selectable clock input
The present invention provides a memory device having a mode register with a selectable bit which sets the memory device to operate with a selected one of a...
Controlling multiple signal polarity in a semiconductor device
A method and apparatus for controlling multiple signal polarity in a memory device. A desired active state signal polarity of at least one signal pad of a device...
Memory device and method having banks of different sizes
A memory device, such as a synchronous random access memory device, includes four banks of memory cells arranged in rows and columns. Different numbers of...
Capacitor supported precharging of memory digit lines
Circuits and methods are provided for precharging pairs of memory digit lines. The final precharge voltage of the digit lines is different from the average of...
Circuit and method for operating a delay-lock loop in a power saving
A control circuit for a delay-lock loop having a delay line and a phase detector is used in a memory device. In a standby mode, the control circuit isolates a...
Programmable fuse and antifuse and method therefor
P-channel MOSFET devices are used as reprogrammable fuse or antifuse elements in a memory decode circuit by utilizing anomalous hole generation. An applied...
Apparatus and method for selectively configuring a memory device using a
The disclosed embodiments of the present invention include a semiconductor memory apparatus having a selectable memory capacity. In one embodiment, a system...
Capacitively-coupled level restore circuits for low voltage swing logic
A level restore circuit includes differential sides and a capacitive network having capacitors cross-coupled between the differential sides to provide a...
Contact system for wafer level testing
Disclosed herein are exemplary embodiments of a contact system (referred to as a "Z-block") for interfacing a semiconductor wafer to an electrical tester, and...
Apparatuses and methods for monitoring rotation of a conductive
Apparatuses and methods for monitoring microfeature workpiece rotation during processing, such as brushing, by monitoring characteristics corresponding to a...
Conductive connection forming methods, oxidation reducing methods, and
integrated circuits formed thereby
A conductive connection forming method includes forming a first layer comprising a first metal on a substrate and forming a second layer comprising a second...
Semiconductor package assembly and method for electrically isolating
A semiconductor package assembly and method for electrically isolating modules, having a capacitor within the semiconductor package assembly. The package...
Shallow trench isolation using low dielectric constant insulator
A shallow trench isolation is disclosed wherein the trench depth is reduced beyond that achieved in prior art processes. The reduced trench depth helps to...
Memory cell and method for forming the same
A semiconductor memory cell structure and method for forming the same. The memory cell is formed on a surface of a substrate and includes an active region formed...
Row driven imager pixel
An imaging system includes a pixel that does not require a row select transistor. Instead, an operating voltage is selectively provided to the pixel's readout...
The invention includes methods of forming regions of differing composition over a substrate. A first material having a pattern of at least one substantially...
Method for forming raised structures by controlled selective epitaxial
growth of facet using spacer
Raised structures comprising overlying silicon layers formed by controlled selective epitaxial growth, and methods for forming such raised-structure on a...
Transistor gate and local interconnect
A method of forming a local interconnect for a semiconductor integrated circuit, the local interconnect comprising a refractory silicide contact having a...
Semiconductor processing methods of forming integrated circuitry
Semiconductor processing methods of forming integrated circuitry are described. In one embodiment, memory circuitry and peripheral circuitry are formed over a...
Methods of forming electrical connections
In one aspect, the invention provides a method of forming an electrical connection in an integrated circuitry device. According to one preferred implementation,...
Interconnecting conductive layers of memory devices
Field-effect transistors, select gates, and select lines have first and second conductive layers separated by an interlayer dielectric layer. A conductive strap...
Method of fabricating a semiconductor device with a wet oxidation with
A method of fabricating a semiconductor device includes depositing a dielectric film and subjecting the dielectric film to a wet oxidation in a rapid thermal...
Methods of forming memory cells and arrays having underlying source-line
Floating-gate memory cells having a trench source-line contact are suited for increased packing densities without a need for low-resistance ground straps placed...
Methods of forming memory cells having diodes and electrode plates
connected to source/drain regions
The invention pertains to thin film constructions comprising NVRAM devices built over a versatile substrate base. In particular aspects, a device includes a body...
Magnetic tunneling junction antifuse device
An MRAM device having a plurality of MRAM cells formed of a fixed magnetic layer, a second soft magnetic layer and a dielectric layer interposed between the...
Prevention of photoresist scumming
A photo acid generator (PAG) or an acid is used to reduce resist scumming and footing. Diffusion of acid from photoresist into neighbors causes a decreased acid...
Small scale actuators and methods for their formation and use
An actuator assembly and method for making and using an actuator assembly. In one embodiment, the assembly includes an actuator body having an actuator channel...
ROM redundancy in ROM embedded DRAM
Redundancy in a read only memory (ROM) embedded dynamic random access memory (DRAM) is accomplished by programming redundancy elements such as antifuses or...
System and method for memory hub-based expansion bus
A system memory includes a memory hub controller, a memory module accessible by the memory hub controller, and an expansion module having a processor circuit...
Compact decode and multiplexing circuitry for a multi-port memory having a
common memory interface
A memory array for a multi-port memory having a common memory interface and a plurality of memory ports through which the memory array is accessed is provided....
Regulating voltages in semiconductor devices
The present invention provides a method and apparatus for regulating voltages in semiconductor devices. The method and apparatus includes providing a first...
Sense amplifier for a non-volatile memory device
The memory device has a plurality of memory cells each coupled to a bitline. A feedback transistor is coupled to the bitline and provides voltage feedback on the...
Current limiting antifuse programming path
Method and apparatus are disclosed for regulating an antifuse programming current by lightly doping an electrically connected region so that the resistance of...
Generating multi-phase clock signals using hierarchical delays
Circuits and methods for generating multi-phase clock signals using digitally-controlled hierarchical delay units (HDs) are provided. A plurality of...
Semiconductor device having a substrate an undoped silicon oxide structure
and an overlaying doped silicon...
An etchant including C.sub.2H.sub.xF.sub.y, where x is an integer from two to five, inclusive, where y is an integer from one to four, inclusive, and where x...
Multiple chip semiconductor package
A semiconductor device package and method of fabricating the same. The semiconductor device package may include a variety of semiconductor dice, thereby...
Electrical and thermal contact for use in semiconductor devices
An electrical and thermal contact for use in a semiconductor device. The electrical and thermal contact includes an intermediate conductive layer, an insulator...
Method of manufacturing devices comprising conductive nano-dots, and
devices comprising same
A method is disclosed that may include forming a first layer of insulating material above a semiconducting substrate, forming an aluminum oxide layer above the...
Epitaxial semiconductor layer and method
A method for epitaxially forming a first semiconductor structure attached to a second semiconductor structure is provided. Devices and methods described include...
High dielectric constant transition metal oxide materials
A transition metal oxide dielectric material is doped with a non-metal in order to enhance the electrical properties of the metal oxide. In a preferred...
Apparatus and method for conditioning and monitoring media used for
A method and apparatus for conditioning and monitoring a planarizing medium used for planarizing a microelectronic substrate. In one embodiment, the apparatus...
Edge connector including internal layer contact, printed circuit board and
electronic module incorporating same
An edge connector, system, printed circuit board and electronic module are described, which include an edge connector comprised of a substrate, including a first...
Method and system for creating a netlist allowing current measurement
through a sub-circuit
A system and method for manipulating a netlist, at the time that the netlist is being created, to permit measurement of current flow through a net, or...
Dual port memory with asymmetric inputs and outputs, device, system and
An asymmetric memory interface including an asymmetric read data interface having a read bus width configured to transfer data from a memory device to a memory...
Radio frequency data communications device
A radio frequency identification device includes an integrated circuit including a receiver, a transmitter, and a microprocessor. The receiver and transmitter...
Data path having grounded precharge operation and test compression
A data path for coupling data between a memory cell and an input/output (IO) line sense amplifier. An IO line coupling circuit is coupled to a pair of global...