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Patent # Description
US-7,189,611 Metal plating using seed film
A seed film and methods incorporating the seed film in semiconductor applications is provided. The seed film includes one or more noble metal layers, where each...
US-7,189,607 Formation of standard voltage threshold and low voltage threshold MOSFET devices
Wells are formed in a substrate where standard Vt and low Vt devices of both a first and second type are to be fabricated. Wells defining the locations of first...
US-7,189,606 Method of forming fully-depleted (FD) SOI MOSFET access transistor
A fully-depleted (FD) Silicon-on-Insulator (SOI) MOSFET access transistor comprising a gate electrode of a conductivity type which is opposite the conductivity...
US-7,189,602 Method and apparatus for reducing substrate bias voltage drop
A semiconductor device is provided with a conductive layer provided on a backside of a semiconductor substrate. The conductive layer helps maintain a uniform...
US-7,189,600 Methods for fabricating stiffeners for flexible substrates
Methods for fabricating stiffeners for flexible substrates, including, but not limited to, tapes, films, or other connective structures, which are configured to...
US-7,189,593 Elimination of RDL using tape base flip chip on flex for die stacking
A flexible film interposer for stacking a flip chip semiconductor die onto a second (bottom) semiconductor die, semiconductor devices and stacked die assemblies...
US-7,189,583 Method for production of MRAM elements
Magneto-resistive random access memory elements include a ferromagnetic layer having uniaxial anisotropy provided by elongate structures formed in the...
US-7,189,333 End effectors and methods for manufacturing end effectors with contact elements to condition polishing pads...
End effectors, apparatuses including end effectors for conditioning planarizing pads, and methods for manufacturing end effectors with contact elements to...
US-7,189,317 Semiconductor manufacturing system for forming metallization layer
A method for forming a metallization layer. A first layer is formed outwardly from a semiconductor substrate. Contact vias are formed through the first layer to...
US-7,189,305 Gas-assist systems for applying and moving ozonated resist stripper to resist-bearing surfaces of substrates
A method for moving resist stripper across the surface of a semiconductor substrate that includes applying a wet chemical resist stripper, such as an organic or...
US-7,189,287 Atomic layer deposition using electron bombardment
Formation of a layer of material on a surface by atomic layer deposition methods and systems includes using electron bombardment of the chemisorbed precursor.
US-7,189,153 Retaining rings, planarizing apparatuses including retaining rings, and methods for planarizing micro-device...
Retaining rings, planarizing apparatuses including retaining rings, and methods for mechanical and/or chemical-mechanical planarization of micro-device...
US-7,188,219 Buffer control system and method for a memory system having outstanding read and write request buffers
A memory controller and method for managing the issuance of read and write requests to a system memory is provided. The number of outstanding read requests and...
US-7,188,217 Embedded DRAM cache memory and method having reduced latency
A computer system includes a processor, a system memory, and an integrated circuit system controller coupled to the processor and the system memory. The system...
US-7,188,036 Internal bias measure with onboard ADC for electronic devices
An apparatus and method for on-chip bias measurement of an analog signals on an integrated circuit with a switchable analog-to-digital converter capable of...
US-7,187,617 Memory system and method for strobing data, command and address signals
A memory system couples command, address or write data signals from a memory controller to a memory device and read data signals from the memory device to the...
US-7,187,601 Active termination circuit and method for controlling the impedance of external integrated circuit terminals
An active termination circuit is used to set the input impedance of a plurality of input terminals. Each of the input terminals is coupled to a supply voltage...
US-7,187,587 Programmable memory address and decode circuits with low tunnel barrier interpoly insulators
Structures and methods for programmable memory address and decode circuits with low tunnel barrier interpoly insulators are provided. The decoder for a memory...
US-7,187,574 High speed data bus
The invention comprises data processing systems and components thereof. Such systems may include a memory controller, a plurality of memory devices, a data bus...
US-7,187,219 Power-on-reset circuit based on the threshold levels and quadratic I-V behavior of MOS transistors
A system and method for providing a clock-independent reset signal based on supply voltage threshold levels is described. The trip points or predefined voltage...
US-7,187,190 Contact pad arrangement on a die
An integrated device includes a redundant bond pad for accessing internal circuitry in the event that the main bond pad for that circuitry is difficult to access...
US-7,187,049 Data download to imager chip using image sensor as a receptor
An imaging device having a CMOS photosensor array for capturing images is described in which the array is also used to input programming and/or data used to...
US-7,187,047 Method and structure for reducing resistance of a semiconductor device feature
A method used to form a semiconductor device comprises forming a polysilicon layer, forming a conductive barrier layer on the polysilicon layer, then forming a...
US-7,187,018 Reduced barrier photodiode/transfer gate device structure of high efficiency charge transfer and reduced lag...
A pixel cell having a reduced potential barrier near a region where a gate and a photodiode are in close proximity to one another, and a method for forming the...
US-7,186,964 Dark current reduction circuitry for CMOS active pixel sensors
A row driver circuit is disclosed for supplying a reset voltage to a plurality of reset transistors of an active pixel sensor array while minimizing gate induced...
US-7,186,664 Methods and structures for metal interconnections in integrated circuits
A typical integrated-circuit fabrication requires interconnecting millions of microscopic transistors and resistors with metal wires. Making the metal wires...
US-7,186,643 Barrier-metal-free copper damascene technology using atomic hydrogen enhanced reflow
A method for forming conductive contacts and interconnects in a semiconductor structure, and the resulting conductive components are provided. In particular, the...
US-7,186,642 Low temperature nitride used as Cu barrier layer
A method of depositing a non-conductive barrier layer onto a metal surface wherein the resistance of the metal remains substantially unchanged before and after...
US-7,186,638 Passivation processes for use with metallization techniques
A method for passivating a substrate, such as a semiconductor substrate, that is to be "metallized," or on which a metal film or structure is to be formed,...
US-7,186,636 Nickel bonding cap over copper metalized bondpads
A method for forming a nickel cap layer over copper metalized bond pad is disclosed in which the phosphorous content of the nickel cap, and particularly the...
US-7,186,608 Masked nitrogen enhanced gate oxide
A method for fabricating improved integrated circuit devices. The method enables selective hardening of gate oxide layers and includes providing a semiconductor...
US-7,186,589 Method for fabricating semiconductor components using mold cavities having runners configured to minimize venting
A system for fabricating semiconductor components includes mating mold cavity plates having mold cavities configured to mold body segments of the semiconductor...
US-7,186,576 Stacked die module and techniques for forming a stacked die module
Embodiments of the present technique relate to forming die stacks. Specifically, embodiments of the present technique include a method of forming and testing...
US-7,186,486 Method to pattern a substrate
An aspect of the present invention includes a method of lithography to enhance uniformity of critical dimensions of features patterned onto a workpiece. Said...
US-7,186,480 Method for adjusting dimensions of photomask features
A method for adjusting one or more dimensions of a photomask subsequent to etching of a defective pattern in the chrome-containing layer thereof is provided. The...
US-7,186,168 Chemical mechanical polishing apparatus and methods for chemical mechanical polishing
The present invention provides a deformable pad useful for chemical mechanical polishing ("CMP"), a CMP apparatus incorporating the deformable pad of the present...
US-7,185,601 Chemically sensitive warning apparatus and method
A chemically sensitive warning apparatus capable of changing colors upon contact with a chemical is disclosed. The apparatus preferably comprises an elongated...
US-7,185,173 Column address path circuit and method for memory devices having a burst access mode
Column addresses are generated by a burst controller that includes respective latches for the three low-order bits of a column address. The two higher order bits...
US-7,185,154 Single segment data object management
A single segment data structure and method for storing data objects employing a single segment data object having a header and a data record. The header includes...
US-7,184,551 Public key cryptography using matrices
The invention provides techniques for secure messages transmission using a public key system to exchange secret keys. A first entity creates public and private...
US-7,184,352 Memory system and method using ECC to achieve low power refresh
Rows of DRAM memory cells are refreshed at either a relatively high rate during normal operation or a relatively slow rate in a reduced power refresh mode. Prior...
US-7,184,329 Alignment of memory read data and clocking
Circuits and methods are provided for aligning data read from a memory with an output clock signal when the memory is operated at very high clock frequencies. To...
US-7,184,327 System and method for enhanced mode register definitions
Apparatus and methods for increasing a number of selectable options for an operating mode. A number of selectable options for an operating mode is increased by...
US-7,184,315 NROM flash memory with self-aligned structural charge separation
A nitride read only memory (NROM) cell has a nitride layer that is not located under the center of the transistor. The gate insulator layer, with the nitride...
US-7,184,312 One transistor SOI non-volatile random access memory cell
One aspect of the present subject matter relates to a memory cell, or more specifically, to a one-transistor SOI non-volatile memory cell. In various...
US-7,184,292 High speed data bus
The invention comprises data processing systems and components thereof. Such systems may include a memory controller, a plurality of memory devices, a data bus...
US-7,184,284 Closed-loop high voltage booster
A voltage boosting circuit with a closed-loop control mechanism and a controllable slew rate. A tracking capacitor and a control current form the closed-loop and...
US-7,184,192 Pattern generator diffractive mirror methods and systems
The present invention relates to an apparatus for creating a pattern on a workpiece sensitive to radiation, such as a photomask a display panel or a microoptical...
US-7,183,792 Method and system for detecting a mode of operation of an integrated circuit, and a memory device including same
A threshold detection circuit for developing a mode trigger signal includes an input that receives an input signal. In response to the input signal having...
US-7,183,790 System and method for testing devices utilizing capacitively coupled signaling
An apparatus and method for testing a semiconductor device in an AC test regime. The test apparatus includes a test plate capacitively couple to the signal...
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