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Patent # Description
US-7,199,349 Amplification with feedback capacitance for photodetector signals
Signals from an imager pixel photodetector are received by an amplifier having capacitive feedback, such as a capacitive transimpedance amplifier (CTIA). The...
US-7,199,347 Layered microlens structures and devices
A microlens structure includes lower lens layers on a substrate. A sputtered layer of glass, such as silicon oxide, is applied over the lower lens layers at an...
US-7,199,050 Pass through via technology for use during the manufacture of a semiconductor device
A method for forming vias which pass through a semiconductor wafer substrate assembly such as a semiconductor die or wafer allows two different types of...
US-7,199,037 Microfeature devices and methods for manufacturing microfeature devices
Microfeature devices, microfeature workpieces, and methods for manufacturing microfeature devices and microfeature workpieces are disclosed herein. The...
US-7,199,023 Atomic layer deposited HfSiON dielectric films wherein each precursor is independendently pulsed
A dielectric film containing atomic layer deposited HfSiON and a method of fabricating such a dielectric film produce a reliable dielectric layer having an...
US-7,199,017 Methods of forming semiconductor circuitry
The invention includes a method of forming semiconductor circuitry. A monocrystalline silicon substrate is provided, and a mask is formed which covers a first...
US-7,199,005 Methods of forming pluralities of capacitors
The invention comprises methods of forming pluralities of capacitors. In one implementation, metal is formed over individual capacitor storage node locations on...
US-7,198,999 Flash memory device having a graded composition, high dielectric constant gate insulator
A graded composition, high dielectric constant gate insulator is deposited between a substrate and floating gate in a flash memory cell transistor. If the...
US-7,198,980 Methods for assembling multiple semiconductor devices
A multidie semiconductor device (MDSCD) package includes a generally planar interposer comprising a substrate with a central receptacle, upper surface...
US-7,198,974 Micro-mechanically strained semiconductor film
One aspect of the present subject matter relates to a method for forming strained semiconductor film. In various embodiments, a single crystalline semiconductor...
US-7,198,693 Microelectronic device having a plurality of stacked dies and methods for manufacturing such microelectronic...
Systems and methods for assembling microelectronic devices that have a base die and a conventional wire-bond die stacked on the base die. In one embodiment of a...
US-RE39,547 Method and apparatus for endpointing mechanical and chemical-mechanical polishing of substrates
An apparatus and method for stopping mechanical and chemical-mechanical polishing of a substrate at a desired endpoint. In one embodiment, a polishing machine...
US-7,197,674 Method and apparatus for conditioning of a digital pulse
An integrated circuit includes a first external pin and an input buffer connected to the first external pin. The input buffer includes an output terminal and a...
US-7,197,607 Non-volatile memory with concurrent write and read operation to differing banks
A synchronous flash memory includes an array of non-volatile memory cells. The memory array is arranged in rows and columns, and can be further arranged in...
US-7,197,603 Method and apparatus for high performance branching in pipelined microsystems
A pipelined processor includes a branch acceleration technique which is based on an improved branch cache. The improved branch cache minimizes or eliminates...
US-7,196,964 Selectable memory word line deactivation
Circuitry and methods allow selected memory word lines (WLs) to be deactivated without using a global deactivate signal. All active WLs do not therefore have to...
US-7,196,958 Power efficient memory and cards
A memory with an internal detection mechanism to detect the presence of either an external component of an external voltage on some no connect pins, allowing a...
US-7,196,936 Ballistic injection NROM flash memory
A split NROM flash memory cell is comprised of source/drain regions in a substrate. The split nitride charge storage regions are insulated from the substrate by...
US-7,196,935 Ballistic injection NROM flash memory
A split NROM flash memory cell is comprised of source/drain regions in a substrate. The split nitride charge storage regions are insulated from the substrate by...
US-7,196,934 Non-volatile memory with erase verify circuit having comparators indicating under-erasure, erasure, and...
A memory device verify system determines a state of memory cells in a memory. The memory includes a memory array having a plurality of memory cells coupled to...
US-7,196,930 Flash memory programming to reduce program disturb
The method for reducing program disturb in a flash memory array biases a selected wordline at a programming voltage. One of the unselected wordlines, closer to...
US-7,196,929 Method for operating a memory device having an amorphous silicon carbide gate insulator
A floating gate transistor has a reduced barrier energy at an interface with an adjacent amorphous silicon carbide (a-SiC) gate insulator, allowing faster charge...
US-7,196,882 Magnetic tunnel junction device and its method of fabrication
The present invention provides a magnetic tunnel junction memory element comprising two pinned ferromagnetic layers having magnetic orientations pointing in...
US-7,196,829 Digital image system and method for combining sensing and image processing on sensor with two-color photo-detector
A digital image system is disclosed having a sensor with an elevated two-color photo-detector for sensing two different color values in combination with a...
US-7,196,544 Communication device for a logic circuit
A circuit is provided to isolate a contact pad from a logic circuit of a die once the contact pad is no longer needed. This circuit can take many forms including...
US-7,196,394 Method and apparatus for a deposited fill layer
A method of forming a semiconducting wafer is provided that utilizes fewer processing operations, reduces process variation, and lowers cost as well as...
US-7,196,304 Row driver for selectively supplying operating power to imager pixel
An imaging system includes a pixel that does not require a row select transistor. Instead, an operating voltage is selectively provided to the pixel's readout...
US-7,196,020 Method for PECVD deposition of selected material films
A process for PECVD of selected material films on a substrate comprising the steps of placing a substrate in a PECVD chamber and maintaining the chamber under...
US-7,196,007 Systems and methods of forming refractory metal nitride layers using disilazanes
A method of forming (and apparatus for forming) refractory metal nitride layers (including silicon nitride layers), such as a tantalum (silicon) nitride barrier...
US-7,195,999 Metal-substituted transistor gates
One aspect of this disclosure relates to a method for forming a transistor. According to various method embodiments, a gate dielectric is formed on a substrate,...
US-7,195,995 Method of manufacturing a multilayered doped conductor for a contact in an integrated circuit device
A method of manufacturing a memory device addressing reliability and refresh characteristics through the use of a multilayered doped conductor, and a method...
US-7,195,957 Packaged microelectronic components
A microelectronic component package includes a plurality of electrical leads which are coupled to a microelectronic component and which have exposed lengths...
US-7,195,947 Photodiode with self-aligned implants for high quantum efficiency and method of formation
A pinned photodiode with a pinned surface layer formed by a self-aligned angled implant is disclosed. The angle of the implant may be tailored to provide an...
US-7,195,940 Methods for packaging image sensitive electronic devices
The invention provides methods for packaging for electronic devices that are light or other radiation-sensitive, such as image sensors including CCD or CMOS...
US-7,194,667 System for storing device test information on a semiconductor device using on-device logic for determination of...
A system for testing a semiconductor device and storing device test results in nonvolatile memory elements on the tested device, in which the semiconductor...
US-7,194,593 Memory hub with integrated non-volatile memory
A memory hub having an integrated non-volatile memory for storing configuration information is provided. The memory hub includes a high-speed interface for...
US-7,193,927 Memory device and method having banks of different sizes
A memory device, such as a synchronous random access memory device, includes four banks of memory cells arranged in rows and columns. Different numbers of...
US-7,193,914 Open digit line array architecture for a memory array
A system and method for sensing a data state stored by a memory cell that includes coupling a first digit line and a second digit line to a precharge voltage and...
US-7,193,910 Adjustable timing circuit of an integrated circuit
An adjustable timing circuit includes non-volatile programmable fuses and adjustable delay elements. A propagation time of the delay element is selected with the...
US-7,193,899 Erase block data splitting
A Flash memory device, system, and data handling routine is detailed with a distributed erase block sector user/overhead data scheme that splits the user data...
US-7,193,893 Write once read only memory employing floating gates
Structures and methods for write once read only memory employing floating gates are provided. The write once read only memory cell includes a floating gate...
US-7,193,312 Castellation wafer level packaging of integrated circuit chips
Systems and methods for packaging integrated circuit chips in castellation wafer level packaging are provided. The active circuit areas of the chips are coupled...
US-7,193,306 Semiconductor structure having stacked semiconductor devices
A semiconductor structure includes flip chips or other semiconductor devices that are mounted on printed circuit boards. The printed circuit boards are stacked...
US-7,193,285 Tilted array geometry for improved MRAM switching
An array of conductive lines for MRAM circuits wherein at least one set of mutually parallel conductive traces is tilted with respect to being perpendicular with...
US-7,193,273 Method for enhancing vertical growth during the selective formation of silicon, and structures formed using same
A method of selectively forming contact regions on a substrate having a plurality of exposed regions includes selectively forming a contact region on each of the...
US-7,193,266 Strapping word lines of NAND memory devices
Apparatus and methods are provided. Conductive straps are connected to a subset of word lines of a memory device. Alternatively, first conductive straps are...
US-7,192,893 Use of linear injectors to deposit uniform selective ozone TEOS oxide film by pulsing reactants on and off
A process for enhanced selective deposition of a silicon oxide onto a substrate by pulsing delivery of the reactants through a linear injector is disclosed. The...
US-7,192,892 Atomic layer deposited dielectric layers
An atomic layer deposited dielectric layer and a method of fabricating such a dielectric layer produce a reliable dielectric layer having an equivalent oxide...
US-7,192,889 Methods for forming a high dielectric film
A method of forming a high dielectric oxide film conventionally formed using a post formation oxygen anneal to reduce the leakage current of such film includes...
US-7,192,888 Low selectivity deposition methods
A deposition method includes forming a nucleation layer over a substrate, forming a layer of a first substance at least one monolayer thick chemisorbed on the...
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