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Patent # Description
US-7,179,717 Methods of forming integrated circuit devices
Forming an integrated circuit device includes forming a hard mask layer overlying a semiconductor substrate. The hard mask layer is patterned to expose portions...
US-7,179,716 Method of forming a metal-containing layer over selected regions of a semiconductor substrate
The invention includes methods of electrochemically treating semiconductor substrates. The invention includes a method of electroplating a substance. A substrate...
US-7,179,706 Permeable capacitor electrode
The present teachings describe a container capacitor that utilizes an etchant permeable lower electrode for the formation of single or double-sided capacitors...
US-7,179,703 Method of forming shallow doped junctions having a variable profile gradation of dopants
Disclosed are methods for forming a shallow junction with a variable concentration profile gradation of dopants. The process of the present invention includes...
US-7,179,681 Techniques for packaging multiple device components
Techniques for fabricating multiple device components. Specifically, techniques for fabricating a stacked package comprising at least one I/C module and a...
US-7,179,361 Method of forming a mass over a semiconductor substrate
The invention includes methods of electrochemically treating semiconductor substrates. The invention includes a method of electroplating a substance. A substrate...
US-7,177,976 Top/bottom symmetrical protection scheme for flash
A synchronous flash memory includes an array of non-volatile memory cells. The memory device has a package configuration that is compatible with an SDRAM. The...
US-7,177,231 Selectable clock input
The present invention provides a memory device having a mode register with a selectable bit which sets the memory device to operate with a selected one of a...
US-7,177,224 Controlling multiple signal polarity in a semiconductor device
A method and apparatus for controlling multiple signal polarity in a memory device. A desired active state signal polarity of at least one signal pad of a device...
US-7,177,223 Memory device and method having banks of different sizes
A memory device, such as a synchronous random access memory device, includes four banks of memory cells arranged in rows and columns. Different numbers of...
US-7,177,213 Capacitor supported precharging of memory digit lines
Circuits and methods are provided for precharging pairs of memory digit lines. The final precharge voltage of the digit lines is different from the average of...
US-7,177,208 Circuit and method for operating a delay-lock loop in a power saving manner
A control circuit for a delay-lock loop having a delay line and a phase detector is used in a memory device. In a standby mode, the control circuit isolates a...
US-7,177,193 Programmable fuse and antifuse and method therefor
P-channel MOSFET devices are used as reprogrammable fuse or antifuse elements in a memory decode circuit by utilizing anomalous hole generation. An applied...
US-7,177,170 Apparatus and method for selectively configuring a memory device using a bi-stable relay
The disclosed embodiments of the present invention include a semiconductor memory apparatus having a selectable memory capacity. In one embodiment, a system...
US-7,176,719 Capacitively-coupled level restore circuits for low voltage swing logic circuits
A level restore circuit includes differential sides and a capacitive network having capacitors cross-coupled between the differential sides to provide a...
US-7,176,702 Contact system for wafer level testing
Disclosed herein are exemplary embodiments of a contact system (referred to as a "Z-block") for interfacing a semiconductor wafer to an electrical tester, and...
US-7,176,676 Apparatuses and methods for monitoring rotation of a conductive microfeature workpiece
Apparatuses and methods for monitoring microfeature workpiece rotation during processing, such as brushing, by monitoring characteristics corresponding to a...
US-7,176,576 Conductive connection forming methods, oxidation reducing methods, and integrated circuits formed thereby
A conductive connection forming method includes forming a first layer comprising a first metal on a substrate and forming a second layer comprising a second...
US-7,176,566 Semiconductor package assembly and method for electrically isolating modules
A semiconductor package assembly and method for electrically isolating modules, having a capacitor within the semiconductor package assembly. The package...
US-7,176,549 Shallow trench isolation using low dielectric constant insulator
A shallow trench isolation is disclosed wherein the trench depth is reduced beyond that achieved in prior art processes. The reduced trench depth helps to...
US-7,176,513 Memory cell and method for forming the same
A semiconductor memory cell structure and method for forming the same. The memory cell is formed on a surface of a substrate and includes an active region formed...
US-7,176,434 Row driven imager pixel
An imaging system includes a pixel that does not require a row select transistor. Instead, an operating voltage is selectively provided to the pixel's readout...
US-7,176,118 Circuit constructions
The invention includes methods of forming regions of differing composition over a substrate. A first material having a pattern of at least one substantially...
US-7,176,109 Method for forming raised structures by controlled selective epitaxial growth of facet using spacer
Raised structures comprising overlying silicon layers formed by controlled selective epitaxial growth, and methods for forming such raised-structure on a...
US-7,176,096 Transistor gate and local interconnect
A method of forming a local interconnect for a semiconductor integrated circuit, the local interconnect comprising a refractory silicide contact having a...
US-7,176,093 Semiconductor processing methods of forming integrated circuitry
Semiconductor processing methods of forming integrated circuitry are described. In one embodiment, memory circuitry and peripheral circuitry are formed over a...
US-7,176,087 Methods of forming electrical connections
In one aspect, the invention provides a method of forming an electrical connection in an integrated circuitry device. According to one preferred implementation,...
US-7,176,086 Interconnecting conductive layers of memory devices
Field-effect transistors, select gates, and select lines have first and second conductive layers separated by an interlayer dielectric layer. A conductive strap...
US-7,176,079 Method of fabricating a semiconductor device with a wet oxidation with steam process
A method of fabricating a semiconductor device includes depositing a dielectric film and subjecting the dielectric film to a wet oxidation in a rapid thermal...
US-7,176,077 Methods of forming memory cells and arrays having underlying source-line connections
Floating-gate memory cells having a trench source-line contact are suited for increased packing densities without a need for low-resistance ground straps placed...
US-7,176,073 Methods of forming memory cells having diodes and electrode plates connected to source/drain regions
The invention pertains to thin film constructions comprising NVRAM devices built over a versatile substrate base. In particular aspects, a device includes a body...
US-7,176,065 Magnetic tunneling junction antifuse device
An MRAM device having a plurality of MRAM cells formed of a fixed magnetic layer, a second soft magnetic layer and a dielectric layer interposed between the...
US-7,175,944 Prevention of photoresist scumming
A photo acid generator (PAG) or an acid is used to reduce resist scumming and footing. Diffusion of acid from photoresist into neighbors causes a decreased acid...
US-7,175,772 Small scale actuators and methods for their formation and use
An actuator assembly and method for making and using an actuator assembly. In one embodiment, the assembly includes an actuator body having an actuator channel...
US-7,174,477 ROM redundancy in ROM embedded DRAM
Redundancy in a read only memory (ROM) embedded dynamic random access memory (DRAM) is accomplished by programming redundancy elements such as antifuses or...
US-7,174,409 System and method for memory hub-based expansion bus
A system memory includes a memory hub controller, a memory module accessible by the memory hub controller, and an expansion module having a processor circuit...
US-7,173,874 Compact decode and multiplexing circuitry for a multi-port memory having a common memory interface
A memory array for a multi-port memory having a common memory interface and a plurality of memory ports through which the memory array is accessed is provided....
US-7,173,869 Regulating voltages in semiconductor devices
The present invention provides a method and apparatus for regulating voltages in semiconductor devices. The method and apparatus includes providing a first...
US-7,173,856 Sense amplifier for a non-volatile memory device
The memory device has a plurality of memory cells each coupled to a bitline. A feedback transistor is coupled to the bitline and provides voltage feedback on the...
US-7,173,855 Current limiting antifuse programming path
Method and apparatus are disclosed for regulating an antifuse programming current by lightly doping an electrically connected region so that the resistance of...
US-7,173,463 Generating multi-phase clock signals using hierarchical delays
Circuits and methods for generating multi-phase clock signals using digitally-controlled hierarchical delay units (HDs) are provided. A plurality of...
US-7,173,339 Semiconductor device having a substrate an undoped silicon oxide structure and an overlaying doped silicon...
An etchant including C.sub.2H.sub.xF.sub.y, where x is an integer from two to five, inclusive, where y is an integer from one to four, inclusive, and where x...
US-7,173,330 Multiple chip semiconductor package
A semiconductor device package and method of fabricating the same. The semiconductor device package may include a variety of semiconductor dice, thereby...
US-7,173,317 Electrical and thermal contact for use in semiconductor devices
An electrical and thermal contact for use in a semiconductor device. The electrical and thermal contact includes an intermediate conductive layer, an insulator...
US-7,173,304 Method of manufacturing devices comprising conductive nano-dots, and devices comprising same
A method is disclosed that may include forming a first layer of insulating material above a semiconducting substrate, forming an aluminum oxide layer above the...
US-7,172,949 Epitaxial semiconductor layer and method
A method for epitaxially forming a first semiconductor structure attached to a second semiconductor structure is provided. Devices and methods described include...
US-7,172,947 High dielectric constant transition metal oxide materials
A transition metal oxide dielectric material is doped with a non-metal in order to enhance the electrical properties of the metal oxide. In a preferred...
US-7,172,491 Apparatus and method for conditioning and monitoring media used for chemical-mechanical planarization
A method and apparatus for conditioning and monitoring a planarizing medium used for planarizing a microelectronic substrate. In one embodiment, the apparatus...
US-7,172,465 Edge connector including internal layer contact, printed circuit board and electronic module incorporating same
An edge connector, system, printed circuit board and electronic module are described, which include an edge connector comprised of a substrate, including a first...
US-7,171,642 Method and system for creating a netlist allowing current measurement through a sub-circuit
A system and method for manipulating a netlist, at the time that the netlist is being created, to permit measurement of current flow through a net, or...
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