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Patent # Description
US-7,176,576 Conductive connection forming methods, oxidation reducing methods, and integrated circuits formed thereby
A conductive connection forming method includes forming a first layer comprising a first metal on a substrate and forming a second layer comprising a second...
US-7,176,566 Semiconductor package assembly and method for electrically isolating modules
A semiconductor package assembly and method for electrically isolating modules, having a capacitor within the semiconductor package assembly. The package...
US-7,176,549 Shallow trench isolation using low dielectric constant insulator
A shallow trench isolation is disclosed wherein the trench depth is reduced beyond that achieved in prior art processes. The reduced trench depth helps to...
US-7,176,513 Memory cell and method for forming the same
A semiconductor memory cell structure and method for forming the same. The memory cell is formed on a surface of a substrate and includes an active region formed...
US-7,176,434 Row driven imager pixel
An imaging system includes a pixel that does not require a row select transistor. Instead, an operating voltage is selectively provided to the pixel's readout...
US-7,176,118 Circuit constructions
The invention includes methods of forming regions of differing composition over a substrate. A first material having a pattern of at least one substantially...
US-7,176,109 Method for forming raised structures by controlled selective epitaxial growth of facet using spacer
Raised structures comprising overlying silicon layers formed by controlled selective epitaxial growth, and methods for forming such raised-structure on a...
US-7,176,096 Transistor gate and local interconnect
A method of forming a local interconnect for a semiconductor integrated circuit, the local interconnect comprising a refractory silicide contact having a...
US-7,176,093 Semiconductor processing methods of forming integrated circuitry
Semiconductor processing methods of forming integrated circuitry are described. In one embodiment, memory circuitry and peripheral circuitry are formed over a...
US-7,176,087 Methods of forming electrical connections
In one aspect, the invention provides a method of forming an electrical connection in an integrated circuitry device. According to one preferred implementation,...
US-7,176,086 Interconnecting conductive layers of memory devices
Field-effect transistors, select gates, and select lines have first and second conductive layers separated by an interlayer dielectric layer. A conductive strap...
US-7,176,079 Method of fabricating a semiconductor device with a wet oxidation with steam process
A method of fabricating a semiconductor device includes depositing a dielectric film and subjecting the dielectric film to a wet oxidation in a rapid thermal...
US-7,176,077 Methods of forming memory cells and arrays having underlying source-line connections
Floating-gate memory cells having a trench source-line contact are suited for increased packing densities without a need for low-resistance ground straps placed...
US-7,176,073 Methods of forming memory cells having diodes and electrode plates connected to source/drain regions
The invention pertains to thin film constructions comprising NVRAM devices built over a versatile substrate base. In particular aspects, a device includes a body...
US-7,176,065 Magnetic tunneling junction antifuse device
An MRAM device having a plurality of MRAM cells formed of a fixed magnetic layer, a second soft magnetic layer and a dielectric layer interposed between the...
US-7,175,944 Prevention of photoresist scumming
A photo acid generator (PAG) or an acid is used to reduce resist scumming and footing. Diffusion of acid from photoresist into neighbors causes a decreased acid...
US-7,175,772 Small scale actuators and methods for their formation and use
An actuator assembly and method for making and using an actuator assembly. In one embodiment, the assembly includes an actuator body having an actuator channel...
US-7,174,477 ROM redundancy in ROM embedded DRAM
Redundancy in a read only memory (ROM) embedded dynamic random access memory (DRAM) is accomplished by programming redundancy elements such as antifuses or...
US-7,174,409 System and method for memory hub-based expansion bus
A system memory includes a memory hub controller, a memory module accessible by the memory hub controller, and an expansion module having a processor circuit...
US-7,173,874 Compact decode and multiplexing circuitry for a multi-port memory having a common memory interface
A memory array for a multi-port memory having a common memory interface and a plurality of memory ports through which the memory array is accessed is provided....
US-7,173,869 Regulating voltages in semiconductor devices
The present invention provides a method and apparatus for regulating voltages in semiconductor devices. The method and apparatus includes providing a first...
US-7,173,856 Sense amplifier for a non-volatile memory device
The memory device has a plurality of memory cells each coupled to a bitline. A feedback transistor is coupled to the bitline and provides voltage feedback on the...
US-7,173,855 Current limiting antifuse programming path
Method and apparatus are disclosed for regulating an antifuse programming current by lightly doping an electrically connected region so that the resistance of...
US-7,173,463 Generating multi-phase clock signals using hierarchical delays
Circuits and methods for generating multi-phase clock signals using digitally-controlled hierarchical delay units (HDs) are provided. A plurality of...
US-7,173,339 Semiconductor device having a substrate an undoped silicon oxide structure and an overlaying doped silicon...
An etchant including C.sub.2H.sub.xF.sub.y, where x is an integer from two to five, inclusive, where y is an integer from one to four, inclusive, and where x...
US-7,173,330 Multiple chip semiconductor package
A semiconductor device package and method of fabricating the same. The semiconductor device package may include a variety of semiconductor dice, thereby...
US-7,173,317 Electrical and thermal contact for use in semiconductor devices
An electrical and thermal contact for use in a semiconductor device. The electrical and thermal contact includes an intermediate conductive layer, an insulator...
US-7,173,304 Method of manufacturing devices comprising conductive nano-dots, and devices comprising same
A method is disclosed that may include forming a first layer of insulating material above a semiconducting substrate, forming an aluminum oxide layer above the...
US-7,172,949 Epitaxial semiconductor layer and method
A method for epitaxially forming a first semiconductor structure attached to a second semiconductor structure is provided. Devices and methods described include...
US-7,172,947 High dielectric constant transition metal oxide materials
A transition metal oxide dielectric material is doped with a non-metal in order to enhance the electrical properties of the metal oxide. In a preferred...
US-7,172,491 Apparatus and method for conditioning and monitoring media used for chemical-mechanical planarization
A method and apparatus for conditioning and monitoring a planarizing medium used for planarizing a microelectronic substrate. In one embodiment, the apparatus...
US-7,172,465 Edge connector including internal layer contact, printed circuit board and electronic module incorporating same
An edge connector, system, printed circuit board and electronic module are described, which include an edge connector comprised of a substrate, including a first...
US-7,171,642 Method and system for creating a netlist allowing current measurement through a sub-circuit
A system and method for manipulating a netlist, at the time that the netlist is being created, to permit measurement of current flow through a net, or...
US-7,171,508 Dual port memory with asymmetric inputs and outputs, device, system and method
An asymmetric memory interface including an asymmetric read data interface having a read bus width configured to transfer data from a memory device to a memory...
US-7,170,867 Radio frequency data communications device
A radio frequency identification device includes an integrated circuit including a receiver, a transmitter, and a microprocessor. The receiver and transmitter...
US-7,170,806 Data path having grounded precharge operation and test compression capability
A data path for coupling data between a memory cell and an input/output (IO) line sense amplifier. An IO line coupling circuit is coupled to a pair of global...
US-7,170,783 Layout for NAND flash memory array having reduced word line impedance
A memory array including a first region in which a first memory sub-array is located and a second region separated from the first region in which a second memory...
US-7,170,361 Method and apparatus of interposing voltage reference traces between signal traces in semiconductor devices
A method and apparatus for substantially reducing or eliminating electromagnetic and electrostatic coupling between signal traces on a substrate is disclosed. A...
US-7,170,304 Selectively configurable probe structures, e.g., selectively configurable probe cards for testing...
Microelectronic components are commonly tested with probe cards. Certain aspects of probes, probe cards, and methods of testing microelectronic components are...
US-7,170,184 Treatment of a ground semiconductor die to improve adhesive bonding to a substrate
Methods are provided to improve the adhesive bonding of a semiconductor die to a substrate through an adhesive paste by forming a layer of silicon dioxide on the...
US-7,170,174 Contact structure and contact liner process
A contact structure and a method of forming thereof for semiconductor devices or assemblies are described. The method provides process steps to create a contact...
US-7,170,171 Support ring for use with a contact pad and semiconductor device components including the same
Dielectric rings are configured to be disposed around contact pads on a surface of a semiconductor device or another substrate. The rings may be fabricated or...
US-7,170,161 In-process semiconductor packages with leadframe grid arrays
Methods of forming a semiconductor assembly are described which include a leadframe with leads having offset portions exposed at an outer surface of a material...
US-7,170,139 Semiconductor constructions
A semiconductor processing method of forming a conductive gate or gate line over a substrate includes, a) forming a conductive gate over a gate dielectric layer...
US-7,170,124 Trench buried bit line memory devices and methods thereof
A memory device includes isolation trenches that are formed generally parallel to and along associated strips of active area. A conductive bit line is recessed...
US-7,170,123 Antiferromagnetically stabilized pseudo spin valve for memory applications
The invention relates to improving the switching reliability of a magnetic memory cell in a magnetic random access memory (MRAM). Embodiments of the invention...
US-7,170,117 Image sensor with improved dynamic range and method of formation
Embodiments of the invention provide an image sensor having an improved dynamic range. A pixel cell comprises at least one transistor structure. The transistor...
US-7,170,103 Wafer with vertical diode structures
A method of making a vertical diode is provided, the vertical diode having associated therewith a diode opening extending through an insulation layer and...
US-7,170,091 Probe look ahead: testing parts not currently under a probehead
A semiconductor substrate, probe card, and methods for stressing and testing dies on a semiconductor substrate are provided. The semiconductor substrate,...
US-7,169,693 Collar positionable about a periphery of a contact pad and around a conductive structure secured to the contact...
Dielectric collars to be disposed around contact pads on a surface of a semiconductor device or another substrate and methods of fabricating and disposing the...
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