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Patent # Description
US-7,205,229 Interconnect alloys and methods and apparatus using same
Integrated circuit interconnect alloys having copper, silver or gold as the major constituent element. The resulting reduction in melting temperature allows for...
US-7,205,227 Methods of forming CMOS constructions
The invention includes methods for forming electrical connections associated with semiconductor constructions. A semiconductor substrate is provided which has a...
US-7,205,223 Method of forming an interconnect structure for a semiconductor device
A copper interconnect structure is disclosed as comprising a copper layer and an aluminum nitride layer formed over the copper layer. The aluminum nitride layer...
US-7,205,221 Under bump metallization pad and solder bump connections
The present invention relates to an improved method of forming and structure for under bump metallurgy ("UBM") pads for a flip chip which reduces the number of...
US-7,205,218 Method including forming gate dielectrics having multiple lanthanide oxide layers
A dielectric film having a layer of a lanthanide oxide and a layer of another lanthanide oxide, and a method of fabricating such a dielectric film produce a...
US-7,204,889 Method of reducing water spotting and oxide growth on a semiconductor structure
The present invention relates to a method of cleaning and drying a semiconductor structure in a modified conventional gas etch/rinse or dryer vessel.
US-7,204,885 Deposition system to provide preheating of chemical vapor deposition precursors
Chemical vapor deposition systems include elements to preheat reactant gases prior to reacting the gases to form layers of a material on a substrate, which...
US-7,203,874 Error detection, documentation, and correction in a flash memory device
A memory device has an error documentation memory array that is separate from the primary memory array. The error documentation memory array stores data relating...
US-7,203,124 System and method for negative word line driver circuit
A negative word line driver employs devices to maintain the potential difference between the active word line signal and the inactive word line signal while...
US-7,203,122 User selectable banks for DRAM
A memory device includes a configurable array of memory cells. A number of array banks is configured based upon data stored in a mode register or decoded by...
US-7,203,098 Methods of erasing flash memory
Methods for erasing flash memory using a decrease in magnitude of a source voltage of a first polarity to increase the magnitude of a control gate voltage of a...
US-7,203,093 Method and apparatus for reading NAND flash memory array
The method for reading/verifying a NAND flash memory device alternates the select gate biasing in response to the position of the cell to be read. If the cell is...
US-7,203,092 Flash memory array using adjacent bit line as source
A memory array having a plurality of flash memory cells arranged in rows and columns. A plurality of bit lines couple the columns such that alternate bit lines...
US-7,203,083 Longest match detection in a CAM
An apparatus and method for a CAM priority match detection circuit that identifies one or more CAM words from a group of CAM words having a "longest match" that...
US-7,202,894 Method and apparatus for real time identification and correction of pixel defects for image sensor arrays
An image processing system and method compares each pixel of an image obtained from an image sensor array with at least eight surrounding pixels of the same...
US-7,202,739 CMOS amplifiers with frequency compensating capacitors
The frequency and transient responses of a CMOS differential amplifier are improved by employing one or more compensating capacitors. A compensating capacitor...
US-7,202,681 Motherboard memory slot ribbon cable and apparatus
A testing apparatus, system and method for testing computer memory modules are disclosed. The apparatus includes a motherboard having a processor and at least...
US-7,202,562 Integrated circuit cooling system and method
A system and method for cooling an integrated circuit is provided. One aspect of this disclosure relates to a cooling system that utilizes sound waves to cool a...
US-7,202,556 Semiconductor package having substrate with multi-layer metal bumps
A semiconductor package includes a substrate formed of a board material, a semiconductor die bonded to the substrate, and an encapsulant on the die. The package...
US-7,202,543 Method and structure to reduce optical crosstalk in a solid state imager
Methods and structures to reduce optical crosstalk in solid state imager arrays. Sections of pixel material layers that previously would have been etched away...
US-7,202,530 Micro-mechanically strained semiconductor film
One aspect of the present subject matter relates to a method for forming strained semiconductor film. In various embodiments, a single crystalline semiconductor...
US-7,202,523 NROM flash memory devices on ultrathin silicon
An NROM flash memory cell is implemented in an ultra-thin silicon-on-insulator structure. In a planar device, the channel between the source/drain areas is...
US-7,202,520 Multiple data state memory cell
A programmable multiple data state memory cell including a first electrode layer formed from a first conductive material, a second electrode layer formed from a...
US-7,202,519 Memory cells having an access transistor with a source/drain region coupled to a capacitor through an extension
Fabrication of memory cell capacitors in an over/under configuration facilitates increased capacitance values for a given die area. A pair of memory cells...
US-7,202,183 Method of filling gaps and methods of depositing materials using high density plasma chemical vapor deposition
The invention includes a method of filling gaps in a semiconductor substrate. A substrate and a gas mixture containing at least one heavy-hydrogen compound are...
US-7,202,171 Method for forming a contact opening in a semiconductor device
A method of forming a self-aligned contact opening in an insulative layer formed over a substrate in a semiconductor device involves etching the insulative layer...
US-7,202,138 Spin coating for maximum fill characteristic yielding a planarized thin film surface
A method for spinning a material onto a semiconductor device structure so as to substantially fill recesses formed in a surface of the semiconductor device...
US-7,202,129 Source lines for NAND memory devices
A source line is formed by forming a source slot in a bulk insulation layer overlying a substrate to expose a portion of a substrate within the source slot,...
US-7,202,127 Methods of forming a plurality of capacitors
A plurality of capacitor electrode openings is formed within capacitor electrode-forming material. A first set of the openings is formed to a depth which is...
US-7,202,104 Co-sputter deposition of metal-doped chalcogenides
The present invention is related to methods and apparatus that allow a chalcogenide glass such as germanium selenide (Ge.sub.xSe.sub.1-x) to be doped with a...
US-7,202,098 Method and structure to reduce optical crosstalk in a solid state imager
Methods and structures to reduce optical crosstalk in solid state imager arrays. Sections of pixel material layers that previously would have been etched away...
US-7,201,635 Methods and systems for conditioning planarizing pads used in planarizing substrates
Monitoring the process of planarizing a workpiece, e.g., conditioning a CMP pad, can present some difficulties. Aspects of this invention provide methods and...
US-7,201,632 In-situ chemical-mechanical planarization pad metrology using ultrasonic imaging
Chemical-mechanical planarization (CMP) apparatus and methods for detecting polishing pad properties using ultrasonic imaging is presented. An ultrasonic probe...
US-7,201,304 Multi-functional solder and articles made therewith, such as microelectronic components
Aspects of the invention provide solder compositions which include two different fluxing agents. One of the fluxing agents promotes melting of a metal of the...
US-7,200,950 Process for monitoring measuring device performance
The disclosed embodiments relate to calibrating a measuring device by comparing a set of master measurement data against a set of current measurement data....
US-7,200,738 Reducing data hazards in pipelined processors to provide high processor utilization
A pipelined computer processor is presented that reduces data hazards such that high processor utilization is attained. The processor restructures a set of...
US-7,200,736 Method and system for substantially registerless processing
A simple instruction set processor preferably utilizes six primary components: a fetch unit, and instruction and address register, a controller/decoder, an...
US-7,200,693 Memory system and method having unidirectional data buses
A memory system and method includes a unidirectional downstream bus coupling write data from a memory controller to several memory devices, and a unidirectional...
US-7,200,063 Circuitry for a programmable element
As part of anti-fuse circuitry for a memory device, a preferred exemplary embodiment of the current invention provides a direct connection between an anti-fuse...
US-7,200,062 Method and system for reducing the peak current in refreshing dynamic random access memory devices
A dynamic random access memory device includes a mode register that is programmed with a delay value. In some embodiments, a offset code is also stored in the...
US-7,200,053 Level shifter for low voltage operation
A voltage level translator boosts the gate voltage of a transistor, and increases the gate to source voltage, to allow operation over a wider range of supply...
US-7,200,052 Apparatus and methods for regulated voltage
An electronic system according to various aspects of the present invention includes a memory and a supply regulation circuit having a regulated output to provide...
US-7,200,048 Flash memory
Flash memory supporting methods for erasing memory cells using a decrease in magnitude of a source voltage of a first polarity to increase the magnitude of a...
US-7,200,047 High voltage positive and negative two-phase discharge system and method for channel erase in flash memory devices
An erase discharge circuit in a flash memory is coupled to an array source and a p-well drive and receives first and second discharge signals. The erase...
US-7,200,046 Low power NROM memory devices
A buried bipolar junction is provided in a charge trapping transistor memory device. During a write operation electrons are injected into a surface depletion...
US-7,200,041 Sensing scheme for low-voltage flash memory
Single-ended sensing devices for sensing a programmed state of a floating-gate memory cell are adapted for use in low-voltage memory devices. The sensing device...
US-7,200,035 Magneto-resistive memory cell structures with improved selectivity
A magneto-resistive memory comprising magneto-resistive memory cells is disclosed, comprising two pinned magnetic layers on one side of a free magnetic layer....
US-7,200,024 System and method for optically interconnecting memory devices
A memory device includes a semiconductor substrate in which memory circuitry has been fabricated. An address converter and a control signal converter are coupled...
US-7,200,022 Apparatus and method for mounting microelectronic devices on a mirrored board assembly
The present invention is directed to a system, a module, and an apparatus and method for forming a microelectronic memory device. In one embodiment, a system...
US-7,199,931 Gapless microlens array and method of fabrication
A microlens array with reduced or no empty space between individual microlenses and a method for forming the same. The microlens array is formed by patterning a...
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