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Patent # Description
US-7,166,509 Write once read only memory with large work function floating gates
Structures and methods for write once read only memory employing floating gates are provided. The write once read only memory cell includes a floating gate...
US-7,166,495 Method of fabricating a multi-die semiconductor package assembly
An apparatus and method for increasing integrated circuit density comprising an upper die and a lower die, the latter preferably a flip chip, which are connected...
US-7,166,479 Methods of forming magnetic shielding for a thin-film memory element
A monolithically formed ferromagnetic thin-film memory is disclosed that has local shielding on at least two sides of selected magnetic storage elements. The...
US-7,166,252 Method for reducing warpage during application and curing of encapsulant materials on a printed circuit board
A method and apparatus for preventing board warpage during the application and curing or drying of liquid epoxies, or the like, on printed circuit boards using a...
US-7,166,247 Foamed mechanical planarization pads made with supercritical fluid
Foamed thermoplastic polymeric mechanical planarization polishing pads ("MP pads") made with supercritical fluids are presented. A supercritical fluid foaming...
US-7,165,975 Electrical connecting apparatus
An electrical connecting apparatus is characterized by inserting a first pin having a flange portion into a through hole of an elastic body via a seat, by...
US-7,165,322 Process of forming socket contacts
A socket contact formation process comprises forming a contact head from a conductive material, forming a contact body from a semiconductive material configured...
US-7,165,185 DDR II write data capture calibration
A calibration circuit for calibrating the input data path of a digital circuit is disclosed. A simple string of a repeating data pattern such as, e.g., "1100,"...
US-7,165,143 System and method for manipulating cache data
A processing system optimized for data string manipulations includes data string execution circuitry associated with a bus interface unit or memory controller....
US-7,165,004 Dynamically adaptable semiconductor parametric testing
An apparatus, method, system, and signal-bearing medium may provide multiple maps, which may include multiple probing sequences to be called upon at run-time...
US-7,164,611 Data retention kill function
A secure memory device that is configured to prevent unauthorized access of data is disclosed. More specifically, a kill function logic device is capable of...
US-7,164,607 Dual bus memory burst architecture
Methods and apparatus for a memory device including a burst architecture employ a double bus architecture that is multiplexed onto an output bus. The resulting...
US-7,164,597 Computer systems
A two-transistor SRAM cell includes a first FET. The first FET is an ultrathin FET of a first polarity type and includes a control electrode, a first load...
US-7,164,595 Device and method for using dynamic cell plate sensing in a DRAM memory cell
A memory cell, device, system and method for operating a memory cell are disclosed that utilize an isolated dynamic cell plate. The memory cell includes a first...
US-7,164,294 Method for forming programmable logic arrays using vertical gate transistors
One aspect disclosed herein relates to a method for forming a programmable logic array. Various embodiments of the method include forming a first logic plane and...
US-7,164,260 Bandgap reference circuit with a shared resistive network
A CMOS bandgap reference (BGR) voltage generator circuit has a passive resistor T-network of low resistance connected between the inverting and non-inverting...
US-7,164,188 Buried conductor patterns formed by surface transformation of empty spaces in solid state materials
A plurality of buried conductors and/or buried plate patterns formed within a monocrystalline substrate is disclosed. A plurality of empty-spaced buried patterns...
US-7,164,182 Pixel with strained silicon layer for improving carrier mobility and blue response in imagers
An imager having a pixel cell having an associated strained silicon layer. The strained silicon layer increases charge transfer efficiency, decreases image lag,...
US-7,164,168 Non-planar flash memory having shielding between floating gates
A first plurality of memory cells is formed on pillars in a first column of the array. A second plurality of memory cells is formed in a first set of trenches in...
US-7,164,165 MIS capacitor
An MIS capacitor with low leakage and high capacitance is disclosed. A layer of hemispherical grained polysilicon (HSG) is formed as a lower electrode. Prior to...
US-7,164,161 Method of formation of dual gate structure for imagers
A device, as in an integrated circuit, includes diverse components such as transistors and capacitors. After conductive layers for all types of components are...
US-7,164,156 Electronic systems using optical waveguide interconnects formed throught a semiconductor wafer
An integrated circuit with a number of optical waveguides that are formed in high aspect ratio holes. The high aspect ratio holes extend through a semiconductor...
US-7,163,893 Advanced barrier liner formation for vias
A high integrity, reliable liner is disclosed for a via in which a titanium aluminide layer is preformed as a lining within a via hole prior to deposition of...
US-7,163,845 Internal package heat dissipator
A technique is provided for dissipating heat from an integrated circuit within a package. A thermally conductive strip may be disposed adjacent to an integrated...
US-7,163,837 Method of forming a resistance variable memory element
A method for controlling silver doping of a chalcogenide glass in a resistance variable memory element is disclosed herein. The method includes forming a silver...
US-7,163,641 Method of forming high aspect ratio apertures
A plasma etch process for etching BPSG employing two primary etchants at low flows and pressures, and a relatively low temperature environment within the etch...
US-7,163,447 Apparatus and method for conditioning a contact surface of a processing pad used in processing microelectronic...
Conditioning devices, systems and methods for conditioning a contact surface of a processing pad used in processing microelectronic workpieces. One embodiment of...
US-7,163,439 Methods and systems for conditioning planarizing pads used in planarizing substrates
Monitoring the process of planarizing a workpiece, e.g., conditioning a CMP pad, can present some difficulties. Aspects of this invention provide methods and...
US-7,163,019 Method of reducing water spotting and oxide growth on a semiconductor structure
The present invention relates to a method of cleaning and drying a semiconductor structure in a modified conventional gas etch/rinse or dryer vessel. In an...
US-7,163,017 Polysilicon etch useful during the manufacture of a semiconductor device
A method for etching a polysilicon layer comprises the steps of providing a semiconductor wafer substrate assembly having at least first and second features...
US-7,162,796 Method of making an interposer with contact structures
A method of making an interposer having an array of contact structures for making temporary electrical contact with the leads of a chip package. The contact...
US-7,162,744 Connected support entitlement system and method of operation
An entitlement system and method for computers allowing controlled access to operating systems, software applications, data, or hardware for a computer system....
US-7,162,668 Memory with element redundancy
A memory device to perform an erase operation algorithm that specifically deals with different types of defects in a memory array. The memory array of one...
US-7,162,606 Multiple segment data object management
A multiple segment data structure and method manage data objects stored in multiple segments. The structure and method use one or more multiple segment index...
US-7,162,592 Method for bus capacitance reduction
Data bus capacitance is reduced by decoupling unaccessed memory circuits from a data bus during data transfers to or from other memory circuits.
US-7,162,570 Flash memory programming
The various embodiments provide for programming floating-gate, or flash, memory devices by writing a block of data words to a volatile storage media from an...
US-7,162,567 Memory hub and method for memory sequencing
A memory module includes a memory hub coupled to several memory devices. The memory hub includes at least one performance counter that tracks one or more system...
US-7,162,386 Dynamically adaptable semiconductor parametric testing
An apparatus, method, system, and signal-bearing medium may provide multiple maps, which may include multiple probing sequences to be called upon at run-time...
US-7,161,870 Synchronous flash memory command sequence
A computer system comprises a memory controller and a synchronous non-volatile memory device coupled to the memory controller via a main memory bus. The...
US-7,161,866 Memory device tester and method for testing reduced power states
A memory device tester capable of testing for proper operation of reduced power states in memory devices. The memory device tester can include a processor or a...
US-7,161,857 Memory redundancy programming
A method and apparatus is provided for performing a redundancy programming. The system of the present invention includes a device testing unit for performing a...
US-7,161,821 Apparatus and method for mounting microelectronic devices on a mirrored board assembly
The present invention is directed to a system, a module, and an apparatus and method for forming a microelectronic memory device. In one embodiment, a system...
US-7,161,394 Digital phase mixers with enhanced speed
Digital phase mixers with enhanced speed are provided. A phase mixer generates a signal having a phase between the phases of two input signals based on select...
US-7,161,391 Skew tolerant high-speed digital phase detector
A skew-tolerant digital phase detector is provided. Specifically, a detector is provided in the digital phase detector to detect certain failure conditions that...
US-7,161,376 Variable impedence output buffer
An output buffer for a semiconductor memory device and other semiconductor devices includes a feedback circuit to dynamically control the output impedance of the...
US-7,161,373 Method for testing using a universal wafer carrier for wafer level die burn-in
A reusable burn-in/test fixture for testing unsingulated dice on a semiconductor wafer consisting of two halves. The first half of the test fixture is a wafer...
US-7,161,372 Input system for an operations circuit
An integrated device includes a redundant bond pad for accessing internal circuitry in the event that the main bond pad for that circuitry is difficult to access...
US-7,161,250 Projected contact structures for engaging bumped semiconductor devices and methods of making the same
A bumped semiconductor device contact structure is disclosed including at least one non-planar contact pad having a plurality of projections extending therefrom...
US-7,161,246 Interconnect alloys and methods and apparatus using same
Integrated circuit interconnect alloys having copper, silver or gold as the major constituent element. The resulting reduction in melting temperature allows for...
US-7,161,237 Flip chip packaging using recessed interposer terminals
A method and apparatus for packaging a semiconductor die with an interposer substrate. The semiconductor device assembly includes a conductively bumped...
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