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Patent # Description
US-7,173,874 Compact decode and multiplexing circuitry for a multi-port memory having a common memory interface
A memory array for a multi-port memory having a common memory interface and a plurality of memory ports through which the memory array is accessed is provided....
US-7,173,869 Regulating voltages in semiconductor devices
The present invention provides a method and apparatus for regulating voltages in semiconductor devices. The method and apparatus includes providing a first...
US-7,173,856 Sense amplifier for a non-volatile memory device
The memory device has a plurality of memory cells each coupled to a bitline. A feedback transistor is coupled to the bitline and provides voltage feedback on the...
US-7,173,855 Current limiting antifuse programming path
Method and apparatus are disclosed for regulating an antifuse programming current by lightly doping an electrically connected region so that the resistance of...
US-7,173,463 Generating multi-phase clock signals using hierarchical delays
Circuits and methods for generating multi-phase clock signals using digitally-controlled hierarchical delay units (HDs) are provided. A plurality of...
US-7,173,339 Semiconductor device having a substrate an undoped silicon oxide structure and an overlaying doped silicon...
An etchant including C.sub.2H.sub.xF.sub.y, where x is an integer from two to five, inclusive, where y is an integer from one to four, inclusive, and where x...
US-7,173,330 Multiple chip semiconductor package
A semiconductor device package and method of fabricating the same. The semiconductor device package may include a variety of semiconductor dice, thereby...
US-7,173,317 Electrical and thermal contact for use in semiconductor devices
An electrical and thermal contact for use in a semiconductor device. The electrical and thermal contact includes an intermediate conductive layer, an insulator...
US-7,173,304 Method of manufacturing devices comprising conductive nano-dots, and devices comprising same
A method is disclosed that may include forming a first layer of insulating material above a semiconducting substrate, forming an aluminum oxide layer above the...
US-7,172,949 Epitaxial semiconductor layer and method
A method for epitaxially forming a first semiconductor structure attached to a second semiconductor structure is provided. Devices and methods described include...
US-7,172,947 High dielectric constant transition metal oxide materials
A transition metal oxide dielectric material is doped with a non-metal in order to enhance the electrical properties of the metal oxide. In a preferred...
US-7,172,491 Apparatus and method for conditioning and monitoring media used for chemical-mechanical planarization
A method and apparatus for conditioning and monitoring a planarizing medium used for planarizing a microelectronic substrate. In one embodiment, the apparatus...
US-7,172,465 Edge connector including internal layer contact, printed circuit board and electronic module incorporating same
An edge connector, system, printed circuit board and electronic module are described, which include an edge connector comprised of a substrate, including a first...
US-7,171,642 Method and system for creating a netlist allowing current measurement through a sub-circuit
A system and method for manipulating a netlist, at the time that the netlist is being created, to permit measurement of current flow through a net, or...
US-7,171,508 Dual port memory with asymmetric inputs and outputs, device, system and method
An asymmetric memory interface including an asymmetric read data interface having a read bus width configured to transfer data from a memory device to a memory...
US-7,170,867 Radio frequency data communications device
A radio frequency identification device includes an integrated circuit including a receiver, a transmitter, and a microprocessor. The receiver and transmitter...
US-7,170,806 Data path having grounded precharge operation and test compression capability
A data path for coupling data between a memory cell and an input/output (IO) line sense amplifier. An IO line coupling circuit is coupled to a pair of global...
US-7,170,783 Layout for NAND flash memory array having reduced word line impedance
A memory array including a first region in which a first memory sub-array is located and a second region separated from the first region in which a second memory...
US-7,170,361 Method and apparatus of interposing voltage reference traces between signal traces in semiconductor devices
A method and apparatus for substantially reducing or eliminating electromagnetic and electrostatic coupling between signal traces on a substrate is disclosed. A...
US-7,170,304 Selectively configurable probe structures, e.g., selectively configurable probe cards for testing...
Microelectronic components are commonly tested with probe cards. Certain aspects of probes, probe cards, and methods of testing microelectronic components are...
US-7,170,184 Treatment of a ground semiconductor die to improve adhesive bonding to a substrate
Methods are provided to improve the adhesive bonding of a semiconductor die to a substrate through an adhesive paste by forming a layer of silicon dioxide on the...
US-7,170,174 Contact structure and contact liner process
A contact structure and a method of forming thereof for semiconductor devices or assemblies are described. The method provides process steps to create a contact...
US-7,170,171 Support ring for use with a contact pad and semiconductor device components including the same
Dielectric rings are configured to be disposed around contact pads on a surface of a semiconductor device or another substrate. The rings may be fabricated or...
US-7,170,161 In-process semiconductor packages with leadframe grid arrays
Methods of forming a semiconductor assembly are described which include a leadframe with leads having offset portions exposed at an outer surface of a material...
US-7,170,139 Semiconductor constructions
A semiconductor processing method of forming a conductive gate or gate line over a substrate includes, a) forming a conductive gate over a gate dielectric layer...
US-7,170,124 Trench buried bit line memory devices and methods thereof
A memory device includes isolation trenches that are formed generally parallel to and along associated strips of active area. A conductive bit line is recessed...
US-7,170,123 Antiferromagnetically stabilized pseudo spin valve for memory applications
The invention relates to improving the switching reliability of a magnetic memory cell in a magnetic random access memory (MRAM). Embodiments of the invention...
US-7,170,117 Image sensor with improved dynamic range and method of formation
Embodiments of the invention provide an image sensor having an improved dynamic range. A pixel cell comprises at least one transistor structure. The transistor...
US-7,170,103 Wafer with vertical diode structures
A method of making a vertical diode is provided, the vertical diode having associated therewith a diode opening extending through an insulation layer and...
US-7,170,091 Probe look ahead: testing parts not currently under a probehead
A semiconductor substrate, probe card, and methods for stressing and testing dies on a semiconductor substrate are provided. The semiconductor substrate,...
US-7,169,693 Collar positionable about a periphery of a contact pad and around a conductive structure secured to the contact...
Dielectric collars to be disposed around contact pads on a surface of a semiconductor device or another substrate and methods of fabricating and disposing the...
US-7,169,691 Method of fabricating wafer-level packaging with sidewall passivation and related apparatus
A method of fabricating a chip-scale or wafer-level package having passivation layers on substantially all surfaces thereof to form a hermetically sealed...
US-7,169,685 Wafer back side coating to balance stress from passivation layer on front of wafer and be used as die attach...
A method for balancing layer-caused compressive or tensile stress in a semiconductor die, die wafer or similar substrate uses a stress-balancing layer (SBL)...
US-7,169,673 Atomic layer deposited nanolaminates of HfO.sub.2/ZrO.sub.2 films as gate dielectrics
A dielectric film containing HfO.sub.2/ZrO.sub.2 nanolaminates and a method of fabricating such a dielectric film produce a reliable gate dielectric having an...
US-7,169,666 Method of forming a device having a gate with a selected electron affinity
A floating gate transistor has a reduced barrier energy at an interface with an adjacent gate insulator, allowing faster charge transfer across the gate...
US-7,169,662 Methods for making semiconductor structures having high-speed areas and high-density areas
Methods for making a semiconductor structure are discussed. The methods include forming openings in a high-density area and a high-speed area, and forming a...
US-7,169,645 Methods of fabrication of package assemblies for optically interactive electronic devices
Packaging assemblies for optically interactive devices and methods of forming the packaging assemblies in an efficient manner that eliminates or reduces the...
US-7,169,545 Resist exposure system and method of forming a pattern on a resist
A resist exposure system and a method of forming a pattern on a resist are provided and include an exposure source, a photoresist composition, and a mask...
US-7,169,248 Methods for releasably attaching support members to microfeature workpieces and microfeature assemblies formed...
Methods for releasably attaching support members to microfeature workpieces and microfeature assemblies formed using such methods. A method for processing a...
US-7,169,014 Apparatuses for controlling the temperature of polishing pads used in planarizing micro-device workpieces
Temperature regulation systems and methods for controlling the temperature of polishing pads used in planarizing micro-device workpieces are disclosed herein. In...
US-7,168,163 Full wafer silicon probe card for burn-in and testing and test system including same
A full-wafer probe card is disclosed along with related methods and systems. The probe card includes test probes comprising cantilever elements configured and...
US-7,168,027 Dynamic synchronization of data capture on an optical or other high speed communications link
A method and system that dynamically adjusts link control parameters of a communications network. The communications network includes a transmitter coupled...
US-7,168,018 Apparatus and method for reducing test resources in testing DRAMs
An apparatus and a method are disclosed for reducing the pin driver count required for testing computer memory devices, specifically Rambus DRAM, while a die is...
US-7,168,013 Memory with element redundancy
A memory device to perform an erase operation algorithm that specifically deals with different types of defects in a memory array. The memory array of one...
US-7,167,408 Circuitry for a programmable element
As part of anti-fuse circuitry for a memory device, a preferred exemplary embodiment of the current invention provides a direct connection between an anti-fuse...
US-7,167,401 Low power chip select (CS) latency option
A system and method to reduce standby currents in input buffers in an electronic device (e.g., a memory device) is disclosed. The input buffers may be activated...
US-7,167,400 Apparatus and method for improving dynamic refresh in a memory device
An apparatus and method for generating a control pulse for closing an active wordline in a memory device is provided. A timeout generator circuit having a time...
US-7,167,399 Flash memory device with a variable erase pulse
A method of operating a flash memory device according to an embodiment of the present invention includes selecting a flash cell in a flash memory device to...
US-7,167,396 Erase verify for nonvolatile memory using reference current-to-voltage converters
A memory device verify system determines a state of memory cells in a memory. The memory includes a memory array having a plurality of memory cells coupled to...
US-7,167,231 Method and apparatus for printing large data flows
An aspect of the present invention includes a method for patterning a workpiece covered at least partly with a layer sensitive to electromagnetic radiation,...
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