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Input buffer with automatic switching point adjustment circuitry, and
synchronous dram device including same
An input buffer is presented for buffering an input signal having a voltage magnitude which alternates between a first voltage level and a second voltage level,...
A floating gate transistor has a reduced barrier energy at an interface with an adjacent gate insulator, allowing faster charge transfer across the gate...
Dielectric plug in mosfets to suppress short-channel effects
The invention provides a technique to fabricate a dielectric plug in a MOSFET. The invention includes apparatus and systems that include one or more devices...
Write once read only memory with large work function floating gates
Structures and methods for write once read only memory employing floating gates are provided. The write once read only memory cell includes a floating gate...
Isolation structures for preventing photons and carriers from reaching
active areas and methods of formation
Regions of an integrated circuit are isolated by a structure that includes at least one isolating trench on the periphery of an active area. The trench is deep,...
Differential column readout scheme for CMOS APS pixels
The present invention provides an improved column readout circuitry and method of operation which minimizes substrate and other common mode noise during a read...
Method and apparatus for pixel signal binning and interpolation in column
circuits of a sensor circuit
A binning circuit and related method, wherein pixel signals from column circuits in a sensor circuit are sampled and interpolated. The binning circuit samples...
Method and apparatus for attaching a workpiece to a workpiece support
A method for attaching a workpiece, for example a semiconductor die, to a workpiece holder, for example a lead frame die support, comprises the steps of...
Method to eliminate striations and surface roughness caused by dry etch
A plasma etch process for forming a high aspect ratio contact opening through a silicon oxide layer is disclosed. The silicon oxide layer is plasma etched using...
Methods of forming openings, and methods of forming container capacitors
A patterned mask can be formed as follows. A first patterned photoresist is formed over a masking layer and utilized during a first etch into the masking layer....
Methods and apparatuses for electrochemical-mechanical polishing
Methods and apparatuses for removing material from a microfeature workpiece are disclosed. In one embodiment, the microfeature workpiece is contacted with a...
Conductive material patterning methods
A patterning method includes providing a first material (e.g., copper) and transforming at a least a surface region of the first material to a second material...
Methods of forming a reaction product and methods of forming a conductive
metal silicide by reaction of metal...
A method of forming a reaction product includes providing a semiconductor substrate comprising a first material. A second material is formed over the first...
Methods for forming porous insulators from "void" creating materials and
structures and semiconductor devices...
Methods for forming porous insulative materials for use in forming dielectric structures of semiconductor devices are disclosed. Each insulative material may...
Strained Si/SiGe/SOI islands and processes of making same
A process of making a strained silicon-on-insulator structure is disclosed. A recess is formed in a substrate to laterally isolate an active area. An...
Method of forming a capacitor
The invention includes a method of forming a semiconductor construction. A semiconductor substrate is provided, and a conductive node is formed to be supported...
Capacitors, methods of forming capacitors, and methods of forming
capacitor dielectric layers
A method of forming a capacitor includes forming first and second capacitor electrodes over a substrate. A capacitor dielectric region is formed intermediate the...
Use of selective epitaxial silicon growth in formation of floating gates
Methods and apparatus utilizing epitaxial silicon growth on a base structure of a floating gate of a floating-gate memory cell to increase the available coupling...
Methods of forming capacitors and methods of forming capacitor dielectric
A method of forming a capacitor includes forming first capacitor electrode material over a semiconductor substrate. A silicon nitride comprising layer is formed...
Method of forming a field effect transistor with halo implant regions
A method of forming a field effect transistor includes forming a channel region within bulk semiconductive material of a semiconductor substrate. Source/drain...
Resistance variable memory elements based on polarized silver-selenide
The invention relates to a resistance variable memory element including polarizable metal-chalcogen regions within a doped chalcogenide glass. A method for...
Method of fabricating a storage gate pixel design
A method of fabricating a pixel cell having a shutter gate structure. First and second charge barriers are respectively created between a photodiode and a first...
Method for forming a storage cell capacitor compatible with high
dielectric constant materials
An integrated circuit structure includes a digit line and an electrode adapted to be part of a storage cell capacitor and includes a barrier layer interposed...
Dual layer workpiece masking and manufacturing process
The status of a plurality of service orders is summarized. A first data set that includes a plurality of records corresponding to service orders, such as...
Methods and apparatus for electrochemical-mechanical processing of
Methods and apparatuses for electrochemical-mechanical processing of microelectronic workpieces. One embodiment of an electrochemical processing apparatus in...
Methods and apparatus for selectively removing conductive material from a
Methods and apparatuses for selectively removing conductive materials from a microelectronic substrate. A method in accordance with an embodiment of the...
Polishing liquids for activating and/or conditioning fixed abrasive
polishing pads, and associated systems and...
Polishing liquids for activating and/or conditioning fixed abrasive polishing pads, and associated systems and methods are disclosed. A method in accordance with...
Method and apparatus for forming modular sockets using flexible
interconnects and resulting structures
A modular bare die socket assembly is provided for attaching a plurality of miniature semiconductor dice to a substrate. The socket assembly is comprised of a...
Integrated semiconductor memory chip with presence detect data capability
An integrated semiconductor memory chip includes hardwired presence detect data which can be accessed for transmission to a location external to the memory chip...
Obtaining search results for content addressable memory
Content addressable memory (CAM) in which search results such as an address code and an array match signal can be obtained for multiple search widths. The CAM...
Techniques for generating serial presence detect contents
Techniques are presented for automatically generating Serial Presence Detect (SPD) contents. Standards for specific values associated with SPD contents are...
Distributed configuration storage
Systems and methods for providing distributed configuration storage are presented. The configuration storage is divided into distributed configuration target...
Memory device and method having programmable address configurations
A memory device includes a configurable address register having a first set of input buffers coupled to a first set on address bus terminals and a second set of...
Memory device and method having data path with multiple prefetch I/O
A memory device is operable in either a high mode or a low speed mode. In either mode, 32 bits of data from each of two memory arrays are prefetched into...
Reducing DQ pin capacitance in a memory device
A system and method to operate an electronic device, such as a memory chip, with a data driver circuit that is configured to reduce data pin (DQ) capacitance ....
Integrated charge sensing scheme for resistive memories
An integrated charge sensing scheme for sensing the resistance of a resistive memory element is described. The current through a resistive memory cell is used to...
6F.sup.2 3-Transistor DRAM gain cell
A high density vertical three transistor memory cell is provided. The high density vertical three transistor memory cell is formed in a vertical pillar. The...
Adjusting the frequency of an oscillator for use in a resistive sense amp
A system and methods optimize the operation of sensing circuitry. In one embodiment, the output of a sensing circuit is stored in a register and processed...
Sensing of resistance variable memory devices
A resistance variable memory device such as e.g., a PCRAM memory device, with either a 4T (transistor) or 2T memory cell configuration and either a dual cell...
In a semiconductor device, a capacitor is provided which has a gap in at least one of its plates. The gap is small enough so that fringe capacitance between the...
Resampling system and method for graphics data including sine-wave
A method and system for calculating resample output values from input samples and their associated sample values. A resampling circuit calculates a frequency...
Minimized differential SAR-type column-wide ADC for CMOS image sensors
An analog-to-digital converter comprising a minimal amount of circuitry for conversion of an input analog signal to a series of digital bits. A differential...
Reference voltage stabilization in CMOS sensors
A reference voltage generator for use in an image sensor provides a reference voltage to an S/H block during a pixel read-out operation and another reference...
Fully-depleted (FD) (SOI) MOSFET access transistor
A fully-depleted (FD) Silicon-on-Insulator (SOI) MOSFET access transistor comprising a gate electrode of a conductivity type which is opposite the conductivity...
High density stepped, non-planar flash memory
A first plurality of memory cells is in a first plane in a first column of the array. A second plurality of memory cells is in a second plane in the same column....
Capacitor structures, DRAM cell structures, and integrated circuitry, and
methods of forming capacitor...
The invention encompasses DRAM constructions, capacitor constructions, integrated circuitry, and methods of forming DRAM constructions, integrated circuitry and...
Transistor structures and transistors with a germanium-containing channel
A transistor structure includes a first undoped, silicon-containing channel layer, a buried germanium channel, and a second undoped, silicon-containing channel...
Silver-selenide/chalcogenide glass stack for resistance variable memory
The invention is related to methods and apparatus for providing a resistance variable memory element with improved data retention and switching characteristics....
Method and apparatus for forming a planarizing pad having a film and
texture elements for planarization of...
A planarizing pad for planarizing a microelectronic substrate, and a method and apparatus for forming the planarizing pad. In one embodiment, planarizing pad...
Semiconductor processing methods of forming and utilizing antireflective
material layers, and methods of...
In one aspect, the invention includes a semiconductor processing method comprising exposing silicon, nitrogen and oxygen in gaseous form to a high density plasma...