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Patent # Description
US-7,164,294 Method for forming programmable logic arrays using vertical gate transistors
One aspect disclosed herein relates to a method for forming a programmable logic array. Various embodiments of the method include forming a first logic plane and...
US-7,164,260 Bandgap reference circuit with a shared resistive network
A CMOS bandgap reference (BGR) voltage generator circuit has a passive resistor T-network of low resistance connected between the inverting and non-inverting...
US-7,164,188 Buried conductor patterns formed by surface transformation of empty spaces in solid state materials
A plurality of buried conductors and/or buried plate patterns formed within a monocrystalline substrate is disclosed. A plurality of empty-spaced buried patterns...
US-7,164,182 Pixel with strained silicon layer for improving carrier mobility and blue response in imagers
An imager having a pixel cell having an associated strained silicon layer. The strained silicon layer increases charge transfer efficiency, decreases image lag,...
US-7,164,168 Non-planar flash memory having shielding between floating gates
A first plurality of memory cells is formed on pillars in a first column of the array. A second plurality of memory cells is formed in a first set of trenches in...
US-7,164,165 MIS capacitor
An MIS capacitor with low leakage and high capacitance is disclosed. A layer of hemispherical grained polysilicon (HSG) is formed as a lower electrode. Prior to...
US-7,164,161 Method of formation of dual gate structure for imagers
A device, as in an integrated circuit, includes diverse components such as transistors and capacitors. After conductive layers for all types of components are...
US-7,164,156 Electronic systems using optical waveguide interconnects formed throught a semiconductor wafer
An integrated circuit with a number of optical waveguides that are formed in high aspect ratio holes. The high aspect ratio holes extend through a semiconductor...
US-7,163,893 Advanced barrier liner formation for vias
A high integrity, reliable liner is disclosed for a via in which a titanium aluminide layer is preformed as a lining within a via hole prior to deposition of...
US-7,163,845 Internal package heat dissipator
A technique is provided for dissipating heat from an integrated circuit within a package. A thermally conductive strip may be disposed adjacent to an integrated...
US-7,163,837 Method of forming a resistance variable memory element
A method for controlling silver doping of a chalcogenide glass in a resistance variable memory element is disclosed herein. The method includes forming a silver...
US-7,163,641 Method of forming high aspect ratio apertures
A plasma etch process for etching BPSG employing two primary etchants at low flows and pressures, and a relatively low temperature environment within the etch...
US-7,163,447 Apparatus and method for conditioning a contact surface of a processing pad used in processing microelectronic...
Conditioning devices, systems and methods for conditioning a contact surface of a processing pad used in processing microelectronic workpieces. One embodiment of...
US-7,163,439 Methods and systems for conditioning planarizing pads used in planarizing substrates
Monitoring the process of planarizing a workpiece, e.g., conditioning a CMP pad, can present some difficulties. Aspects of this invention provide methods and...
US-7,163,019 Method of reducing water spotting and oxide growth on a semiconductor structure
The present invention relates to a method of cleaning and drying a semiconductor structure in a modified conventional gas etch/rinse or dryer vessel. In an...
US-7,163,017 Polysilicon etch useful during the manufacture of a semiconductor device
A method for etching a polysilicon layer comprises the steps of providing a semiconductor wafer substrate assembly having at least first and second features...
US-7,162,796 Method of making an interposer with contact structures
A method of making an interposer having an array of contact structures for making temporary electrical contact with the leads of a chip package. The contact...
US-7,162,744 Connected support entitlement system and method of operation
An entitlement system and method for computers allowing controlled access to operating systems, software applications, data, or hardware for a computer system....
US-7,162,668 Memory with element redundancy
A memory device to perform an erase operation algorithm that specifically deals with different types of defects in a memory array. The memory array of one...
US-7,162,606 Multiple segment data object management
A multiple segment data structure and method manage data objects stored in multiple segments. The structure and method use one or more multiple segment index...
US-7,162,592 Method for bus capacitance reduction
Data bus capacitance is reduced by decoupling unaccessed memory circuits from a data bus during data transfers to or from other memory circuits.
US-7,162,570 Flash memory programming
The various embodiments provide for programming floating-gate, or flash, memory devices by writing a block of data words to a volatile storage media from an...
US-7,162,567 Memory hub and method for memory sequencing
A memory module includes a memory hub coupled to several memory devices. The memory hub includes at least one performance counter that tracks one or more system...
US-7,162,386 Dynamically adaptable semiconductor parametric testing
An apparatus, method, system, and signal-bearing medium may provide multiple maps, which may include multiple probing sequences to be called upon at run-time...
US-7,161,870 Synchronous flash memory command sequence
A computer system comprises a memory controller and a synchronous non-volatile memory device coupled to the memory controller via a main memory bus. The...
US-7,161,866 Memory device tester and method for testing reduced power states
A memory device tester capable of testing for proper operation of reduced power states in memory devices. The memory device tester can include a processor or a...
US-7,161,857 Memory redundancy programming
A method and apparatus is provided for performing a redundancy programming. The system of the present invention includes a device testing unit for performing a...
US-7,161,821 Apparatus and method for mounting microelectronic devices on a mirrored board assembly
The present invention is directed to a system, a module, and an apparatus and method for forming a microelectronic memory device. In one embodiment, a system...
US-7,161,394 Digital phase mixers with enhanced speed
Digital phase mixers with enhanced speed are provided. A phase mixer generates a signal having a phase between the phases of two input signals based on select...
US-7,161,391 Skew tolerant high-speed digital phase detector
A skew-tolerant digital phase detector is provided. Specifically, a detector is provided in the digital phase detector to detect certain failure conditions that...
US-7,161,376 Variable impedence output buffer
An output buffer for a semiconductor memory device and other semiconductor devices includes a feedback circuit to dynamically control the output impedance of the...
US-7,161,373 Method for testing using a universal wafer carrier for wafer level die burn-in
A reusable burn-in/test fixture for testing unsingulated dice on a semiconductor wafer consisting of two halves. The first half of the test fixture is a wafer...
US-7,161,372 Input system for an operations circuit
An integrated device includes a redundant bond pad for accessing internal circuitry in the event that the main bond pad for that circuitry is difficult to access...
US-7,161,250 Projected contact structures for engaging bumped semiconductor devices and methods of making the same
A bumped semiconductor device contact structure is disclosed including at least one non-planar contact pad having a plurality of projections extending therefrom...
US-7,161,246 Interconnect alloys and methods and apparatus using same
Integrated circuit interconnect alloys having copper, silver or gold as the major constituent element. The resulting reduction in melting temperature allows for...
US-7,161,237 Flip chip packaging using recessed interposer terminals
A method and apparatus for packaging a semiconductor die with an interposer substrate. The semiconductor device assembly includes a conductively bumped...
US-7,161,236 Bow control in an electronic package
A package including a package substrate, a die-substrate assembly including a substrate including a plurality of layers including a layer having a mesh to...
US-7,161,219 MRAM devices with fine tuned offset
A MRAM cell structure is disclosed as containing an additional ferromagnetic layer and coupling layer between the third ferromagnetic layer and the...
US-7,161,217 Trench corner effect bidirectional flash memory cell
A non-volatile memory cell structure that is capable of holding two data bits. The structure includes a trench in a substrate with two sides of the trench being...
US-7,161,211 Aluminum-containing film derived from using hydrogen and oxygen gas in sputter deposition
Aluminum-containing films having an oxygen content within the films. The aluminum-containing film is formed by introducing hydrogen gas along with argon gas into...
US-7,161,203 Gated field effect device comprising gate dielectric having different K regions
This invention includes gated field effect devices, and methods of forming gated field effect devices. In one implementation, a gated field effect device...
US-7,161,201 Antiferromagnetically stabilized pseudo spin valve for memory applications
The invention relates to improving the switching reliability of a magnetic memory cell in a magnetic random access memory (MRAM). Embodiments of the invention...
US-7,161,174 Field-effect transistors having doped aluminum oxide dielectrics
Doped aluminum oxide layers having a porous aluminum oxide layer and methods of their fabrication. The porous aluminum oxide layer may be formed by evaporation...
US-7,160,817 Dielectric material forming methods
A dielectric material forming method includes forming a first monolayer and forming a second monolayer on the first monolayer, one of the first and second...
US-7,160,801 Integrated circuit using a dual poly process
A method for forming an electrical interconnect overlying a buried contact region of a substrate is characterized by a deposition of a first polycrystalline...
US-7,160,795 Method and structures for reduced parasitic capacitance in integrated circuit metallizations
A method of reducing parasitic capacitance in an integrated circuit having three or more metal levels is described. The method comprises forming a bond pad at...
US-7,160,788 Methods of forming integrated circuits
This invention includes methods of forming integrated circuits, and includes DRAM circuitry memory cells. In one implementation, a method of forming an...
US-7,160,785 Container capacitor structure and method of formation thereof
Disclosed is a container capacitor structure and method of constructing it. An etch mask and etch are used to expose portions of an exterior surface of electrode...
US-7,160,738 Magnetic annealing sequences for patterned MRAM synthetic antiferromagnetic pinned layers
A method is provided for fabricating a fixed layer for a MRAM device. The method includes providing the fixed layer. The fixed layer includes an ...
US-7,160,577 Methods for atomic-layer deposition of aluminum oxides in integrated circuits
The present inventors devised unique atomic-layer deposition systems, methods, and apparatus suitable for aluminum-oxide deposition. One exemplary method entails...
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