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Patent # Description
US-7,182,669 Methods and systems for planarizing workpieces, e.g., microelectronic workpieces
Planarizing workpieces, e.g., microelectronic workpieces, can employ a process indicator that is adapted to change an optical property in response to a...
US-7,182,668 Methods for analyzing and controlling performance parameters in mechanical and chemical-mechanical...
Methods and apparatuses for analyzing and controlling performance parameters in planarization of microelectronic substrates. In one embodiment, a planarizing...
US-7,182,241 Multi-functional solder and articles made therewith, such as microelectronic components
Aspects of the invention provide solder compositions which include two different fluxing agents. One of the fluxing agents promotes melting of a metal of the...
US-7,181,837 Plating buss and a method of use thereof
The present invention relates generally to a plating buss design and method for minimizing short circuit problems in PCB panel singulation. More particularly,...
US-7,181,593 Active memory command engine and method
A command engine for an active memory receives high level tasks from a host and generates corresponding sets of either DCU commands to a DRAM control unit or ACU...
US-7,181,584 Dynamic command and/or address mirroring system and method for memory modules
A memory module includes a memory hub that couples signals to memory devices mounted on opposite first and second surfaces of a memory module substrate. The...
US-7,181,566 Scratch control memory array in a flash memory device
A memory device has a scratch control array of non-volatile memory cells that is separate from the primary array of memory cells. The scratch control array...
US-7,180,803 Data compression read mode for memory testing
Memory devices having a normal mode of operation and a test mode of operation are useful in quality programs. The test mode of operation includes a data...
US-7,180,802 Method of stress-testing an isolation gate in a dynamic random access memory
The present invention includes a DRAM array. The DRAM array includes a first memory cell, a second memory cell and an isolation gate formed between the first and...
US-7,180,797 Reduced power registered memory module and method
A registered memory module includes a plurality of flip-flops having respective data terminals, respective clock terminals receiving a clock signal and output...
US-7,180,791 Flash with consistent latency for read operations
A synchronous flash memory includes an array of non-volatile memory cells. The memory device has a package configuration that is compatible with an SDRAM. The...
US-7,180,781 Memory block erasing in a flash memory device
An erase pulse is applied to the memory block to be erased. An erase verification operation is performed to verify that each memory cell of the memory block is...
US-7,180,591 Semiconductor processors, sensors, semiconductor processing systems, semiconductor workpiece processing...
Semiconductor processors, sensors, semiconductor processing systems, semiconductor workpiece processing methods, and turbidity monitoring methods are provided....
US-7,180,522 Apparatus and method for distributed memory control in a graphics processing system
A distributed memory controller memory system for a graphics processing system having addressable memory areas each coupled to a respective memory controller....
US-7,180,386 Variable resistance circuit
A method of finding an unknown value from within a range of values is disclosed that divides the range into weighted subranges and then, beginning with an...
US-7,180,370 CMOS amplifiers with frequency compensating capacitors
The frequency and transient responses of a CMOS differential amplifier are improved by employing one or more compensating capacitors. A compensating capacitor...
US-7,180,189 Abberation mark and method for estimating overlay error and optical abberations
An aberration mark for use in an optical photolithography system, and a method for estimating overlay errors and optical aberrations. The aberration mark...
US-7,180,006 Tape substrate and method for fabricating the same
A tape substrate including an insulating film, a copper foil pattern formed on the insulating film at one side of the insulating film, and provided with a...
US-7,179,730 Semiconductor damascene trench and methods thereof
A memory device cell layout, a computer system comprising a memory device having a particular cell layout, and methods of fabricating static memory cells and...
US-7,179,717 Methods of forming integrated circuit devices
Forming an integrated circuit device includes forming a hard mask layer overlying a semiconductor substrate. The hard mask layer is patterned to expose portions...
US-7,179,716 Method of forming a metal-containing layer over selected regions of a semiconductor substrate
The invention includes methods of electrochemically treating semiconductor substrates. The invention includes a method of electroplating a substance. A substrate...
US-7,179,706 Permeable capacitor electrode
The present teachings describe a container capacitor that utilizes an etchant permeable lower electrode for the formation of single or double-sided capacitors...
US-7,179,703 Method of forming shallow doped junctions having a variable profile gradation of dopants
Disclosed are methods for forming a shallow junction with a variable concentration profile gradation of dopants. The process of the present invention includes...
US-7,179,681 Techniques for packaging multiple device components
Techniques for fabricating multiple device components. Specifically, techniques for fabricating a stacked package comprising at least one I/C module and a...
US-7,179,361 Method of forming a mass over a semiconductor substrate
The invention includes methods of electrochemically treating semiconductor substrates. The invention includes a method of electroplating a substance. A substrate...
US-7,177,976 Top/bottom symmetrical protection scheme for flash
A synchronous flash memory includes an array of non-volatile memory cells. The memory device has a package configuration that is compatible with an SDRAM. The...
US-7,177,231 Selectable clock input
The present invention provides a memory device having a mode register with a selectable bit which sets the memory device to operate with a selected one of a...
US-7,177,224 Controlling multiple signal polarity in a semiconductor device
A method and apparatus for controlling multiple signal polarity in a memory device. A desired active state signal polarity of at least one signal pad of a device...
US-7,177,223 Memory device and method having banks of different sizes
A memory device, such as a synchronous random access memory device, includes four banks of memory cells arranged in rows and columns. Different numbers of...
US-7,177,213 Capacitor supported precharging of memory digit lines
Circuits and methods are provided for precharging pairs of memory digit lines. The final precharge voltage of the digit lines is different from the average of...
US-7,177,208 Circuit and method for operating a delay-lock loop in a power saving manner
A control circuit for a delay-lock loop having a delay line and a phase detector is used in a memory device. In a standby mode, the control circuit isolates a...
US-7,177,193 Programmable fuse and antifuse and method therefor
P-channel MOSFET devices are used as reprogrammable fuse or antifuse elements in a memory decode circuit by utilizing anomalous hole generation. An applied...
US-7,177,170 Apparatus and method for selectively configuring a memory device using a bi-stable relay
The disclosed embodiments of the present invention include a semiconductor memory apparatus having a selectable memory capacity. In one embodiment, a system...
US-7,176,719 Capacitively-coupled level restore circuits for low voltage swing logic circuits
A level restore circuit includes differential sides and a capacitive network having capacitors cross-coupled between the differential sides to provide a...
US-7,176,702 Contact system for wafer level testing
Disclosed herein are exemplary embodiments of a contact system (referred to as a "Z-block") for interfacing a semiconductor wafer to an electrical tester, and...
US-7,176,676 Apparatuses and methods for monitoring rotation of a conductive microfeature workpiece
Apparatuses and methods for monitoring microfeature workpiece rotation during processing, such as brushing, by monitoring characteristics corresponding to a...
US-7,176,576 Conductive connection forming methods, oxidation reducing methods, and integrated circuits formed thereby
A conductive connection forming method includes forming a first layer comprising a first metal on a substrate and forming a second layer comprising a second...
US-7,176,566 Semiconductor package assembly and method for electrically isolating modules
A semiconductor package assembly and method for electrically isolating modules, having a capacitor within the semiconductor package assembly. The package...
US-7,176,549 Shallow trench isolation using low dielectric constant insulator
A shallow trench isolation is disclosed wherein the trench depth is reduced beyond that achieved in prior art processes. The reduced trench depth helps to...
US-7,176,513 Memory cell and method for forming the same
A semiconductor memory cell structure and method for forming the same. The memory cell is formed on a surface of a substrate and includes an active region formed...
US-7,176,434 Row driven imager pixel
An imaging system includes a pixel that does not require a row select transistor. Instead, an operating voltage is selectively provided to the pixel's readout...
US-7,176,118 Circuit constructions
The invention includes methods of forming regions of differing composition over a substrate. A first material having a pattern of at least one substantially...
US-7,176,109 Method for forming raised structures by controlled selective epitaxial growth of facet using spacer
Raised structures comprising overlying silicon layers formed by controlled selective epitaxial growth, and methods for forming such raised-structure on a...
US-7,176,096 Transistor gate and local interconnect
A method of forming a local interconnect for a semiconductor integrated circuit, the local interconnect comprising a refractory silicide contact having a...
US-7,176,093 Semiconductor processing methods of forming integrated circuitry
Semiconductor processing methods of forming integrated circuitry are described. In one embodiment, memory circuitry and peripheral circuitry are formed over a...
US-7,176,087 Methods of forming electrical connections
In one aspect, the invention provides a method of forming an electrical connection in an integrated circuitry device. According to one preferred implementation,...
US-7,176,086 Interconnecting conductive layers of memory devices
Field-effect transistors, select gates, and select lines have first and second conductive layers separated by an interlayer dielectric layer. A conductive strap...
US-7,176,079 Method of fabricating a semiconductor device with a wet oxidation with steam process
A method of fabricating a semiconductor device includes depositing a dielectric film and subjecting the dielectric film to a wet oxidation in a rapid thermal...
US-7,176,077 Methods of forming memory cells and arrays having underlying source-line connections
Floating-gate memory cells having a trench source-line contact are suited for increased packing densities without a need for low-resistance ground straps placed...
US-7,176,073 Methods of forming memory cells having diodes and electrode plates connected to source/drain regions
The invention pertains to thin film constructions comprising NVRAM devices built over a versatile substrate base. In particular aspects, a device includes a body...
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