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Patent # Description
US-7,155,644 Automatic test entry termination in a memory device
A memory device has a control register comprising a test mode disable bit. The test mode is initially enabled. If the device does not receive an appropriate key...
US-7,155,630 Method and unit for selectively enabling an input buffer based on an indication of a clock transition
A system unit including a processor unit and an input storage unit. The processor unit generates an input signal and a clock signal. The input storage unit...
US-7,155,589 Permanent memory block protection in a flash memory device
A secure command is entered into a Flash memory device. A control data word is written to the memory device to specify which blocks of memory are to be...
US-7,155,565 Automatic learning in a CAM
A CAM array which enables a learning process to be an extension of a search process is disclosed. When a search fails to find a matching data in the CAM array,...
US-7,155,562 Method for reading while writing to a single partition flash memory
A device manager receives an operation request for a memory device. The device manager suspends interrupts to be serviced and determines if there is sufficient...
US-7,155,561 Method and system for using dynamic random access memory as cache memory
A cache memory system and method includes a DRAM having a plurality of banks, and it also includes 2 SRAMs each having a capacity that is equal to the capacity...
US-7,155,391 Systems and methods for speech recognition and separate dialect identification
A speech-to-text conversion system. The two-way speech recognition and dialect system comprises a computer system, an attached microphone assembly, and...
US-7,155,300 Method for using data regarding manufacturing procedures integrated circuits (IC's) have undergone, such as...
An inventive method in an integrated circuit (IC) manufacturing process for using data regarding repair procedures conducted on IC's at probe to determine...
US-7,154,800 No-precharge FAMOS cell and latch circuit in a memory device
The fuse and latch circuit has a Floating gate Avalanche injection Metal Oxide Semiconductor (FAMOS) transistor (fuse) that is coupled to a read circuit. The...
US-7,154,785 Charge pump circuitry having adjustable current outputs
Methods and apparatus are provided. A memory device includes charge pump circuitry having a plurality of parallel charge pumps for supplying a programming...
US-7,154,782 Contiguous block addressing scheme
An improved non-volatile erase block memory device apparatus and method is described that incorporates an improved addressing scheme to provide for extended...
US-7,154,781 Contiguous block addressing scheme
An improved non-volatile erase block memory device apparatus and method is described that incorporates an improved addressing scheme to provide for extended...
US-7,154,780 Contiguous block addressing scheme
An improved non-volatile erase block memory device apparatus and method is described that incorporates an improved addressing scheme to provide for extended...
US-7,154,778 Nanocrystal write once read only memory for archival storage
Structures and methods for write once read only memory employing charge trapping are provided. The write once read only memory cell includes a metal oxide...
US-7,154,546 Pixel optimization for color
A macro pixel is provided. The macro pixel includes at least two color pixel elements. Each color pixel element includes a photoreceptor that in response to...
US-7,154,354 High permeability layered magnetic films to reduce noise in high speed interconnection
A structure for magnetically shielded transmission lines for use with high speed integrated circuits having an improved signal to noise ratio, and a method for...
US-7,154,289 Input buffer with automatic switching point adjustment circuitry, and synchronous dram device including same
An input buffer is presented for buffering an input signal having a voltage magnitude which alternates between a first voltage level and a second voltage level,...
US-7,154,153 Memory device
A floating gate transistor has a reduced barrier energy at an interface with an adjacent gate insulator, allowing faster charge transfer across the gate...
US-7,154,146 Dielectric plug in mosfets to suppress short-channel effects
The invention provides a technique to fabricate a dielectric plug in a MOSFET. The invention includes apparatus and systems that include one or more devices...
US-7,154,140 Write once read only memory with large work function floating gates
Structures and methods for write once read only memory employing floating gates are provided. The write once read only memory cell includes a floating gate...
US-7,154,136 Isolation structures for preventing photons and carriers from reaching active areas and methods of formation
Regions of an integrated circuit are isolated by a structure that includes at least one isolating trench on the periphery of an active area. The trench is deep,...
US-7,154,078 Differential column readout scheme for CMOS APS pixels
The present invention provides an improved column readout circuitry and method of operation which minimizes substrate and other common mode noise during a read...
US-7,154,075 Method and apparatus for pixel signal binning and interpolation in column circuits of a sensor circuit
A binning circuit and related method, wherein pixel signals from column circuits in a sensor circuit are sampled and interpolated. The binning circuit samples...
US-7,153,788 Method and apparatus for attaching a workpiece to a workpiece support
A method for attaching a workpiece, for example a semiconductor die, to a workpiece holder, for example a lead frame die support, comprises the steps of...
US-7,153,779 Method to eliminate striations and surface roughness caused by dry etch
A plasma etch process for forming a high aspect ratio contact opening through a silicon oxide layer is disclosed. The silicon oxide layer is plasma etched using...
US-7,153,778 Methods of forming openings, and methods of forming container capacitors
A patterned mask can be formed as follows. A first patterned photoresist is formed over a masking layer and utilized during a first etch into the masking layer....
US-7,153,777 Methods and apparatuses for electrochemical-mechanical polishing
Methods and apparatuses for removing material from a microfeature workpiece are disclosed. In one embodiment, the microfeature workpiece is contacted with a...
US-7,153,775 Conductive material patterning methods
A patterning method includes providing a first material (e.g., copper) and transforming at a least a surface region of the first material to a second material...
US-7,153,769 Methods of forming a reaction product and methods of forming a conductive metal silicide by reaction of metal...
A method of forming a reaction product includes providing a semiconductor substrate comprising a first material. A second material is formed over the first...
US-7,153,754 Methods for forming porous insulators from "void" creating materials and structures and semiconductor devices...
Methods for forming porous insulative materials for use in forming dielectric structures of semiconductor devices are disclosed. Each insulative material may...
US-7,153,753 Strained Si/SiGe/SOI islands and processes of making same
A process of making a strained silicon-on-insulator structure is disclosed. A recess is formed in a substrate to laterally isolate an active area. An...
US-7,153,751 Method of forming a capacitor
The invention includes a method of forming a semiconductor construction. A semiconductor substrate is provided, and a conductive node is formed to be supported...
US-7,153,746 Capacitors, methods of forming capacitors, and methods of forming capacitor dielectric layers
A method of forming a capacitor includes forming first and second capacitor electrodes over a substrate. A capacitor dielectric region is formed intermediate the...
US-7,153,741 Use of selective epitaxial silicon growth in formation of floating gates
Methods and apparatus utilizing epitaxial silicon growth on a base structure of a floating gate of a floating-gate memory cell to increase the available coupling...
US-7,153,736 Methods of forming capacitors and methods of forming capacitor dielectric layers
A method of forming a capacitor includes forming first capacitor electrode material over a semiconductor substrate. A silicon nitride comprising layer is formed...
US-7,153,731 Method of forming a field effect transistor with halo implant regions
A method of forming a field effect transistor includes forming a channel region within bulk semiconductive material of a semiconductor substrate. Source/drain...
US-7,153,721 Resistance variable memory elements based on polarized silver-selenide network growth
The invention relates to a resistance variable memory element including polarizable metal-chalcogen regions within a doped chalcogenide glass. A method for...
US-7,153,719 Method of fabricating a storage gate pixel design
A method of fabricating a pixel cell having a shutter gate structure. First and second charge barriers are respectively created between a photodiode and a first...
US-7,153,707 Method for forming a storage cell capacitor compatible with high dielectric constant materials
An integrated circuit structure includes a digit line and an electrode adapted to be part of a storage cell capacitor and includes a barrier layer interposed...
US-7,153,634 Dual layer workpiece masking and manufacturing process
The status of a plurality of service orders is summarized. A first data set that includes a plurality of records corresponding to service orders, such as...
US-7,153,410 Methods and apparatus for electrochemical-mechanical processing of microelectronic workpieces
Methods and apparatuses for electrochemical-mechanical processing of microelectronic workpieces. One embodiment of an electrochemical processing apparatus in...
US-7,153,195 Methods and apparatus for selectively removing conductive material from a microelectronic substrate
Methods and apparatuses for selectively removing conductive materials from a microelectronic substrate. A method in accordance with an embodiment of the...
US-7,153,191 Polishing liquids for activating and/or conditioning fixed abrasive polishing pads, and associated systems and...
Polishing liquids for activating and/or conditioning fixed abrasive polishing pads, and associated systems and methods are disclosed. A method in accordance with...
US-7,153,164 Method and apparatus for forming modular sockets using flexible interconnects and resulting structures
A modular bare die socket assembly is provided for attaching a plurality of miniature semiconductor dice to a substrate. The socket assembly is comprised of a...
US-7,152,143 Integrated semiconductor memory chip with presence detect data capability
An integrated semiconductor memory chip includes hardwired presence detect data which can be accessed for transmission to a location external to the memory chip...
US-7,152,141 Obtaining search results for content addressable memory
Content addressable memory (CAM) in which search results such as an address code and an array match signal can be obtained for multiple search widths. The CAM...
US-7,152,139 Techniques for generating serial presence detect contents
Techniques are presented for automatically generating Serial Presence Detect (SPD) contents. Standards for specific values associated with SPD contents are...
US-7,152,123 Distributed configuration storage
Systems and methods for providing distributed configuration storage are presented. The configuration storage is divided into distributed configuration target...
US-7,151,709 Memory device and method having programmable address configurations
A memory device includes a configurable address register having a first set of input buffers coupled to a first set on address bus terminals and a second set of...
US-7,151,707 Memory device and method having data path with multiple prefetch I/O configurations
A memory device is operable in either a high mode or a low speed mode. In either mode, 32 bits of data from each of two memory arrays are prefetched into...
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