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Patent # Description
US-7,162,606 Multiple segment data object management
A multiple segment data structure and method manage data objects stored in multiple segments. The structure and method use one or more multiple segment index...
US-7,162,592 Method for bus capacitance reduction
Data bus capacitance is reduced by decoupling unaccessed memory circuits from a data bus during data transfers to or from other memory circuits.
US-7,162,570 Flash memory programming
The various embodiments provide for programming floating-gate, or flash, memory devices by writing a block of data words to a volatile storage media from an...
US-7,162,567 Memory hub and method for memory sequencing
A memory module includes a memory hub coupled to several memory devices. The memory hub includes at least one performance counter that tracks one or more system...
US-7,162,386 Dynamically adaptable semiconductor parametric testing
An apparatus, method, system, and signal-bearing medium may provide multiple maps, which may include multiple probing sequences to be called upon at run-time...
US-7,161,870 Synchronous flash memory command sequence
A computer system comprises a memory controller and a synchronous non-volatile memory device coupled to the memory controller via a main memory bus. The...
US-7,161,866 Memory device tester and method for testing reduced power states
A memory device tester capable of testing for proper operation of reduced power states in memory devices. The memory device tester can include a processor or a...
US-7,161,857 Memory redundancy programming
A method and apparatus is provided for performing a redundancy programming. The system of the present invention includes a device testing unit for performing a...
US-7,161,821 Apparatus and method for mounting microelectronic devices on a mirrored board assembly
The present invention is directed to a system, a module, and an apparatus and method for forming a microelectronic memory device. In one embodiment, a system...
US-7,161,394 Digital phase mixers with enhanced speed
Digital phase mixers with enhanced speed are provided. A phase mixer generates a signal having a phase between the phases of two input signals based on select...
US-7,161,391 Skew tolerant high-speed digital phase detector
A skew-tolerant digital phase detector is provided. Specifically, a detector is provided in the digital phase detector to detect certain failure conditions that...
US-7,161,376 Variable impedence output buffer
An output buffer for a semiconductor memory device and other semiconductor devices includes a feedback circuit to dynamically control the output impedance of the...
US-7,161,373 Method for testing using a universal wafer carrier for wafer level die burn-in
A reusable burn-in/test fixture for testing unsingulated dice on a semiconductor wafer consisting of two halves. The first half of the test fixture is a wafer...
US-7,161,372 Input system for an operations circuit
An integrated device includes a redundant bond pad for accessing internal circuitry in the event that the main bond pad for that circuitry is difficult to access...
US-7,161,250 Projected contact structures for engaging bumped semiconductor devices and methods of making the same
A bumped semiconductor device contact structure is disclosed including at least one non-planar contact pad having a plurality of projections extending therefrom...
US-7,161,246 Interconnect alloys and methods and apparatus using same
Integrated circuit interconnect alloys having copper, silver or gold as the major constituent element. The resulting reduction in melting temperature allows for...
US-7,161,237 Flip chip packaging using recessed interposer terminals
A method and apparatus for packaging a semiconductor die with an interposer substrate. The semiconductor device assembly includes a conductively bumped...
US-7,161,236 Bow control in an electronic package
A package including a package substrate, a die-substrate assembly including a substrate including a plurality of layers including a layer having a mesh to...
US-7,161,219 MRAM devices with fine tuned offset
A MRAM cell structure is disclosed as containing an additional ferromagnetic layer and coupling layer between the third ferromagnetic layer and the...
US-7,161,217 Trench corner effect bidirectional flash memory cell
A non-volatile memory cell structure that is capable of holding two data bits. The structure includes a trench in a substrate with two sides of the trench being...
US-7,161,211 Aluminum-containing film derived from using hydrogen and oxygen gas in sputter deposition
Aluminum-containing films having an oxygen content within the films. The aluminum-containing film is formed by introducing hydrogen gas along with argon gas into...
US-7,161,203 Gated field effect device comprising gate dielectric having different K regions
This invention includes gated field effect devices, and methods of forming gated field effect devices. In one implementation, a gated field effect device...
US-7,161,201 Antiferromagnetically stabilized pseudo spin valve for memory applications
The invention relates to improving the switching reliability of a magnetic memory cell in a magnetic random access memory (MRAM). Embodiments of the invention...
US-7,161,174 Field-effect transistors having doped aluminum oxide dielectrics
Doped aluminum oxide layers having a porous aluminum oxide layer and methods of their fabrication. The porous aluminum oxide layer may be formed by evaporation...
US-7,160,817 Dielectric material forming methods
A dielectric material forming method includes forming a first monolayer and forming a second monolayer on the first monolayer, one of the first and second...
US-7,160,801 Integrated circuit using a dual poly process
A method for forming an electrical interconnect overlying a buried contact region of a substrate is characterized by a deposition of a first polycrystalline...
US-7,160,795 Method and structures for reduced parasitic capacitance in integrated circuit metallizations
A method of reducing parasitic capacitance in an integrated circuit having three or more metal levels is described. The method comprises forming a bond pad at...
US-7,160,788 Methods of forming integrated circuits
This invention includes methods of forming integrated circuits, and includes DRAM circuitry memory cells. In one implementation, a method of forming an...
US-7,160,785 Container capacitor structure and method of formation thereof
Disclosed is a container capacitor structure and method of constructing it. An etch mask and etch are used to expose portions of an exterior surface of electrode...
US-7,160,738 Magnetic annealing sequences for patterned MRAM synthetic antiferromagnetic pinned layers
A method is provided for fabricating a fixed layer for a MRAM device. The method includes providing the fixed layer. The fixed layer includes an ...
US-7,160,577 Methods for atomic-layer deposition of aluminum oxides in integrated circuits
The present inventors devised unique atomic-layer deposition systems, methods, and apparatus suitable for aluminum-oxide deposition. One exemplary method entails...
US-7,160,179 Methods for mechanical or chemical-mechanical planarization of microelectronic-device substrate assemblies
Planarizing machines, carrier heads for planarizing machines and methods for planarizing microelectronic-device substrate assemblies in mechanical or...
US-7,160,176 Methods and apparatus for electrically and/or chemically-mechanically removing conductive material from a...
A method and apparatus for removing conductive material from a microelectronic substrate. In one embodiment, a support member supports a microelectronic...
US-7,159,752 Continuous mode solder jet apparatus
A solder jet apparatus is disclosed. The solder jet apparatus is a continuous mode solder jet that includes a blanking system and raster scan system. The use of...
US-7,159,311 Method of making an interposer with contact structures
A method of making an interposer having an array of contact structures for making temporary electrical contact with the leads of a chip package. The contact...
US-7,159,141 Repairable block redundancy scheme
A scheme for block substitution within a flash memory device is disclosed which uses a programmable look-up table to store new addresses for block selection when...
US-7,159,092 Method and system for adjusting the timing offset between a clock signal and respective digital signals...
A method and circuit adaptively adjust respective timing offsets of digital signals relative to a clock output along with the digital signals to enable a latch...
US-7,158,443 Delay-lock loop and method adapting itself to operate over a wide frequency range
A delay-lock loop receives an input clock signal from the output of a programmable divider that receives a reference clock signal. The delay-lock loop includes a...
US-7,158,422 System and method for communicating information to a memory device using a reconfigured device pin
A system and method for communicating information to and from memory deices. In one embodiment, the invention includes a memory system having a memory device...
US-7,158,410 Integrated DRAM-NVRAM multi-level memory
An integrated DRAM-NVRAM, multi-level memory cell is comprised of a vertical DRAM device with a shared vertical gate floating plate device. The floating plate...
US-7,158,401 Methods for machine detection of at least one aspect of an object, methods for machine identification of a...
Electronic systems including Si/Ge substrates. The electronic systems can include data storage devices and/or logic devices having active regions extending into...
US-7,158,399 Digital data apparatuses and digital data operational methods
Digital data apparatuses and digital data operational methods are described. According to one embodiment, a digital data apparatus includes a semiconductive...
US-7,158,280 Methods and systems for improved boundary contrast
The present invention relates to methods and systems that define feature boundaries in a radiation sensitive medium on a workpiece using a diffraction-type...
US-7,158,031 Thin, flexible, RFID label and system for use
A radio frequency indentification (RFID) label includes an integrated circuit and an antenna. The label may also include two flexible films directly sealed to...
US-7,158,004 Integrated circuit inductors
The invention relates to an inductor comprising a plurality of interconnected conductive segments interwoven with a substrate. The inductance of the inductor is...
US-7,157,783 Platinum stuffed with silicon oxide as a diffusion oxygen barrier for semiconductor devices
The present invention provides techniques to fabricate high dielectric MIM storage cell capacitors. In one embodiment, this is accomplished by forming a silicon...
US-7,157,778 Semiconductor constructions
The invention encompasses a method of forming an oxide region over a semiconductor substrate. A nitrogen-containing layer is formed across at least some of the...
US-7,157,775 Semiconductor constructions
The invention includes a semiconductor construction having a pair of channel regions that have sub-regions doped with indium and surrounded by boron. A pair of...
US-7,157,771 Vertical device 4F.sup.2 EEPROM memory
EEPROM memory devices and arrays are described that facilitate the use of vertical floating gate memory cells and select gates in NOR or NAND high density memory...
US-7,157,769 Flash memory having a high-permittivity tunnel dielectric
A high permittivity tunneling dielectric is used in a flash memory cell to provide greater tunneling current into the floating gate with smaller gate voltages....
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