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Patent # Description
US-7,151,698 Integrated charge sensing scheme for resistive memories
An integrated charge sensing scheme for sensing the resistance of a resistive memory element is described. The current through a resistive memory cell is used to...
US-7,151,690 6F.sup.2 3-Transistor DRAM gain cell
A high density vertical three transistor memory cell is provided. The high density vertical three transistor memory cell is formed in a vertical pillar. The...
US-7,151,689 Adjusting the frequency of an oscillator for use in a resistive sense amp
A system and methods optimize the operation of sensing circuitry. In one embodiment, the output of a sensing circuit is stored in a register and processed...
US-7,151,688 Sensing of resistance variable memory devices
A resistance variable memory device such as e.g., a PCRAM memory device, with either a 4T (transistor) or 2T memory cell configuration and either a dual cell...
US-7,151,659 Gapped-plate capacitor
In a semiconductor device, a capacitor is provided which has a gap in at least one of its plates. The gap is small enough so that fringe capacitance between the...
US-7,151,539 Resampling system and method for graphics data including sine-wave components
A method and system for calculating resample output values from input samples and their associated sample values. A resampling circuit calculates a frequency...
US-7,151,475 Minimized differential SAR-type column-wide ADC for CMOS image sensors
An analog-to-digital converter comprising a minimal amount of circuitry for conversion of an input analog signal to a series of digital bits. A differential...
US-7,151,472 Reference voltage stabilization in CMOS sensors
A reference voltage generator for use in an image sensor provides a reference voltage to an S/H block during a pixel read-out operation and another reference...
US-7,151,303 Fully-depleted (FD) (SOI) MOSFET access transistor
A fully-depleted (FD) Silicon-on-Insulator (SOI) MOSFET access transistor comprising a gate electrode of a conductivity type which is opposite the conductivity...
US-7,151,294 High density stepped, non-planar flash memory
A first plurality of memory cells is in a first plane in a first column of the array. A second plurality of memory cells is in a second plane in the same column....
US-7,151,291 Capacitor structures, DRAM cell structures, and integrated circuitry, and methods of forming capacitor...
The invention encompasses DRAM constructions, capacitor constructions, integrated circuitry, and methods of forming DRAM constructions, integrated circuitry and...
US-7,151,285 Transistor structures and transistors with a germanium-containing channel
A transistor structure includes a first undoped, silicon-containing channel layer, a buried germanium channel, and a second undoped, silicon-containing channel...
US-7,151,273 Silver-selenide/chalcogenide glass stack for resistance variable memory
The invention is related to methods and apparatus for providing a resistance variable memory element with improved data retention and switching characteristics....
US-7,151,056 Method and apparatus for forming a planarizing pad having a film and texture elements for planarization of...
A planarizing pad for planarizing a microelectronic substrate, and a method and apparatus for forming the planarizing pad. In one embodiment, planarizing pad...
US-7,151,054 Semiconductor processing methods of forming and utilizing antireflective material layers, and methods of...
In one aspect, the invention includes a semiconductor processing method comprising exposing silicon, nitrogen and oxygen in gaseous form to a high density plasma...
US-7,151,041 Methods of forming semiconductor circuitry
The invention includes a method of forming semiconductor circuitry wherein a first semiconductor structure comprising a first monocrystalline semiconductor...
US-7,151,040 Methods for increasing photo alignment margins
Methods and structures are provided for increasing alignment margins when contacting pitch multiplied interconnect lines with other conductive features in memory...
US-7,151,037 Processes of forming stacked resistor constructions
The invention includes semiconductor constructions having a thin film stacked resistor in electrical connection with a source/drain region of a transistor...
US-7,151,030 Horizontal memory devices with vertical gates
Structures and methods for memory devices are provided which operate with lower control gate voltages than conventional floating gate transistors, and which do...
US-7,151,026 Semiconductor processing methods
Semiconductor processing methods are described which can be used to reduce the chances of an inadvertent contamination during processing. In one implementation,...
US-7,151,024 Long retention time single transistor vertical memory gain cell
A single transistor vertical memory gain cell with long data retention times. The memory cell is formed from a silicon carbide substrate to take advantage of the...
US-7,151,013 Semiconductor package having exposed heat dissipating surface and method of fabrication
A high density semiconductor package with thermally enhanced properties is described. The semiconductor package includes a pair of lead frames, each being...
US-7,150,949 Further method to pattern a substrate
The present invention relates to methods for patterning substrates, such as reticles, masks or wafers, which reduce critical dimension variations, improving CD...
US-7,150,945 Polarized reticle, photolithography system, and method of forming a pattern using a polarized reticle in...
Polarized reticles, photolithography systems utilizing a polarized reticle, and methods of using such a system are disclosed. A polarized reticle is formed...
US-7,150,789 Atomic layer deposition methods
An atomic layer deposition method includes positioning a semiconductor substrate within an atomic layer deposition chamber. A first precursor gas is flowed to...
US-7,150,390 Flip chip dip coating encapsulant
A method for underfilling and encapsulating a flip chip in one step is disclosed. The flip chip is immersed in a polymer bath to apply a coating of the polymer...
US-7,149,986 Automated load determination for partitioned simulation
A method and device for automatically generating load circuits for a netlist. A computer system having a schematic for a circuit is used to create a netlist....
US-7,149,876 Method and apparatus for a shift register based interconnection for a massively parallel processor array
A system and method for using wider data paths within Processing Elements (PEs) of a Massively Parallel Array (MPP) to speed the computational performance of the...
US-7,149,875 Data reordering processor and method for use in an active memory device
An active memory device includes a command engine that receives high level tasks from a host and generates corresponding sets of either DCU commands to a DRAM...
US-7,149,874 Memory hub bypass circuit and method
A computer system and a method used to access data from a plurality of memory devices with a memory hub. The computer system includes a plurality of memory...
US-7,149,857 Out of order DRAM sequencer
Memory access requests are successively received in a memory request queue of a memory controller. Any conflicts or potential delays between temporally proximate...
US-7,149,845 Current mode logic scheme and circuit for matchline sense amplifier design using constant current bias cascode...
A CAM device features matchlines which are coupled in series between a top current source, a bottom current source, and ground. The top current source is...
US-7,149,841 Memory devices with buffered command address bus
Circuits and methods are provided that alleviate overloading of the command address bus and limit decreases in command address bus bandwidth to allow increased...
US-7,149,824 Dynamically setting burst length of memory device by applying signal to at least one external pin during a read...
One or more external control pins and/or addressing pins on a memory device are used to set one or both of a burst length and burst type of the memory device.
US-7,149,158 Apparatus and method for providing uninterrupted continuous play during a change of sides of a dual-sided...
An apparatus and method for providing continuous uninterrupted playback of a dual sided optical disk during side-to-side changing of the optical disk. The point...
US-7,149,145 Delay stage-interweaved analog DLL/PLL
A methodology is disclosed that enables the delay stages of an analog delay locked loop (DLL) or phase locked loop (PLL) to be programmed according to the...
US-7,149,143 Decoder for memory data bus
Memory device is described that utilizes a reduced number of sense amplifiers to sense the data bits of a selected column page. The sense amplifiers are...
US-7,149,141 Memory device and method having low-power, high write latency mode and high-power, low write latency mode...
A logic circuit operates write receivers in a dynamic random access memory device in either a low-power mode, high write latency mode or a high-power mode, low...
US-7,149,124 Boosted substrate/tub programming for flash memories
A boosted substrate tub/substrate floating gate memory cell programming process is described that applies a voltage to the substrate or substrate "tub" of a NAND...
US-7,149,117 Reduction of adjacent floating gate data pattern sensitivity
The method for programming non-volatile memory cells erases the memory cells to be programmed. The memory cells are then programmed to a reduced floating gate...
US-7,149,109 Single transistor vertical memory gain cell
A high density vertical single transistor gain cell is realized for DRAM operation. The gain cell includes a vertical transistor having a source region, a drain...
US-7,149,100 Serial transistor-cell array architecture
A memory array architecture suitable for variable resistance memory that mitigates sneak path and associated problems by limiting the number of memory cells...
US-7,148,971 Apparatus for measuring the physical properties of a surface and a pattern generating apparatus for writing a...
The present invention relates to a pattern generating apparatus for writing a pattern on a surface of an object, comprising: a stage having an object having a...
US-7,148,833 Sharing operational amplifier between two stages of pipelined ADC and/or two channels of signal processing...
A mechanism for discharging parasitic capacitance at an input of an operational amplifier, which is shared between two stages of a pipelined analog-to-digital...
US-7,148,831 Variable quantization ADC for image sensors
An A/D converter suitable for use in a system in which the signal power of noise increases with the signal power of the signal, such as an imaging system,...
US-7,148,742 Power supply voltage detection circuitry and methods for use of the same
Power detection circuitry that provides a substantially constant trip-point is provided. The circuitry is immune to temperature and process variations, thus...
US-7,148,718 Articles of manufacture and wafer processing apparatuses
The present invention includes an electronic device workpiece processing apparatus and method of communicating signals within an electronic device workpiece...
US-7,148,715 Systems and methods for testing microelectronic imagers and microfeature devices
Systems and methods for testing microelectronic imagers and microfeature devices are disclosed herein. In one embodiment, a method includes providing a...
US-7,148,555 Method for enhancing electrode surface area in DRAM cell capacitors
Methods for forming the lower electrode of a capacitor in a semiconductor circuit, and the capacitors formed by such methods are provided. The lower electrode is...
US-7,148,547 Semiconductor contact device
The invention provides an advanced metallization technique for fabricating a memory cell array on a substrate. The array is fabricated by forming discrete and...
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