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Patent # Description
US-7,183,611 SRAM constructions, and electronic systems comprising SRAM constructions
The invention includes SRAM constructions comprising at least one transistor device having an active region extending into a crystalline layer comprising Si/Ge....
US-7,183,531 Amplification with feedback capacitance for photodetector signals
Signals from an imager pixel photodetector are received by an amplifier having capacitive feedback, such as a capacitive transimpedance amplifier (CTIA). The...
US-7,183,485 Microelectronic component assemblies having lead frames adapted to reduce package bow
The present disclosure suggests various microelectronic component assembly designs and methods for manufacturing microelectronic component assemblies. In one...
US-7,183,220 Plasma etching methods
A plasma etching method includes forming a polymer comprising carbon and a halogen over at least some internal surfaces of a plasma etch chamber. After forming...
US-7,183,208 Methods for treating pluralities of discrete semiconductor substrates
The invention includes a method for treating a plurality of discrete semiconductor substrates. The discrete semiconductor substrates are placed within a reactor...
US-7,183,194 Method of forming socket contacts
In a socket used to house semiconductor die during testing, a recessed socket contact and methods of making the same are provided that avoid pinching the die's...
US-7,183,191 Method for fabricating a chip scale package using wafer level processing
Channels are formed that pass through an active surface of a semiconductor substrate to provide isolation between adjacent active surface regions defining...
US-7,183,185 Methods of forming transistor gates; and methods of forming programmable read-only memory constructions
The invention includes a method of forming a transistor gate. One or more conductive materials are formed over a semiconductor substrate, and a block is formed...
US-7,183,164 Methods of reducing floating body effect
Methods of reducing the floating body effect in vertical transistors are disclosed. The floating body effect occurs when an active region in a pillar is cut off...
US-7,183,138 Method and apparatus for decoupling conductive portions of a microelectronic device package
A method and apparatus for decoupling conductive portions of a microelectronic device package. In one embodiment, the package can include a microelectronic...
US-7,183,134 Ultrathin leadframe BGA circuit package
A circuit package is formed using a leadframe. The leadframe is formed or etched to align a plurality of bond pad structures above a reference plane while...
US-7,183,133 Microelectronic devices with improved heat dissipation and methods for cooling microelectronic devices
Microelectronic devices with improved heat dissipation, methods of making microelectronic devices, and methods of cooling microelectronic devices are disclosed...
US-7,182,979 High efficiency method for performing a chemical vapordeposition utilizing a nonvolatile precursor
A method directed to the use of a nonvolatile precursor, either a solid or liquid precursor, suitable for CVD, including liquid source CVD (LSCVD). Using the...
US-7,182,669 Methods and systems for planarizing workpieces, e.g., microelectronic workpieces
Planarizing workpieces, e.g., microelectronic workpieces, can employ a process indicator that is adapted to change an optical property in response to a...
US-7,182,668 Methods for analyzing and controlling performance parameters in mechanical and chemical-mechanical...
Methods and apparatuses for analyzing and controlling performance parameters in planarization of microelectronic substrates. In one embodiment, a planarizing...
US-7,182,241 Multi-functional solder and articles made therewith, such as microelectronic components
Aspects of the invention provide solder compositions which include two different fluxing agents. One of the fluxing agents promotes melting of a metal of the...
US-7,181,837 Plating buss and a method of use thereof
The present invention relates generally to a plating buss design and method for minimizing short circuit problems in PCB panel singulation. More particularly,...
US-7,181,593 Active memory command engine and method
A command engine for an active memory receives high level tasks from a host and generates corresponding sets of either DCU commands to a DRAM control unit or ACU...
US-7,181,584 Dynamic command and/or address mirroring system and method for memory modules
A memory module includes a memory hub that couples signals to memory devices mounted on opposite first and second surfaces of a memory module substrate. The...
US-7,181,566 Scratch control memory array in a flash memory device
A memory device has a scratch control array of non-volatile memory cells that is separate from the primary array of memory cells. The scratch control array...
US-7,180,803 Data compression read mode for memory testing
Memory devices having a normal mode of operation and a test mode of operation are useful in quality programs. The test mode of operation includes a data...
US-7,180,802 Method of stress-testing an isolation gate in a dynamic random access memory
The present invention includes a DRAM array. The DRAM array includes a first memory cell, a second memory cell and an isolation gate formed between the first and...
US-7,180,797 Reduced power registered memory module and method
A registered memory module includes a plurality of flip-flops having respective data terminals, respective clock terminals receiving a clock signal and output...
US-7,180,791 Flash with consistent latency for read operations
A synchronous flash memory includes an array of non-volatile memory cells. The memory device has a package configuration that is compatible with an SDRAM. The...
US-7,180,781 Memory block erasing in a flash memory device
An erase pulse is applied to the memory block to be erased. An erase verification operation is performed to verify that each memory cell of the memory block is...
US-7,180,591 Semiconductor processors, sensors, semiconductor processing systems, semiconductor workpiece processing...
Semiconductor processors, sensors, semiconductor processing systems, semiconductor workpiece processing methods, and turbidity monitoring methods are provided....
US-7,180,522 Apparatus and method for distributed memory control in a graphics processing system
A distributed memory controller memory system for a graphics processing system having addressable memory areas each coupled to a respective memory controller....
US-7,180,386 Variable resistance circuit
A method of finding an unknown value from within a range of values is disclosed that divides the range into weighted subranges and then, beginning with an...
US-7,180,370 CMOS amplifiers with frequency compensating capacitors
The frequency and transient responses of a CMOS differential amplifier are improved by employing one or more compensating capacitors. A compensating capacitor...
US-7,180,189 Abberation mark and method for estimating overlay error and optical abberations
An aberration mark for use in an optical photolithography system, and a method for estimating overlay errors and optical aberrations. The aberration mark...
US-7,180,006 Tape substrate and method for fabricating the same
A tape substrate including an insulating film, a copper foil pattern formed on the insulating film at one side of the insulating film, and provided with a...
US-7,179,730 Semiconductor damascene trench and methods thereof
A memory device cell layout, a computer system comprising a memory device having a particular cell layout, and methods of fabricating static memory cells and...
US-7,179,717 Methods of forming integrated circuit devices
Forming an integrated circuit device includes forming a hard mask layer overlying a semiconductor substrate. The hard mask layer is patterned to expose portions...
US-7,179,716 Method of forming a metal-containing layer over selected regions of a semiconductor substrate
The invention includes methods of electrochemically treating semiconductor substrates. The invention includes a method of electroplating a substance. A substrate...
US-7,179,706 Permeable capacitor electrode
The present teachings describe a container capacitor that utilizes an etchant permeable lower electrode for the formation of single or double-sided capacitors...
US-7,179,703 Method of forming shallow doped junctions having a variable profile gradation of dopants
Disclosed are methods for forming a shallow junction with a variable concentration profile gradation of dopants. The process of the present invention includes...
US-7,179,681 Techniques for packaging multiple device components
Techniques for fabricating multiple device components. Specifically, techniques for fabricating a stacked package comprising at least one I/C module and a...
US-7,179,361 Method of forming a mass over a semiconductor substrate
The invention includes methods of electrochemically treating semiconductor substrates. The invention includes a method of electroplating a substance. A substrate...
US-7,177,976 Top/bottom symmetrical protection scheme for flash
A synchronous flash memory includes an array of non-volatile memory cells. The memory device has a package configuration that is compatible with an SDRAM. The...
US-7,177,231 Selectable clock input
The present invention provides a memory device having a mode register with a selectable bit which sets the memory device to operate with a selected one of a...
US-7,177,224 Controlling multiple signal polarity in a semiconductor device
A method and apparatus for controlling multiple signal polarity in a memory device. A desired active state signal polarity of at least one signal pad of a device...
US-7,177,223 Memory device and method having banks of different sizes
A memory device, such as a synchronous random access memory device, includes four banks of memory cells arranged in rows and columns. Different numbers of...
US-7,177,213 Capacitor supported precharging of memory digit lines
Circuits and methods are provided for precharging pairs of memory digit lines. The final precharge voltage of the digit lines is different from the average of...
US-7,177,208 Circuit and method for operating a delay-lock loop in a power saving manner
A control circuit for a delay-lock loop having a delay line and a phase detector is used in a memory device. In a standby mode, the control circuit isolates a...
US-7,177,193 Programmable fuse and antifuse and method therefor
P-channel MOSFET devices are used as reprogrammable fuse or antifuse elements in a memory decode circuit by utilizing anomalous hole generation. An applied...
US-7,177,170 Apparatus and method for selectively configuring a memory device using a bi-stable relay
The disclosed embodiments of the present invention include a semiconductor memory apparatus having a selectable memory capacity. In one embodiment, a system...
US-7,176,719 Capacitively-coupled level restore circuits for low voltage swing logic circuits
A level restore circuit includes differential sides and a capacitive network having capacitors cross-coupled between the differential sides to provide a...
US-7,176,702 Contact system for wafer level testing
Disclosed herein are exemplary embodiments of a contact system (referred to as a "Z-block") for interfacing a semiconductor wafer to an electrical tester, and...
US-7,176,676 Apparatuses and methods for monitoring rotation of a conductive microfeature workpiece
Apparatuses and methods for monitoring microfeature workpiece rotation during processing, such as brushing, by monitoring characteristics corresponding to a...
US-7,176,576 Conductive connection forming methods, oxidation reducing methods, and integrated circuits formed thereby
A conductive connection forming method includes forming a first layer comprising a first metal on a substrate and forming a second layer comprising a second...
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