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Patent # Description
US-7,167,401 Low power chip select (CS) latency option
A system and method to reduce standby currents in input buffers in an electronic device (e.g., a memory device) is disclosed. The input buffers may be activated...
US-7,167,400 Apparatus and method for improving dynamic refresh in a memory device
An apparatus and method for generating a control pulse for closing an active wordline in a memory device is provided. A timeout generator circuit having a time...
US-7,167,399 Flash memory device with a variable erase pulse
A method of operating a flash memory device according to an embodiment of the present invention includes selecting a flash cell in a flash memory device to...
US-7,167,396 Erase verify for nonvolatile memory using reference current-to-voltage converters
A memory device verify system determines a state of memory cells in a memory. The memory includes a memory array having a plurality of memory cells coupled to...
US-7,167,231 Method and apparatus for printing large data flows
An aspect of the present invention includes a method for patterning a workpiece covered at least partly with a layer sensitive to electromagnetic radiation,...
US-7,167,156 Electrowetting display
The present invention comprises construction of a display from display elements that are actuated using the physical principle of electrowetting. In one...
US-7,167,014 Method for testing using a universal wafer carrier for wafer level die burn-in
A reusable burn-in/test fixture for testing unsingulated dice on a semiconductor wafer consisting of two halves. The first half of the test fixture is a wafer...
US-7,167,012 Universal wafer carrier for wafer level die burn-in
A reusable burn-in/test fixture for testing unsingulated dice on a semiconductor wafer consisting of two halves. The first half of the test fixture is a wafer...
US-7,167,010 Pin-in elastomer electrical contactor and methods and processes for making and using the same
A contactor card assembly for use with a semiconductor substrate. An upper keeper plate and a lower keeper plate each include a number of conductive pins...
US-7,166,925 Semiconductor devices having stereolithographically fabricated protective layers thereon through which contact...
A method for forming packaged substrates includes using a stereolithographic process to form a protective dielectric polymeric sealing structure on at least the...
US-7,166,918 Semiconductor package assembly and method for electrically isolating modules
A semiconductor package assembly and method for electrically isolating modules, having a capacitor within the semiconductor package assembly. The package...
US-7,166,915 Multi-chip module system
Multi-chip module systems and method of fabrication thereof wherein the equivalent of a failed die of a multi-chip module (MCM) is added to the module in a...
US-7,166,896 Cross diffusion barrier layer in polysilicon
A semiconductor device includes a cross diffusion barrier layer sandwiched between a gate layer and an electrode layer. The gate layer has a first gate portion...
US-7,166,888 Scalable high density non-volatile memory cells in a contactless memory array
A plurality of split gate non-volatile memory cells are formed vertically in a trench along the sidewalls. Each cell is comprised of a bistable element and an...
US-7,166,886 DRAM cells with repressed floating gate memory, low tunnel barrier interpoly insulators
Structures and methods for memory cells having a volatile and a non-volatile component in a single memory cell are provided. The memory cell includes a first...
US-7,166,885 Semiconductor devices
The invention includes semiconductor devices. In one implementation, semiconductor device includes a first conductive material. A first layer of a dielectric...
US-7,166,883 Capacitor structures
The invention includes a method of forming a capacitor structure. A first electrical node is formed, and a layer of metallic aluminum is formed over the first...
US-7,166,879 Photogate for use in an imaging device
A photogate-based photosensor for use in a CMOS imager exhibiting improved short wavelength light response. The photogate is formed of a thin conductive layer...
US-7,166,875 Vertical diode structures
A method of making a vertical diode is provided, the vertical dioxide having associated therewith a diode opening extending through an insulation layer and...
US-7,166,543 Methods for forming an enriched metal oxide surface for use in a semiconductor device
Methods of forming a metal oxide surface that is enriched with metal oxide in its higher oxidation state for use in a semiconductor device are provided. A metal...
US-7,166,539 Wet etching method of removing silicon from a substrate
A wet etching method of removing silicon from a substrate includes depositing a layer comprising silicon in elemental form over a substrate. The layer is exposed...
US-7,166,527 Etch stop layer in poly-metal structures
In accordance with one embodiment of the present invention, a method of interfacing a poly-metal structure and a semiconductor substrate is provided where an...
US-7,166,509 Write once read only memory with large work function floating gates
Structures and methods for write once read only memory employing floating gates are provided. The write once read only memory cell includes a floating gate...
US-7,166,495 Method of fabricating a multi-die semiconductor package assembly
An apparatus and method for increasing integrated circuit density comprising an upper die and a lower die, the latter preferably a flip chip, which are connected...
US-7,166,479 Methods of forming magnetic shielding for a thin-film memory element
A monolithically formed ferromagnetic thin-film memory is disclosed that has local shielding on at least two sides of selected magnetic storage elements. The...
US-7,166,252 Method for reducing warpage during application and curing of encapsulant materials on a printed circuit board
A method and apparatus for preventing board warpage during the application and curing or drying of liquid epoxies, or the like, on printed circuit boards using a...
US-7,166,247 Foamed mechanical planarization pads made with supercritical fluid
Foamed thermoplastic polymeric mechanical planarization polishing pads ("MP pads") made with supercritical fluids are presented. A supercritical fluid foaming...
US-7,165,975 Electrical connecting apparatus
An electrical connecting apparatus is characterized by inserting a first pin having a flange portion into a through hole of an elastic body via a seat, by...
US-7,165,322 Process of forming socket contacts
A socket contact formation process comprises forming a contact head from a conductive material, forming a contact body from a semiconductive material configured...
US-7,165,185 DDR II write data capture calibration
A calibration circuit for calibrating the input data path of a digital circuit is disclosed. A simple string of a repeating data pattern such as, e.g., "1100,"...
US-7,165,143 System and method for manipulating cache data
A processing system optimized for data string manipulations includes data string execution circuitry associated with a bus interface unit or memory controller....
US-7,165,004 Dynamically adaptable semiconductor parametric testing
An apparatus, method, system, and signal-bearing medium may provide multiple maps, which may include multiple probing sequences to be called upon at run-time...
US-7,164,611 Data retention kill function
A secure memory device that is configured to prevent unauthorized access of data is disclosed. More specifically, a kill function logic device is capable of...
US-7,164,607 Dual bus memory burst architecture
Methods and apparatus for a memory device including a burst architecture employ a double bus architecture that is multiplexed onto an output bus. The resulting...
US-7,164,597 Computer systems
A two-transistor SRAM cell includes a first FET. The first FET is an ultrathin FET of a first polarity type and includes a control electrode, a first load...
US-7,164,595 Device and method for using dynamic cell plate sensing in a DRAM memory cell
A memory cell, device, system and method for operating a memory cell are disclosed that utilize an isolated dynamic cell plate. The memory cell includes a first...
US-7,164,294 Method for forming programmable logic arrays using vertical gate transistors
One aspect disclosed herein relates to a method for forming a programmable logic array. Various embodiments of the method include forming a first logic plane and...
US-7,164,260 Bandgap reference circuit with a shared resistive network
A CMOS bandgap reference (BGR) voltage generator circuit has a passive resistor T-network of low resistance connected between the inverting and non-inverting...
US-7,164,188 Buried conductor patterns formed by surface transformation of empty spaces in solid state materials
A plurality of buried conductors and/or buried plate patterns formed within a monocrystalline substrate is disclosed. A plurality of empty-spaced buried patterns...
US-7,164,182 Pixel with strained silicon layer for improving carrier mobility and blue response in imagers
An imager having a pixel cell having an associated strained silicon layer. The strained silicon layer increases charge transfer efficiency, decreases image lag,...
US-7,164,168 Non-planar flash memory having shielding between floating gates
A first plurality of memory cells is formed on pillars in a first column of the array. A second plurality of memory cells is formed in a first set of trenches in...
US-7,164,165 MIS capacitor
An MIS capacitor with low leakage and high capacitance is disclosed. A layer of hemispherical grained polysilicon (HSG) is formed as a lower electrode. Prior to...
US-7,164,161 Method of formation of dual gate structure for imagers
A device, as in an integrated circuit, includes diverse components such as transistors and capacitors. After conductive layers for all types of components are...
US-7,164,156 Electronic systems using optical waveguide interconnects formed throught a semiconductor wafer
An integrated circuit with a number of optical waveguides that are formed in high aspect ratio holes. The high aspect ratio holes extend through a semiconductor...
US-7,163,893 Advanced barrier liner formation for vias
A high integrity, reliable liner is disclosed for a via in which a titanium aluminide layer is preformed as a lining within a via hole prior to deposition of...
US-7,163,845 Internal package heat dissipator
A technique is provided for dissipating heat from an integrated circuit within a package. A thermally conductive strip may be disposed adjacent to an integrated...
US-7,163,837 Method of forming a resistance variable memory element
A method for controlling silver doping of a chalcogenide glass in a resistance variable memory element is disclosed herein. The method includes forming a silver...
US-7,163,641 Method of forming high aspect ratio apertures
A plasma etch process for etching BPSG employing two primary etchants at low flows and pressures, and a relatively low temperature environment within the etch...
US-7,163,447 Apparatus and method for conditioning a contact surface of a processing pad used in processing microelectronic...
Conditioning devices, systems and methods for conditioning a contact surface of a processing pad used in processing microelectronic workpieces. One embodiment of...
US-7,163,439 Methods and systems for conditioning planarizing pads used in planarizing substrates
Monitoring the process of planarizing a workpiece, e.g., conditioning a CMP pad, can present some difficulties. Aspects of this invention provide methods and...
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