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Patent # Description
US-7,148,544 Semiconductor-on-insulator constructions
The invention includes semiconductor constructions having a thin film stacked resistor in electrical connection with a source/drain region of a transistor...
US-7,148,538 Vertical NAND flash memory array
Memory devices, arrays, and strings are described that facilitate the use of vertical floating gate memory cells in NAND architecture memory strings, arrays, and...
US-7,148,536 Memory circuitry and method of forming memory circuitry
A method of forming memory circuitry having a memory array having a plurality of memory capacitors and having peripheral memory circuitry operatively configured...
US-7,148,534 Angled implant in a fabrication technique to improve conductivity of a base material
Ion implantation may be used to break up a dielectric layer that forms during the fabrication of a memory array. More specifically, during the fabrication of...
US-7,148,528 Pinned photodiode structure and method of formation
An imager having a photodiode with a shallow doping profile with respect to the top surface of a substrate is disclosed. An imager with a graded pinned surface...
US-7,148,525 Using high-k dielectrics in isolation structures method, pixel and imager device
An imager device that has an isolation structure such that pinned photodiode characteristics are maintained without increasing doping levels. The invention...
US-7,148,462 Pixel with differential readout
An imager in which two adjacent pixels share row and reset lines and a row selection circuitry while the output transistors of the two pixels are configured as a...
US-7,148,134 Integrated circuitry and a semiconductor processing method of forming a series of conductive lines
A semiconductor processing method of forming a plurality of conductive lines includes, a) providing a substrate; b) providing a first conductive material layer...
US-7,148,118 Methods of forming metal nitride, and methods of forming capacitor constructions
The invention encompasses methods of forming metal nitride proximate dielectric materials. The metal nitride comprises two portions, with one of the portions...
US-7,148,102 Methods of forming buried bit line DRAM circuitry
A method of forming buried bit line DRAM circuitry includes collectively forming a buried bit line forming trench, bit line vias extending from the bit line...
US-7,148,083 Transfer mold semiconductor packaging processes
In one implementation, a circuit substrate includes a substrate having opposing sides. At least one of the sides is configured for transfer mold packaging and...
US-7,147,974 Methods for converting reticle configurations
The invention includes methods of converting reticles from configurations suitable for utilization with later generation (shorter wavelength) stepper radiations...
US-7,147,973 Method to recover the exposure sensitivity of chemically amplified resins from post coat delay effect
Methods of fabricating a photomask, methods of treating a chemically amplified resist-coated photomask blank, a photomask blank resulting from the methods, and...
US-7,147,543 Carrier assemblies, planarizing apparatuses including carrier assemblies, and methods for planarizing...
Carrier assemblies, planarizing machines with carrier assemblies, and methods for mechanical and/or chemical-mechanical planarization of micro-device workpieces...
US-7,146,814 Micro-machine and a method of powering a micro-machine
A rotatable micro-machine is comprised of a solvent reservoir, a porous evaporation region and a channel connecting the solvent reservoir to the evaporation...
US-7,146,722 Method of forming a bond pad structure
A bond pad structure comprising two bond pads, methods of forming the bond pad structure, an integrated circuit die incorporating the bond pad structure, and...
US-7,146,720 Fabricating a carrier substrate by using a solder resist opening as a combination pin one indicator and fiducial
A method for forming a fiducial and pin one indicator that utilizes a single solder resist opening in a die mounting substrate to perform the combined functions...
US-7,146,585 Programmable element latch circuit
An antifuse latch device and method for performing a redundancy pretest without the use of additional test circuitry is disclosed. Conventional antifuse latch...
US-7,146,489 Methods for intelligent caching in an embedded DRAM-DSP architecture
An efficient embedded-DRAM processor architecture and associated methods. In one exemplary embodiment, the architecture includes a DRAM array, a set of register...
US-7,146,447 System for facilitating the replacement or insertion of devices in a computer system through the use of a...
A computer software system is disclosed for facilitating a user's replacement or insertion of devices in a computer server network system. The system allows a...
US-7,145,817 Reduced power redundancy address decoder and comparison circuit
A redundancy address decoder for a memory having at least one bank of memory segmented into a plurality of memory blocks. The redundancy address decoder includes...
US-7,145,816 Using redundant memory for extra features
Apparatus and methods are provided. A memory device has a memory array comprising primary and redundant portions. A redundancy circuit is coupled to the memory...
US-7,145,815 Active termination control
A method and apparatus are provided for active termination control in a memory by an module register providing an active termination control signal to the...
US-7,145,800 Preconditioning of defective and redundant columns in a memory device
A redundant column is mapped to a defective or over-erased column in the memory array. When an erase command occurs, both the redundant column and the defective...
US-7,145,799 Chip protection register unlocking
An improved Flash memory device is described with a protection register lock bit erase enable circuit. A bond pad coupled to the lock bit erase enable circuit of...
US-7,145,798 Methods for fabricating a magnetic keeper for a memory device
An MRAM device comprising an array of MRAM elements, with each element having an MRAM bit influenced by a magnetic field from a current flowing through a...
US-7,145,795 Multi-cell resistive memory array architecture with select transistor
A memory device having memory cells in which a single access transistor controls the grounding of at least two storage elements, such as resistive storage...
US-7,145,577 System and method for multi-sampling primitives to reduce aliasing
A method and system for performing multi-sample, antialiased rendering of images by performing multi-sample antialiasing at the primitive level. Geometric...
US-7,145,376 Method and circuitry for reducing duty cycle distortion in differential delay lines
A method and circuitry are provided for reducing duty cycle distortion in differential solid state delay lines. The differential solid state delay lines of the...
US-7,145,374 Methods and apparatus for delay circuit
The present invention provides apparatus and methods relating to delay circuits. An electronic system includes a deskewing circuit configured to measure a delay...
US-7,145,372 Startup circuit and method
A startup circuit provides a single connection to a node of a reference or other circuit to be started. The startup circuit injects high current into devices to...
US-7,145,355 Selectively configurable probe structures, e.g., for testing microelectronic components
Microelectronic components are commonly tested with probe cards. Certain aspects of the invention provide alternative probes, probe cards, and methods of testing...
US-7,145,323 Apparatus for measuring parasitic capacitance and inductance of I/O leads on an electrical component using a...
Apparatus and methods are provided for measuring the potential for mutual coupling in an integrated circuit package of any type or configuration using a network...
US-7,145,228 Microelectronic devices
Methods for packaging microelectronic devices and microelectronic devices formed by such methods are disclosed herein. In one embodiment, a method includes...
US-7,145,225 Interposer configured to reduce the profiles of semiconductor device assemblies and packages including the same...
An interposer includes a substrate, first and second sets of contact pads carried by the substrate, and receptacles formed in a surface of the substrate and...
US-7,145,189 Photon amplification for image sensors
A pixel cell having a substrate, photo-conversion device, and at least one dielectric layer over the photo-conversion device. The at least one dielectric layer...
US-7,145,186 Memory cell with trenched gated thyristor
One aspect of this disclosure relates to a memory cell. Various memory cell embodiments include an isolated semiconductor region separated from a bulk...
US-7,144,810 Methods for forming rough ruthenium-containing layers and structures/methods using same
A method for forming a rough ruthenium-containing layer on the surface of a substrate assembly includes providing a ruthenium-containing precursor into the...
US-7,144,779 Method of forming epitaxial silicon-comprising material
The invention includes methods of forming epitaxial silicon-comprising material and methods of forming vertical transistors. In one implementation, a method of...
US-7,144,690 Photolithographic methods of using a single reticle to form overlapping patterns
The invention includes a photolithographic method in which overlapping first and second exposure patterns are formed on a photosensitive material from light...
US-7,144,304 Method and apparatus for planarizing a microelectronic substrate with a tilted planarizing surface
A method and apparatus for planarizing a microelectronic substrate. In one embodiment, the apparatus can include an elongated, non-continuous polishing pad...
US-7,144,245 Packages for semiconductor die
A ball grid array assembly includes a package cover that encapsulates a die and a portion of a substrate to which the die is attached, including an edge of the...
US-7,143,500 Method to prevent damage to probe card
Probe cards are configured with protective circuitry suitable for use in electrical testing of semiconductor dice without damage to the probe cards. Protective...
US-7,143,255 Chip protection register lock circuit in a flash memory device
A chip protection register lock circuit uses a plurality of lock bits in a lock bit register. If the register contains N bits, N/2 bits of the register are...
US-7,142,838 Wake up device for a communications system
The present invention teaches a communications system comprising a first communications device for receiving data and a wake up signal. The first communications...
US-7,142,577 Method of forming mirrors by surface transformation of empty spaces in solid state materials and structures thereon
A multi-layered reflective mirror formed of spaced-apart plate-shaped empty space patterns formed within a substrate is disclosed. The plurality of plate-shaped...
US-7,142,543 High speed programmable counter
A digital counter allows the provision of start and stop values in order to allow it to be configurable to any length. The counter rolls over to zero at a...
US-7,142,461 Active termination control though on module register
A method and apparatus are provided for active termination control in a memory by a module register providing an active termination control signal to the memory....
US-7,142,459 Programming flash memories
A flash memory device has an array of flash memory cells, a detector for detecting an external voltage applied to the flash memory device, and a command control...
US-7,142,446 Apparatus and method to reduce undesirable effects caused by a fault in a memory device
A method and apparatus is provided for reducing the current in a memory device. Peripheral device control signals are translated to the wordline off voltage...
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