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Reduced data line pre-fetch scheme
A memory device for reducing the number of data read lines needed in a memory device. Specifically, multiple helper flip-flops are used to prefetch data in a...
Method for mismatch detection between the frequency of illumination source
and the duration of optical...
A method for achieving flickerless operation of imagers using a rolling shutter, including the steps of detecting flicker in an image frame and adjusting an...
Method for testing using a universal wafer carrier for wafer level die
A reusable burn-in/test fixture for testing unsingulated dice on a semiconductor wafer consisting of two halves. The first half of the test fixture is a wafer...
Air socket for testing integrated circuits
An electrical component testing device comprising a housing having at least one recess covered by a flexible membrane so as to form a chamber. A fluid passage...
Gated semiconductor assemblies and methods of forming gated semiconductor
In one aspect, the invention includes a method of forming a gated semiconductor assembly, comprising: a) forming a silicon nitride layer over and against a...
DRAM constructions, memory arrays and semiconductor constructions
The invention includes a method of depositing a noble metal. A substrate is provided. The substrate has a first region and a second region. The first and second...
Image sensor having a transistor for allowing increased dynamic range
Embodiments of the invention provide an image sensor having an improved dynamic range. A pixel cell comprises at least one transistor structure. The transistor...
Transistor with variable electron affinity gate
A SiC material composition is selected to establish the barrier energy between the SIC gate and a gate insulator. Various embodiments of selected SiC material...
Method and apparatus for fabricating a memory device with a dielectric
etch stop layer
The present technique relates to a method and apparatus to provide a dielectric etch stop layer that prevents shorts for a buried digit layer as an interconnect....
Semiconductor processing methods of forming dynamic random access memory
Methods of forming dynamic random access memories (DRAM) are described. In one embodiment, an insulative layer is formed over a substrate having a plurality of...
Vacuum treatment of waste stream with anti-incrustation measures
A method of treating a waste stream comprises a vacuum treatment to promote disintegration of the waste material by "flash vapor" production, causing a swiftly...
Low friction polish-stop stratum for endpointing chemical-mechanical
planarization processing of semiconductor...
The present invention is a semiconductor wafer that enhances polish-stop endpointing in chemical-mechanical planarization processes. The semiconductor wafer has...
Linear and non-linear object management
A linear and non-linear object management method and structure. A data structure on a computer-readable medium is used to store linear and non-linear objects in...
Transparent SDRAM in an embedded environment
A transparent memory array has a processor and a plurality of memory banks, each memory bank being directly connected to the processor. The memory array has...
Partially-ordered cams used in ternary hierarchical address
An apparatus and method that utilizes partial ordering of ternary hierarchical addresses and their associated masks entries in both binary and ternary content...
CAM with automatic writing to the next free address
A method and apparatus for automatically writing non-matching data to a non-valid location within a Content Addressable Memory (CAM) is disclosed. The non-valid...
Memory bus polarity indicator system and method for reducing the affects
of simultaneous switching outputs...
A method and system transfer read data from a memory device having a data bus and a data masking pin adapted to receive a masking signal during write operations...
Dynamically adaptable semiconductor parametric testing
An apparatus, method, system, and signal-bearing medium may provide multiple maps, which may include multiple probing sequences to be called upon at run-time...
Method and circuit for adjusting the timing of output data based on the
current and future states of the output...
A clock synchronization circuit receives an input clock signal along with current and future data signals. The clock synchronization circuit generates a phase...
A method, apparatus, and system are provided for implementing a zero-enabled fuse system. An apparatus includes a first set of fuses for activating a first...
Voltage regulator and data path for a memory device
A method and apparatus provide unbalanced output drive capability, for example, to correct for output skews in subsequent output stages. In one aspect, a...
Memory architecture and method of manufacture and operation thereof
An architecture, and its method of formation and operation, containing a high density memory array of semi-volatile or non-volatile memory elements, including,...
Cutting CAM peak power by clock regioning
A CAM device architecture where CAM cells are divided into at least two arrays and each array is operated in a different clock domain so that at no time are the...
Active pixel sensor with mixed analog and digital signal integration
An active pixel sensor includes mixed analog and digital signal integration on the same substrate. The analog part of the array forms the active pixel sensor,...
Method and apparatus to set a tuning range for an analog delay
An apparatus and method for an analog fine delay line, a hybrid delay line, and a delay locked loop (DLL) is described. In the DLL, a coarse phase detector...
Apparatus and method for independent control of on-die termination for
output buffers of a memory device
An apparatus and method providing independent control of on-die termination (ODT) of output buffers. The ODTs for the buffer circuits of an input/output (I/O)...
Thick solder mask for confining encapsulant material over selected
locations of a substrate and assemblies...
A solder mask includes an opening through which intermediate conductive elements may be positioned to connect bond pads of a semiconductor die exposed through an...
Trench interconnect structure and formation method
Embodiments concern vertical interconnect structures having sub-micron widths for use in integrated circuits, and methods of their manufacture, which result in...
Multilevel interconnect structure with low-k dielectric
A multilevel interconnect structure with a low-k dielectric constant is fabricated in an integrated circuit structure by the steps of depositing a layer of...
Intrinsic thermal enhancement for FBGA package
A semiconductor device for dissipating heat generated by a die during operation and having a low height profile, a semiconductor die package incorporating the...
High density stepped, non-planar nitride read only memory
A non-planar, stepped NROM array is comprised of cells formed in trenches and on pillars that are etched into a substrate. Each cell has a plurality of charge...
Structures for stabilizing semiconductor devices relative to test
substrates and methods for fabricating the...
Stabilizers to be disposed on a surface of a semiconductor device or test substrate and methods of fabricating and disposing the stabilizers on semiconductor...
Systems for forming insulative coatings for via holes in semiconductor
An insulative coating for an aperture of a semiconductor device component includes a plurality of adjacent, mutually adhered regions. The adjacent, mutually...
Methods of depositing silver onto a metal selenide-comprising surface and
methods of depositing silver onto a...
The invention includes methods of depositing silver onto a metal selenide-comprising surface, and methods of forming a resistance variable device. In one...
Reduced barrier photodiode/gate device structure for high efficiency
charge transfer and reduced lag and method...
A pixel cell having a reduced potential barrier near a region where a gate and a photodiode are in close proximity to one another, and a method for forming the...
Methods and apparatuses for planarizing microelectronic substrate
Methods and apparatuses for planarizing microelectronic substrate assemblies on fixed-abrasive polishing pads with non-abrasive lubricating planarizing...
Programmed material consolidation methods for fabricating printed circuit
Methods for fabricating semiconductor device components include use of programmed material consolidation processes to form the substrates or conductive elements...
Testing a multibank memory module
A method and system for testing a memory module that has at least a first and second memory bank. The first and second memory banks have a plurality of...
Compression circuit for testing a memory device
An apparatus for testing a memory device having a plurality of data lines includes an input circuit, a compression circuit, and an output circuit. The input...
Multiple processor system and method including multiple memory hub modules
A processor-based electronic system includes several memory modules arranged in first and second ranks. The memory modules in the first rank are directly...
Method and apparatus for data compression in memory devices
A test circuit for a memory device having a pair of arrays each of which includes a plurality of memory cells arranged in rows and columns. A pair of...
Write state machine architecture for flash memory internal instructions
A system and method for a write state machine for non-volatile memory is disclosed. The write state machine has an associated read only memory for storing...
Integrated circuit memory device and method
Structures and methods for DEAPROM memory with low tunnel barrier intergate insulators are provided. The DEAPROM memory includes a first source/drain region and...
Method and apparatus for testing image sensors
Methods and apparatuses for testing image sensors are disclosed. Desirable apparatuses of the present invention include image sensor testing devices comprising a...
Semiconductor substrate for build-up packages
The present invention provides techniques to fabricate build-up single or multichip modules. In one embodiment, this is accomplished by dispensing die-attach...
Technique for attaching die to leads
A semiconductor die assembly comprising a semiconductor die with bond pads, a plurality of leads which extend across the semiconductor die and terminate over...
Graded composition metal oxide tunnel barrier interpoly insulators
Structures and methods for programmable array type logic and/or memory devices with graded composition metal oxide tunnel barrier intergate insulators are...
Cleaning composition useful in semiconductor integrated circuit
A composition for use in semiconductor processing wherein the composition comprises water, phosphoric acid, and an organic acid; wherein the organic acid is...
Atomic layer-deposited hafnium aluminum oxide
A dielectric film containing HfAlO.sub.3 and a method of fabricating such a dielectric film produce a reliable gate dielectric having an equivalent oxide...
Method of forming a semiconductor device
In the formation of semiconductor devices, a processing method is provided, including steps for forming an oxide layer. The embodied methods involve a series of...