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Patent # Description
US-7,153,736 Methods of forming capacitors and methods of forming capacitor dielectric layers
A method of forming a capacitor includes forming first capacitor electrode material over a semiconductor substrate. A silicon nitride comprising layer is formed...
US-7,153,731 Method of forming a field effect transistor with halo implant regions
A method of forming a field effect transistor includes forming a channel region within bulk semiconductive material of a semiconductor substrate. Source/drain...
US-7,153,721 Resistance variable memory elements based on polarized silver-selenide network growth
The invention relates to a resistance variable memory element including polarizable metal-chalcogen regions within a doped chalcogenide glass. A method for...
US-7,153,719 Method of fabricating a storage gate pixel design
A method of fabricating a pixel cell having a shutter gate structure. First and second charge barriers are respectively created between a photodiode and a first...
US-7,153,707 Method for forming a storage cell capacitor compatible with high dielectric constant materials
An integrated circuit structure includes a digit line and an electrode adapted to be part of a storage cell capacitor and includes a barrier layer interposed...
US-7,153,634 Dual layer workpiece masking and manufacturing process
The status of a plurality of service orders is summarized. A first data set that includes a plurality of records corresponding to service orders, such as...
US-7,153,410 Methods and apparatus for electrochemical-mechanical processing of microelectronic workpieces
Methods and apparatuses for electrochemical-mechanical processing of microelectronic workpieces. One embodiment of an electrochemical processing apparatus in...
US-7,153,195 Methods and apparatus for selectively removing conductive material from a microelectronic substrate
Methods and apparatuses for selectively removing conductive materials from a microelectronic substrate. A method in accordance with an embodiment of the...
US-7,153,191 Polishing liquids for activating and/or conditioning fixed abrasive polishing pads, and associated systems and...
Polishing liquids for activating and/or conditioning fixed abrasive polishing pads, and associated systems and methods are disclosed. A method in accordance with...
US-7,153,164 Method and apparatus for forming modular sockets using flexible interconnects and resulting structures
A modular bare die socket assembly is provided for attaching a plurality of miniature semiconductor dice to a substrate. The socket assembly is comprised of a...
US-7,152,143 Integrated semiconductor memory chip with presence detect data capability
An integrated semiconductor memory chip includes hardwired presence detect data which can be accessed for transmission to a location external to the memory chip...
US-7,152,141 Obtaining search results for content addressable memory
Content addressable memory (CAM) in which search results such as an address code and an array match signal can be obtained for multiple search widths. The CAM...
US-7,152,139 Techniques for generating serial presence detect contents
Techniques are presented for automatically generating Serial Presence Detect (SPD) contents. Standards for specific values associated with SPD contents are...
US-7,152,123 Distributed configuration storage
Systems and methods for providing distributed configuration storage are presented. The configuration storage is divided into distributed configuration target...
US-7,151,709 Memory device and method having programmable address configurations
A memory device includes a configurable address register having a first set of input buffers coupled to a first set on address bus terminals and a second set of...
US-7,151,707 Memory device and method having data path with multiple prefetch I/O configurations
A memory device is operable in either a high mode or a low speed mode. In either mode, 32 bits of data from each of two memory arrays are prefetched into...
US-7,151,700 Reducing DQ pin capacitance in a memory device
A system and method to operate an electronic device, such as a memory chip, with a data driver circuit that is configured to reduce data pin (DQ) capacitance ....
US-7,151,698 Integrated charge sensing scheme for resistive memories
An integrated charge sensing scheme for sensing the resistance of a resistive memory element is described. The current through a resistive memory cell is used to...
US-7,151,690 6F.sup.2 3-Transistor DRAM gain cell
A high density vertical three transistor memory cell is provided. The high density vertical three transistor memory cell is formed in a vertical pillar. The...
US-7,151,689 Adjusting the frequency of an oscillator for use in a resistive sense amp
A system and methods optimize the operation of sensing circuitry. In one embodiment, the output of a sensing circuit is stored in a register and processed...
US-7,151,688 Sensing of resistance variable memory devices
A resistance variable memory device such as e.g., a PCRAM memory device, with either a 4T (transistor) or 2T memory cell configuration and either a dual cell...
US-7,151,659 Gapped-plate capacitor
In a semiconductor device, a capacitor is provided which has a gap in at least one of its plates. The gap is small enough so that fringe capacitance between the...
US-7,151,539 Resampling system and method for graphics data including sine-wave components
A method and system for calculating resample output values from input samples and their associated sample values. A resampling circuit calculates a frequency...
US-7,151,475 Minimized differential SAR-type column-wide ADC for CMOS image sensors
An analog-to-digital converter comprising a minimal amount of circuitry for conversion of an input analog signal to a series of digital bits. A differential...
US-7,151,472 Reference voltage stabilization in CMOS sensors
A reference voltage generator for use in an image sensor provides a reference voltage to an S/H block during a pixel read-out operation and another reference...
US-7,151,303 Fully-depleted (FD) (SOI) MOSFET access transistor
A fully-depleted (FD) Silicon-on-Insulator (SOI) MOSFET access transistor comprising a gate electrode of a conductivity type which is opposite the conductivity...
US-7,151,294 High density stepped, non-planar flash memory
A first plurality of memory cells is in a first plane in a first column of the array. A second plurality of memory cells is in a second plane in the same column....
US-7,151,291 Capacitor structures, DRAM cell structures, and integrated circuitry, and methods of forming capacitor...
The invention encompasses DRAM constructions, capacitor constructions, integrated circuitry, and methods of forming DRAM constructions, integrated circuitry and...
US-7,151,285 Transistor structures and transistors with a germanium-containing channel
A transistor structure includes a first undoped, silicon-containing channel layer, a buried germanium channel, and a second undoped, silicon-containing channel...
US-7,151,273 Silver-selenide/chalcogenide glass stack for resistance variable memory
The invention is related to methods and apparatus for providing a resistance variable memory element with improved data retention and switching characteristics....
US-7,151,056 Method and apparatus for forming a planarizing pad having a film and texture elements for planarization of...
A planarizing pad for planarizing a microelectronic substrate, and a method and apparatus for forming the planarizing pad. In one embodiment, planarizing pad...
US-7,151,054 Semiconductor processing methods of forming and utilizing antireflective material layers, and methods of...
In one aspect, the invention includes a semiconductor processing method comprising exposing silicon, nitrogen and oxygen in gaseous form to a high density plasma...
US-7,151,041 Methods of forming semiconductor circuitry
The invention includes a method of forming semiconductor circuitry wherein a first semiconductor structure comprising a first monocrystalline semiconductor...
US-7,151,040 Methods for increasing photo alignment margins
Methods and structures are provided for increasing alignment margins when contacting pitch multiplied interconnect lines with other conductive features in memory...
US-7,151,037 Processes of forming stacked resistor constructions
The invention includes semiconductor constructions having a thin film stacked resistor in electrical connection with a source/drain region of a transistor...
US-7,151,030 Horizontal memory devices with vertical gates
Structures and methods for memory devices are provided which operate with lower control gate voltages than conventional floating gate transistors, and which do...
US-7,151,026 Semiconductor processing methods
Semiconductor processing methods are described which can be used to reduce the chances of an inadvertent contamination during processing. In one implementation,...
US-7,151,024 Long retention time single transistor vertical memory gain cell
A single transistor vertical memory gain cell with long data retention times. The memory cell is formed from a silicon carbide substrate to take advantage of the...
US-7,151,013 Semiconductor package having exposed heat dissipating surface and method of fabrication
A high density semiconductor package with thermally enhanced properties is described. The semiconductor package includes a pair of lead frames, each being...
US-7,150,949 Further method to pattern a substrate
The present invention relates to methods for patterning substrates, such as reticles, masks or wafers, which reduce critical dimension variations, improving CD...
US-7,150,945 Polarized reticle, photolithography system, and method of forming a pattern using a polarized reticle in...
Polarized reticles, photolithography systems utilizing a polarized reticle, and methods of using such a system are disclosed. A polarized reticle is formed...
US-7,150,789 Atomic layer deposition methods
An atomic layer deposition method includes positioning a semiconductor substrate within an atomic layer deposition chamber. A first precursor gas is flowed to...
US-7,150,390 Flip chip dip coating encapsulant
A method for underfilling and encapsulating a flip chip in one step is disclosed. The flip chip is immersed in a polymer bath to apply a coating of the polymer...
US-7,149,986 Automated load determination for partitioned simulation
A method and device for automatically generating load circuits for a netlist. A computer system having a schematic for a circuit is used to create a netlist....
US-7,149,876 Method and apparatus for a shift register based interconnection for a massively parallel processor array
A system and method for using wider data paths within Processing Elements (PEs) of a Massively Parallel Array (MPP) to speed the computational performance of the...
US-7,149,875 Data reordering processor and method for use in an active memory device
An active memory device includes a command engine that receives high level tasks from a host and generates corresponding sets of either DCU commands to a DRAM...
US-7,149,874 Memory hub bypass circuit and method
A computer system and a method used to access data from a plurality of memory devices with a memory hub. The computer system includes a plurality of memory...
US-7,149,857 Out of order DRAM sequencer
Memory access requests are successively received in a memory request queue of a memory controller. Any conflicts or potential delays between temporally proximate...
US-7,149,845 Current mode logic scheme and circuit for matchline sense amplifier design using constant current bias cascode...
A CAM device features matchlines which are coupled in series between a top current source, a bottom current source, and ground. The top current source is...
US-7,149,841 Memory devices with buffered command address bus
Circuits and methods are provided that alleviate overloading of the command address bus and limit decreases in command address bus bandwidth to allow increased...
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