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Memory system and method using partial ECC to achieve low power refresh
and fast access to data
A DRAM memory device includes several banks of memory cells each of which are divided into first and second sets of memory cells. The memory cells in the first...
Apparatuses and method for over-voltage event protection
Circuits, integrated circuits, apparatuses, and methods, such as those for protecting circuits against electrostatic discharge events are disclosed. An example...
Phase change memory cell with constriction structure
Some embodiments include methods of forming memory cells. Such methods can include forming a first electrode, a second electrode, and a memory element directly...
Phase change memory stack with treated sidewalls
Memory devices and methods for fabricating memory devices have been disclosed. One such memory device includes a first electrode material formed on a word line...
Memory cells, semiconductor structures, semiconductor devices, and methods
A magnetic cell includes a magnetic region formed from a precursor magnetic material comprising a diffusive species and at least one other species. An amorphous...
Methods of fabricating fin structures
There is provided fin methods for fabricating fin structures. More specifically, fin structures are formed in a substrate. The fin structures may include two...
Cross-hair cell wordline formation
Methods and devices depicting fabrication of non-planar access devices having fins and narrow trenches, among which is a method that includes wet etching a...
Methods for forming interconnects in microelectronic workpieces and
microelectronic workpieces formed using...
Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces formed using such methods are disclosed herein. One embodiment,...
Program operations with embedded leak checks
Methods of operating a memory device having embedded leak checks may mitigate data loss events due to access line defects, and may facilitate improved power...
Methods of operating a memory device having a buried boosting plate
Memory devices are disclosed, such as those that include a semiconductor-on-insulator (SOI) NAND memory array having a boosting plate. The boosting plate may be...
Dynamically configurable MLC state assignment
Memory devices facilitating a data conditioning scheme for multilevel memory cells. For example, one such memory device is capable of inverting the lower page...
Fast programming memory device
In an embodiment of a memory device including a matrix of memory cells wherein the memory cells are arranged in a plurality of memory cells strings each one...
Systems, and devices, and methods for programming a resistive memory cell
Embodiments disclosed herein may relate to programming a memory cell with a programming pulse that comprises a quenching period having different portions.
Methods and apparatuses having a voltage generator with an adjustable
voltage drop for representing a voltage...
Apparatus and methods utilize a replica circuit to generate a voltage for programming of a memory cell, such as a memory cell of a phase-change memory (PCM)....
Apparatuses having a ferroelectric field-effect transistor memory array
and related method
An apparatus comprises field-effect transistor (FET) structures stacked horizontally and vertically in a three-dimensional memory array architecture, gates...
Memory device command decoding system and memory device and
processor-based system using same
Systems, devices and methods are disclosed. In an embodiment of one such method, a method of decoding received command signals, the method comprises decoding...
Mapping between program states and data patterns
The present disclosure includes methods and apparatuses for mapping between program states and data patterns. One method includes mapping a data pattern to a...
Methods and systems for detection in a state machine
A device including a data analysis element including a plurality of memory cells. The memory cells analyze at least a portion of a data stream and output a...
Reference voltage generator for single-ended communication systems
A reference voltage (V.sub.ref) generator for a single-ended receiver in a communication system is disclosed. The V.sub.ref generator in one example comprises a...
Method, system, and device for heating a phase change memory cell
A memory device, comprising: a phase change material; and an electrode configured to heat the phase change material to change a state of the phase change...
Field effect transistor constructions and memory arrays
In some embodiments, a transistor includes a stack having a bottom source/drain region, a first insulative material, a conductive gate, a second insulative...
Transistors and methods of forming transistors
Some embodiments include a transistor having a drain region and a source region. A conductive gate is between the source and drain regions. First channel...
Methods of forming diodes
Some embodiments include methods of forming diodes in which a first electrode is formed to have a pedestal extending upwardly from a base. At least one layer is...
Semiconductor device structures including metal oxide structures
Methods of forming metal oxide structures and methods of forming metal oxide patterns on a substrate using a block copolymer system formulated for...
Cell pillar structures and integrated flows
Various embodiments comprise apparatuses and methods, such as a memory stack having a continuous cell pillar. In various embodiments, the apparatus includes a...
Manufacturing process for zero-capacitor random access memory circuits
Embodiments of a manufacturing process flow for producing standalone memory devices that can achieve bit cell sizes on the order of 4F2 or 5F2, and that can be...
Methods of fabricating semiconductor structures
Semiconductor structures may include a stack of alternating dielectric materials and control gates, charge storage structures laterally adjacent to the control...
Nanostructures having low defect density and methods of forming thereof
A method of forming nanostructure comprises forming self-assembled nucleic acids on at least a portion of a substrate. The method further comprises contacting...
Apparatuses and methods of reading memory cells based on response to a
The disclosed technology generally relates to memory apparatuses and methods of operating the same, and more particularly to memory arrays and methods of...
Memory cells, non-volatile memory arrays, methods of operating memory
cells, methods of writing to and writing...
In one aspect, a method of operating a memory cell includes using different electrodes to change a programmed state of the memory cell than are used to read the...
Row address decoding block for non-volatile memories and methods for
decoding pre-decoded address information
Decoding blocks, memories, and methods for decoding pre-decoded address information are disclosed. One such decoding block includes a first latch and voltage...
Apparatuses and methods for performing logical operations using sensing
The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an...
Memory system and method using stacked memory device dice, and system
using the memory system
A memory system and method uses stacked memory device dice coupled to each other and to a logic die. The logic die may include a timing correction system that...
Memory, memory controllers, and methods for dynamically switching a data
masking/data bus inversion input
Examples are described herein of dynamic switching of data masking and data bus inversion functionality of a memory input. Both dynamic switching and a static...
Methods and systems for routing in a state machine
A device includes a routing buffer. The routing buffer includes a first port configured to receive a signal relating to an analysis of at least a portion of a...
Memory hub architecture having programmable lane widths
A processor-based system includes a processor coupled to a system controller through a processor bus. The system controller is used to couple at least one input...
Memory address translation
The present disclosure includes devices, systems, and methods for memory address translation. One or more embodiments include a memory array and a controller...
Apparatuses and methods for storing validity masks and operating
Apparatuses and methods for storing a validity mask and operating apparatuses are described. A number of methods for operating an apparatus include storing a...
Photonic device and methods of formation
A photonic device and methods of formation that provide an area providing reduced optical coupling between a substrate and an inner core of the photonic device...
Semiconductor assemblies with multi-level substrates and associated
methods of manufacturing
Various embodiments of semiconductor assemblies with multi-level substrates and associated methods of manufacturing are described below. In one embodiment, a...
Multilayer wiring base plate and probe card using the same
A multilayer wiring base plate includes an insulating plate including a plurality of synthetic resin layers made of an insulating material, a wiring circuit...
Methods for bypassing faulty connections
Apparatus are disclosed, such as those involving a 3-D integrated circuit. One such apparatus includes a first die including a plurality of vertical connectors...
Methods of depositing phase change materials and methods of forming memory
A method of forming a phase change material which having germanium and tellurium therein includes depositing a germanium-containing material over a substrate....
Electronic device, memory cell, and method of flowing electric current
An electronic device includes two conductive electrodes. A first current path extends from one of the electrodes to the other and has a dominant thermally...
Memory cells, methods of fabrication, and semiconductor devices
A magnetic cell includes a magnetic tunnel junction that comprises magnetic and nonmagnetic materials exhibiting hexagonal crystal structures. The hexagonal...
Engineered substrates for semiconductor devices and associated systems and
Engineered substrates for semiconductor devices are disclosed herein. A device in accordance with a particular embodiment includes a transducer structure having...
Circuit structures, memory circuitry, and methods
A circuit structure includes a substrate having an array region and a peripheral region. The substrate in the array and peripheral regions includes insulator...
Self-aligned interconnection for integrated circuits
Methods and structures provide horizontal conductive lines of fine pitch and self-aligned contacts extending from them, where the contacts have at least one...
Method of manufacturing semiconductor device having embedded conductive
Disclosed herein is a method includes: forming first and second cavities, the first cavity having a first width, each of the second cavities having a second...
Stacked semiconductor die assemblies with improved thermal performance and
associated systems and methods
Stacked semiconductor die assemblies with improved thermal performance and associated systems and methods are disclosed herein. In one embodiment, a...