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Patent # Description
US-9,400,309 Electric connecting apparatus
An apparatus includes a probe card having a probe board with a conductive path electrically connected to a tester and probes enabling to respectively contact...
US-9,397,290 Memory cells
Memory cells useful in phase change memory include a phase change material between first and second electrode and having a surface facing a surface of the...
US-9,397,210 Forming air gaps in memory arrays and memory arrays with air gaps thus formed
A memory array has first and second memory cells over a semiconductor and an isolation region extending into the semiconductor. The isolation region includes an...
US-9,397,187 Methods of forming diodes
Some embodiments include methods of forming diodes in which a first electrode is formed to have a pedestal extending upwardly from a base. At least one layer is...
US-9,397,145 Memory structures and related cross-point memory arrays, electronic systems, and methods of forming memory...
A memory structure comprises first conductive lines extending in a first direction over portions of a base structure, storage element structures extending in...
US-9,397,105 Nanodot charge storage structures
Methods, devices, and systems associated with charge storage structures in semiconductor devices are described herein. In one or more embodiments, a method of...
US-9,397,078 Semiconductor device assembly with underfill containment cavity
Semiconductor device assemblies with underfill containment cavities are disclosed herein. In one embodiment, a semiconductor device assembly can include a first...
US-9,396,996 Methods of forming openings in semiconductor structures
A method of forming a semiconductor structure comprises forming pools of acidic or basic material in a substrate structure. A resist is formed over the pools of...
US-9,396,952 Methods of forming transistor gates
Some embodiments include methods of forming charge storage transistor gates and standard FET gates in which common processing is utilized for fabrication of at...
US-9,396,791 Programming memories with multi-level pass signal
Memories and methods for programming memories with multi-level pass signals are provided. One method includes programming cells of the memory selected to be...
US-9,395,927 Outputting a particular data quantization from memory
The present disclosure includes methods, devices, and systems for outputting data particular quantization of data from memory devices and systems. Outputting...
US-9,391,645 Determining soft data using a classification code
Apparatuses and methods for determining soft data using a classification code are provided. One example apparatus can include a classification code (CC) decoder...
US-9,391,206 Methods of forming transistors
Some embodiments include methods of forming transistors. Recesses are formed to extend into semiconductor material. The recesses have upper regions lined with...
US-9,391,092 Circuit structures, memory circuitry, and methods
A circuit structure includes a substrate having an array region and a peripheral region. The substrate in the array and peripheral regions includes insulator...
US-9,391,082 Memory arrays with a memory cell adjacent to a smaller size of a pillar having a greater channel length than a...
The disclosure is related to memory arrays and methods. One such memory array has a substantially vertical pillar. A memory cell adjacent to the pillar where...
US-9,391,062 Apparatuses, circuits, and methods for protection circuits for dual-direction nodes
Apparatuses, circuits, and methods are disclosed for biased protection circuits for dual-direction nodes. In one such example apparatus, a protection circuit is...
US-9,391,001 Semiconductor constructions
Some embodiments include semiconductor constructions having first and second electrically conductive lines that intersect with one another at an intersection....
US-9,390,882 Apparatus having a magnetic lens configured to diverge an electron beam
Apparatus having a magnetic lens configured to diverge an electron beam are useful in three-dimensional imaging using an electron microscope. The magnetic lens...
US-9,390,792 Apparatuses, memories, and methods for address decoding and selecting an access line
Apparatuses, memories, and methods for decoding memory addresses for selecting access lines in a memory are disclosed. An example apparatus includes an address...
US-9,390,770 Apparatuses and methods for accessing memory including sense amplifier sections and coupled sources
Apparatuses and methods for accessing memory are described. An example method includes accessing memory cells of a memory section, and sharing a source of an...
US-9,390,768 Apparatuses, devices and methods for sensing a snapback event in a circuit
Example subject matter disclosed herein relates to apparatuses and/or devices, and/or various methods for use therein, in which an application of an electric...
US-9,390,049 Logical unit address assignment
Described embodiments include logical units within a memory device with control circuitry configured to assign a logical unit address to the logical unit....
US-9,389,841 Methods and systems for using state vector data in a state machine engine
A state machine engine includes a state vector system. The state vector system includes an input buffer configured to receive state vector data from a restore...
US-9,389,833 Method and system to dynamically power-down a block of a pattern-recognition processor
A device includes a pattern-recognition processor. The pattern recognition processor includes blocks, such that each of the blocks include a plurality of...
US-9,385,317 Memory cells and methods of forming memory cells
Some embodiments include a memory cell having a first electrode, and an intermediate material over and directly against the first electrode. The intermediate...
US-9,385,315 Memory cell structures
The present disclosure includes memory cell structures and method of forming the same. One such memory cell includes a first electrode having sidewalls angled...
US-9,385,278 Semiconductor growth substrates and associated systems and methods for die singulation
Semiconductor growth substrates and associated systems and methods for die singulation are disclosed. A representative method for manufacturing semiconductor...
US-9,385,276 Epitaxial devices
Epitaxial growth methods and devices are described that include a textured surface on a substrate. Geometry of the textured surface provides a reduced lattice...
US-9,385,132 Arrays of recessed access devices, methods of forming recessed access gate constructions, and methods of...
A method of forming an array of recessed access device gate constructions includes using the width of an anisotropically etched sidewall spacer in forming mask...
US-9,385,112 Semiconductor devices
A semiconductor device includes a substrate having laterally-adjacent first and second substrate regions. A first isolation region is at least in the first...
US-9,385,045 Methods of forming gated devices
Some embodiments include methods of forming gated devices. An upper region of a semiconductor material is patterned into a plurality of walls that extend...
US-9,384,830 Apparatuses and methods for performing multiple memory operations
The disclosed technology relates to a memory device configured to perform multiple access operations in response to a single command received through a memory...
US-9,384,814 Thyristor memory and methods of operation
Apparatuses and methods can include write schemes for a thyristor memory cell in which an access pulse applied to the gate of the thyristor memory cell is...
US-9,384,799 Advanced memory interfaces and methods
Controllers, interfaces, memory devices, methods and systems are disclosed, including a controller configured to interface with a separate memory device and...
US-9,384,785 Multi-channel memory and power supply-driven channel selection
Subject matter disclosed herein relates to a memory device, and more particularly to a multi-channel memory device and methods of selecting one or more channels...
US-9,384,134 Persistent memory for processor main memory
Subject matter disclosed herein relates to a system of one or more processors that includes persistent memory.
US-9,384,127 Flash memory architecture with separate storage of overhead and user data
A memory device has a plurality of dedicated data blocks for storing user data and a plurality of dedicated overhead blocks for storing overhead data. A...
US-9,379,315 Memory cells, methods of fabrication, semiconductor device structures, and memory systems
Magnetic memory cells, methods of fabrication, semiconductor device structures, and memory systems are disclosed. A magnetic cell core includes at least one...
US-9,379,241 Semiconductor device with strained channels
In various method embodiments, a device region in a semiconductor substrate and isolation regions adjacent to the device region are defined. The device region...
US-9,379,199 Semiconductor device including a contact plug with barrier materials
Disclosed herein is a semiconductor device that comprises a plug including an upper portion, a lower portion and a side surface and comprising tungsten, a...
US-9,379,091 Semiconductor die assemblies and semiconductor devices including same
Methods of fabricating multi-die assemblies including a wafer segment having no integrated circuitry thereon and having a plurality of vertically stacked dice...
US-9,379,005 Three dimensional memory and methods of forming the same
Some embodiments include a memory device and methods of forming the memory device. One such memory device includes a first group of memory cells, each of the...
US-9,378,847 Systems and methods involving managing a problematic memory cell
Subject matter described pertains to managing problematic memory cells in a memory array.
US-9,378,839 Apparatus and methods including source gates
Apparatus and methods are disclosed, such as an apparatus that includes a string of charge storage devices associated with a pillar (e.g., of semiconductor...
US-9,378,823 Programming a memory cell to a voltage to indicate a data value and after a relaxation time programming the...
A memory cell is programmed to at least a first threshold voltage to indicate a particular data value. After waiting for a relaxation time, the memory cell is...
US-9,378,818 Apparatuses and operation methods associated with resistive memory cell arrays with separate select lines
The present disclosure includes methods and apparatuses that include resistive memory. A number of embodiments include a first memory cell coupled to a data...
US-9,378,791 Apparatuses and methods for controlling a clock signal provided to a clock tree
Apparatuses, sense circuits, and methods for controlling a clock signal to a clock tree is described. An example apparatus includes a consecutive write command...
US-9,378,790 Apparatus and method for buffered write commands in a memory
Memories, buffered write command circuits, and methods for executing memory commands in a memory. In some embodiments, read commands that are received after...
US-9,378,783 I/O circuit with phase mixer for slew rate control
An apparatus includes a terminal, a first plurality of driver lines, and a first phase mixer. The driver lines drive the terminal to a first logic state...
US-9,378,774 Interconnection for memory electrodes
Row and/or column electrode lines for a memory device are staggered such that gaps are formed between terminated lines. Vertical interconnection to central...
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