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Patent # Description
US-9,299,742 High-voltage solid-state transducers and associated systems and methods
High-voltage solid-state transducer (SST) devices and associated systems and methods are disclosed herein. An SST device in accordance with a particular...
US-9,299,709 Semiconductor device and semiconductor memory devices having first, second, and third insulating layers
Disclosed herein is a device that includes: a semiconductor substrate; a first insulating layer over a surface of the semiconductor substrate; first and second...
US-9,299,684 Microelectronic device packages, stacked microelectronic device packages, and methods for manufacturing...
A stackable microelectronic package includes a first microelectronic die attached to and electrically connecting with a first substrate. A second ...
US-9,299,663 Semiconductor devices and methods for backside photo alignment
Various embodiments of microelectronic devices and methods of manufacturing are described herein. In one embodiment, a method for aligning an electronic feature...
US-9,299,449 Methods and apparatus for sensing a memory cell
Methods of operating a memory include selectively discharging a data line through a memory cell selected for sensing, discharging a sense node to the data line...
US-9,299,442 Dynamic data caches, decoders and decoding methods
Examples described include dynamic data caches (DDCs), decoders and decoding methods that may fit into a smaller width area. The DDCs, decoders and decoding...
US-9,299,441 Programming and/or erasing a memory device in response to its program and/or erase history
For one embodiment, a programming method includes programming one or more memory cells of a memory device during a programming operation, determining, internal...
US-9,299,440 Methods and apparatuses including a variable termination impedance ratio
Methods of changing a centerline voltage of a data signal are described, along with apparatuses to change the centerline voltage. In one such method, portions...
US-9,299,439 Erasable block segmentation for memory
Various embodiments comprise apparatuses such as those having a block of memory divided into sub-blocks that share a common data line. Each of the sub-blocks of...
US-9,299,437 Apparatuses and methods including memory write operation
Some embodiments include apparatuses and methods having memory cells and access lines coupled to the memory cells. In one such apparatus, the access lines...
US-9,299,423 Optical interconnect in high-speed memory systems
A optical link for achieving electrical isolation between a controller and a memory device is disclosed. The optical link increases the noise immunity of...
US-9,299,416 Semiconductor device having a reduced footprint of wires connecting a DLL circuit with an input/output buffer
An apparatus includes a clock terminal configured to receive an external clock signal, a clock generator configured to generate an internal clock signal in...
US-9,299,406 Apparatuses and methods for providing word line voltages during standby
Apparatuses and methods of providing word line voltages include an example apparatus including a voltage driver and a word line driver. The voltage driver is...
US-9,299,405 Methods for sensing memory elements in semiconductor devices
A memory device that, in certain embodiments, includes a plurality of memory elements connected to a bit-line and a delta-sigma modulator with a digital output...
US-9,298,545 Data protection across multiple memory blocks
Data protection across multiple memory blocks can include writing a first portion of a codeword in a first location of a first memory block and writing a second...
US-9,298,437 Unrolling quantifications to control in-degree and/or out-degree of automaton
Apparatus, systems, and methods for a compiler are disclosed. One such compiler parses a human readable expression into a syntax tree and converts the syntax...
US-9,298,374 Methods of providing access to I/O devices
A method of providing one or more computing devices with access to a plurality of resources. The plurality of resources are provided by at least one physical...
US-D752,762 External transmit modulator for an implantable neural stimulator
US-D752,761 External transit modulator for implantable neural stimulator
US-9,294,105 Delay line off-state control with power reduction
A method and apparatus is provided for controlling a delay line for achieving power reduction. The device comprises a delay lock loop to provide an output...
US-9,294,095 Apparatuses and methods for input buffer having combined output
Apparatuses and methods are disclosed, including an apparatus that includes a first differential amplifier to amplify a difference between an input signal and a...
US-9,294,072 Semiconductor device and method for adjusting impedance of output circuit
An impedance adjustment circuit includes a counter circuit outputting a count value thereof as a plurality of first impedance adjustment signals, a mode...
US-9,293,678 Solid-state light emitters having substrates with thermal and electrical conductivity enhancements and method...
Solid-state lighting devices (SSLDs) including a carrier substrate with conductors and methods of manufacturing SSLDs. The conductors can provide (a) improved...
US-9,293,639 Vertical solid-state transducers and high voltage solid-state transducers having buried contacts and associated...
Solid-state transducers ("SSTs") and vertical high voltage SSTs having buried contacts are disclosed herein. An SST die in accordance with a particular...
US-9,293,638 Self-identifying solid-state transducer modules and associated systems and methods
Self-identifying solid-state transducer (SST) modules and associated systems and methods are disclosed herein. In several embodiments, for example, an SST...
US-9,293,367 Conductive interconnect structures and formation methods using supercritical fluids
Conductive interconnect structures and formation methods using supercritical fluids are disclosed. A method in accordance with one embodiment of the invention...
US-9,293,342 Patterned bases, and patterning methods
Some embodiments include methods of patterning a base. First and second masking features are formed over the base. The first and second masking features include...
US-9,293,328 Semiconductor device structures comprising a polymer bonded to a base material and methods of fabrication
Methods for adhering materials and methods for enhancing adhesion between materials are disclosed. In some embodiments, a polymer brush material is bonded to a...
US-9,293,319 Removal of metal
Methods of removing metal from a portion of a substrate are useful in integrated circuit fabrication. Methods include exposing the substrate to an oxidizing...
US-9,293,214 Determining and using soft data in memory devices and systems
The present disclosure includes methods, devices, and systems for determining and using soft data in memory devices and systems. One or more embodiments include...
US-9,293,213 Sensing data stored in memory
The present disclosure includes apparatuses and methods for sensing data stored in memory. A number of embodiments include an array of memory cells, and a...
US-9,293,196 Memory cells, memory systems, and memory programming methods
Memory cells, memory systems and methods are described. In one embodiment, a memory cell includes electrodes and a memory element, and a first electrically...
US-9,293,191 Apparatuses and methods for multi-memory array accesses
Methods and apparatuses are disclosed for multi-memory array access. One example apparatus includes a pair of input/output lines, and a first array coupled to...
US-9,293,185 Apparatus including a capacitor-less memory cell and related methods
A capacitor-less memory cell, memory device, system and process of forming the capacitor-less memory cell include forming the capacitor-less memory cell in an...
US-9,293,176 Power management
Methods, and apparatus configured to perform such methods, providing peak power management are useful in mitigating excessive current levels within a multi-die...
US-9,293,170 Configurable bandwidth memory devices and methods
Memory devices and methods are described, such as those that include a stack of memory dies and an attached logic die. Method and devices described provide for...
US-9,292,383 Multilevel encoding with error correction
Embodiments of the present disclosure provide methods, systems, and apparatuses related to multilevel encoding with error correction. In some embodiments, a...
US-9,292,382 Codewords that span pages of memory
The present disclosure includes apparatuses and methods for codewords that span pages of memory. A number of methods include writing a first portion of a...
US-9,291,907 Methods for forming resist features and arrays of aligned, elongate resist features
Methods of forming resist features, resist patterns, and arrays of aligned, elongate resist features are disclosed. The methods include addition of a compound,...
US-9,290,857 Methods and apparatus for sorting and/or depositing nanotubes
Methods and apparatus for forming devices using nanotubes. In one embodiment, an apparatus for depositing nanotubes onto a workpiece comprises a vessel...
US-9,287,859 Flexible input/output transceiver
An I/O transceiver includes a driver with a feedback circuit having a mode select signal input, a serial data signal input, and a driver output signal input....
US-9,287,502 Resistance variable memory cell structures and methods
Resistance variable memory cell structures and methods are described herein. One or more resistance variable memory cell structures include a first electrode...
US-9,287,500 Memory cells and methods of forming memory cells
Some embodiments include a memory cell having an electrode and a switching material over the electrode. The electrode is a first composition which includes a...
US-9,287,452 Solid state lighting devices with dielectric insulation and methods of manufacturing
Solid state lighting devices and associated methods of manufacturing are disclosed herein. In one embodiment, a solid state lighting device includes a first...
US-9,287,379 Memory arrays
Some embodiments include a memory array which has a stack of alternating first and second levels. Channel material pillars extend through the stack, and...
US-9,287,284 Semiconductor field-effect transistor, memory cell and memory device
Semiconductor device formed by a first conductive strip of semiconductor material; a control gate region of semiconductor material, facing a channel portion of...
US-9,287,275 Semiconductor constructions
Some embodiments include methods of forming flash memory cells and semiconductor constructions, and some embodiments include semiconductor constructions. Some...
US-9,287,271 Vertical transistor devices, memory arrays, and methods of forming vertical transistor devices
A vertical transistor device includes a line of active area adjacent a line of dielectric isolation. A buried data/sense line obliquely angles relative to the...
US-9,287,260 Transistors having one or more dummy lines with different collective widths coupled thereto
In an embodiment, an array of transistors has a first line coupled to a first transistor. The first line extends over a second transistor that is successively...
US-9,287,240 Stacked semiconductor die assemblies with thermal spacers and associated systems and methods
Stacked semiconductor die assemblies with thermal spacers and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die...
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