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Patent # Description
US-7,157,783 Platinum stuffed with silicon oxide as a diffusion oxygen barrier for semiconductor devices
The present invention provides techniques to fabricate high dielectric MIM storage cell capacitors. In one embodiment, this is accomplished by forming a silicon...
US-7,157,778 Semiconductor constructions
The invention encompasses a method of forming an oxide region over a semiconductor substrate. A nitrogen-containing layer is formed across at least some of the...
US-7,157,775 Semiconductor constructions
The invention includes a semiconductor construction having a pair of channel regions that have sub-regions doped with indium and surrounded by boron. A pair of...
US-7,157,771 Vertical device 4F.sup.2 EEPROM memory
EEPROM memory devices and arrays are described that facilitate the use of vertical floating gate memory cells and select gates in NOR or NAND high density memory...
US-7,157,769 Flash memory having a high-permittivity tunnel dielectric
A high permittivity tunneling dielectric is used in a flash memory cell to provide greater tunneling current into the floating gate with smaller gate voltages....
US-7,157,761 Capacitor with noble metal pattern
An intermediate product for an integrated circuit is disclosed. The intermediate product comprises a first portion of a conductive layer, preferably a layer of...
US-7,157,757 Semiconductor constructions
The invention includes semiconductor constructions, methods of forming gatelines, and methods of forming transistor structures. The invention can include, for...
US-7,157,733 Floating-gate field-effect transistors having doped aluminum oxide dielectrics
Doped aluminum oxide layers having a porous aluminum oxide layer and methods of their fabrication. The porous aluminum oxide layer may be formed by evaporation...
US-7,157,683 Method, apparatus and system providing configurable current source device for image sensors
A configurable current source for imager readout system that can be operated as a simple-current-source or as a cascode-current-source. The configurable current...
US-7,157,387 Techniques to create low K ILD for BEOL
One aspect of the present subject matter relates to a method for forming an interlayer dielectric (ILD). In various embodiments of the method, an insulator layer...
US-7,157,385 Method of depositing a silicon dioxide-comprising layer in the fabrication of integrated circuitry
This invention includes methods of depositing a silicon dioxide comprising layer in the fabrication of integrated circuitry, and to methods of forming trench...
US-7,157,364 Method for forming metal contacts on a substrate
Metal traces and solder bump pads are formed on a semiconductor substrate by way of a semiconductor template that has been micromachined to receive solder paste...
US-7,157,353 Method for fabricating encapsulated semiconductor components
A semiconductor component includes a thinned semiconductor die having protective polymer layers on up to six surfaces. The component also includes contact bumps...
US-7,157,324 Transistor structure having reduced transistor leakage attributes
Undesirable transistor leakage in transistor structures becomes greatly reduced in substrates having a doped implant region formed via pulling back first and...
US-7,157,310 Methods for packaging microfeature devices and microfeature devices formed by such methods
Methods for packaging microfeature devices on and/or in microfeature workpieces at the wafer level and microfeature devices that are formed using such methods...
US-7,157,305 Forming multi-layer memory arrays
A method of forming a memory array includes forming a stack of two or more layers of memory material on a substrate, each layer of memory material having an...
US-7,157,302 Imaging device and method of manufacture
An imaging chip is packaged in transparent injection molded material. The chip may have photosensitive elements arranged in a two-dimensional array on...
US-7,156,727 Web-format polishing pads and methods for manufacturing and using web-format polishing pads in mechanical and...
A web-format polishing pad for mechanical and/or chemical-mechanical planarization of microelectronic substrate assemblies, and methods for making and using such...
US-7,156,633 Apparatus for encapsulating a multi-chip substrate array
A mold apparatus for encapsulating IC chips mounted on a substrate. In an exemplary embodiment a mold is provided with an upper mold platen having a plurality of...
US-7,156,362 Method and apparatus for forming metal contacts on a substrate
Solder bump pads are formed on a semiconductor substrate by way of a semiconductor template that has been micromachined to receive solder paste material. The...
US-7,156,361 Method and apparatus for forming metal contacts on a substrate
Metal traces and solder bump pads are formed on a semiconductor substrate by way of a semiconductor template that has been micromachined to receive solder paste...
US-7,155,644 Automatic test entry termination in a memory device
A memory device has a control register comprising a test mode disable bit. The test mode is initially enabled. If the device does not receive an appropriate key...
US-7,155,630 Method and unit for selectively enabling an input buffer based on an indication of a clock transition
A system unit including a processor unit and an input storage unit. The processor unit generates an input signal and a clock signal. The input storage unit...
US-7,155,589 Permanent memory block protection in a flash memory device
A secure command is entered into a Flash memory device. A control data word is written to the memory device to specify which blocks of memory are to be...
US-7,155,565 Automatic learning in a CAM
A CAM array which enables a learning process to be an extension of a search process is disclosed. When a search fails to find a matching data in the CAM array,...
US-7,155,562 Method for reading while writing to a single partition flash memory
A device manager receives an operation request for a memory device. The device manager suspends interrupts to be serviced and determines if there is sufficient...
US-7,155,561 Method and system for using dynamic random access memory as cache memory
A cache memory system and method includes a DRAM having a plurality of banks, and it also includes 2 SRAMs each having a capacity that is equal to the capacity...
US-7,155,391 Systems and methods for speech recognition and separate dialect identification
A speech-to-text conversion system. The two-way speech recognition and dialect system comprises a computer system, an attached microphone assembly, and...
US-7,155,300 Method for using data regarding manufacturing procedures integrated circuits (IC's) have undergone, such as...
An inventive method in an integrated circuit (IC) manufacturing process for using data regarding repair procedures conducted on IC's at probe to determine...
US-7,154,800 No-precharge FAMOS cell and latch circuit in a memory device
The fuse and latch circuit has a Floating gate Avalanche injection Metal Oxide Semiconductor (FAMOS) transistor (fuse) that is coupled to a read circuit. The...
US-7,154,785 Charge pump circuitry having adjustable current outputs
Methods and apparatus are provided. A memory device includes charge pump circuitry having a plurality of parallel charge pumps for supplying a programming...
US-7,154,782 Contiguous block addressing scheme
An improved non-volatile erase block memory device apparatus and method is described that incorporates an improved addressing scheme to provide for extended...
US-7,154,781 Contiguous block addressing scheme
An improved non-volatile erase block memory device apparatus and method is described that incorporates an improved addressing scheme to provide for extended...
US-7,154,780 Contiguous block addressing scheme
An improved non-volatile erase block memory device apparatus and method is described that incorporates an improved addressing scheme to provide for extended...
US-7,154,778 Nanocrystal write once read only memory for archival storage
Structures and methods for write once read only memory employing charge trapping are provided. The write once read only memory cell includes a metal oxide...
US-7,154,546 Pixel optimization for color
A macro pixel is provided. The macro pixel includes at least two color pixel elements. Each color pixel element includes a photoreceptor that in response to...
US-7,154,354 High permeability layered magnetic films to reduce noise in high speed interconnection
A structure for magnetically shielded transmission lines for use with high speed integrated circuits having an improved signal to noise ratio, and a method for...
US-7,154,289 Input buffer with automatic switching point adjustment circuitry, and synchronous dram device including same
An input buffer is presented for buffering an input signal having a voltage magnitude which alternates between a first voltage level and a second voltage level,...
US-7,154,153 Memory device
A floating gate transistor has a reduced barrier energy at an interface with an adjacent gate insulator, allowing faster charge transfer across the gate...
US-7,154,146 Dielectric plug in mosfets to suppress short-channel effects
The invention provides a technique to fabricate a dielectric plug in a MOSFET. The invention includes apparatus and systems that include one or more devices...
US-7,154,140 Write once read only memory with large work function floating gates
Structures and methods for write once read only memory employing floating gates are provided. The write once read only memory cell includes a floating gate...
US-7,154,136 Isolation structures for preventing photons and carriers from reaching active areas and methods of formation
Regions of an integrated circuit are isolated by a structure that includes at least one isolating trench on the periphery of an active area. The trench is deep,...
US-7,154,078 Differential column readout scheme for CMOS APS pixels
The present invention provides an improved column readout circuitry and method of operation which minimizes substrate and other common mode noise during a read...
US-7,154,075 Method and apparatus for pixel signal binning and interpolation in column circuits of a sensor circuit
A binning circuit and related method, wherein pixel signals from column circuits in a sensor circuit are sampled and interpolated. The binning circuit samples...
US-7,153,788 Method and apparatus for attaching a workpiece to a workpiece support
A method for attaching a workpiece, for example a semiconductor die, to a workpiece holder, for example a lead frame die support, comprises the steps of...
US-7,153,779 Method to eliminate striations and surface roughness caused by dry etch
A plasma etch process for forming a high aspect ratio contact opening through a silicon oxide layer is disclosed. The silicon oxide layer is plasma etched using...
US-7,153,778 Methods of forming openings, and methods of forming container capacitors
A patterned mask can be formed as follows. A first patterned photoresist is formed over a masking layer and utilized during a first etch into the masking layer....
US-7,153,777 Methods and apparatuses for electrochemical-mechanical polishing
Methods and apparatuses for removing material from a microfeature workpiece are disclosed. In one embodiment, the microfeature workpiece is contacted with a...
US-7,153,775 Conductive material patterning methods
A patterning method includes providing a first material (e.g., copper) and transforming at a least a surface region of the first material to a second material...
US-7,153,769 Methods of forming a reaction product and methods of forming a conductive metal silicide by reaction of metal...
A method of forming a reaction product includes providing a semiconductor substrate comprising a first material. A second material is formed over the first...
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