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Patent # Description
US-7,129,738 Method and apparatus for calibrating driver impedance
The present invention provides a method and apparatus is provided for calibrating a driver impedance in an integrated circuit device. The method includes...
US-7,129,725 Semiconductor test interconnect with variable flexure contacts having polymer material
An interconnect for testing semiconductor components includes a substrate, and interconnect contacts on the substrate for electrically engaging terminal contacts...
US-7,129,724 Plasma probe
A plasma probe includes a substrate having substantially the same properties as those of a substrate to be processed, a bottom electrode layer located over the...
US-7,129,631 Black matrix for flat panel field emission displays
A flat panel field emission device includes a black matrix formed from an electrically insulative material such as praseodymium-manganese oxide. The insulative...
US-7,129,584 Elimination of RDL using tape base flip chip on flex for die stacking
A flexible film interposer for stacking a flip chip semiconductor die onto a second (bottom) semiconductor die, semiconductor devices and stacked die assemblies...
US-7,129,573 System having semiconductor component with encapsulated, bonded, interconnect contacts
A semiconductor component includes a die having a pattern of die contacts, and interconnect contacts bonded to the die contacts and encapsulated in an insulating...
US-7,129,567 Substrate, semiconductor die, multichip module, and system including a via structure comprising a plurality of...
Methods of forming at least one multiconductor via are disclosed. Specifically, a substrate may be provided and at least one through-hole may be formed...
US-7,129,553 Lanthanide oxide/hafnium oxide dielectrics
Dielectric layers containing a chemical vapor deposited hafnium oxide and an electron beam evaporated lanthanide oxide and a method of fabricating such a...
US-7,129,535 Capacitor constructions
The invention includes methods in which metal oxide dielectric materials are deposited over barrier layers. The barrier layers can comprise compositions of metal...
US-7,129,534 Magneto-resistive memory and method of manufacturing the same
A method of forming a magneto-resistive memory element includes forming a groove in a layer of insulating material. A liner is formed conformably within the...
US-7,129,457 Redundant imaging systems
Imaging arrays typically include thousands or millions of photodetectors that convert sensed light into corresponding electric signals, which are ultimately...
US-7,129,188 Transistor fabrication methods
A transistor gate is formed which comprises semiconductive material and conductive metal. Source/drain regions are formed proximate the transistor gate. In one...
US-7,129,180 Masking structure having multiple layers including an amorphous carbon layer
A masking structure having multiple layers is formed. The masking structure includes an amorphous carbon layer and a cap layer formed over the amorphous carbon...
US-7,129,160 Method for simultaneously removing multiple conductive materials from microelectronic substrates
A method and apparatus for simultaneously removing conductive materials from a microelectronic substrate. A method in accordance with one embodiment of the...
US-7,129,156 Method for fabricating a silicon carbide interconnect for semiconductor components using heating
An interconnect for semiconductor components includes a substrate, and interconnect contacts on the substrate for electrically engaging component contacts on the...
US-7,129,128 Method of improved high K dielectric-polysilicon interface for CMOS devices
Methods for forming dielectric layers over polysilicon substrates, useful in the construction of capacitors and other semiconductor circuit components are...
US-7,129,114 Methods relating to singulating semiconductor wafers and wafer scale assemblies
Methods relating to the singulation of dice from semiconductor wafers. Trenches or channels are formed in the bottom surface of a semiconductor wafer,...
US-7,128,842 Polyimide as a mask in vapor hydrogen fluoride etching
A layer of polyimide or polysilicon is used as a mask in vapor hydrogen fluoride etching. Both non-photosensitive and photosensitive type polyimide may be used....
US-7,128,787 Atomic layer deposition method
An atomic layer deposition method includes positioning a semiconductor substrate within an atomic layer deposition chamber. A first precursor gas is flowed to...
US-7,128,551 Surface smoothing of stereolithographically formed 3-D objects
A stereolithographic method and apparatus for forming polymeric structures comprising a plurality of overlying layers, each layer formed by polymerizing a thin...
US-7,127,622 Memory subsystem voltage control and method
A method and apparatus for providing a preferred operating voltage to a memory device as specified by a stored configuration parameter. The apparatus includes a...
US-7,127,559 Caching of dynamic arrays
Systems and methods are provided for caching dynamic arrays. According to one aspect, a cache memory device is provided for caching dynamic arrays or dynamic...
US-7,127,365 Method for identifying a defective die site
The present invention relates to the marking and identification of defective die sites on a mounting substrate. A mounting substrate is provided which is...
US-7,127,319 Reducing asymmetrically deposited film induced registration error
Methods, systems, products and apparatuses are disclosed herein relating to registration and asymmetrically deposited films, and more specifically, to reducing...
US-7,126,874 Memory system and method for strobing data, command and address signals
A memory system couples command, address or write data signals from a memory controller to a memory device and read data signals from the memory device to the...
US-7,126,871 Circuits and methods to protect a gate dielectric antifuse
According to embodiments of the present invention, an antifuse circuit is operated by coupling an elevated voltage to a first terminal of an antifuse,...
US-7,126,863 Active termination control
A method and apparatus are provided for active termination control in a memory. The memory turns on active termination based on information programmed into one...
US-7,126,394 History-based slew rate control to reduce intersymbol interference
In one aspect of the invention, a method of reducing intersymbol interference on a signal line is disclosed. A state machine records previous bits that were...
US-7,126,393 Delay circuit with reset-based forward path static delay
A delay locked loop circuit and method of operating the same. The delay locked loop circuit comprises a forward delay path having a variable delay portion and a...
US-7,126,380 Distributed clock generator for semiconductor devices and related methods of operating semiconductor devices
A distributed clock generator for a semiconductor device. In one embodiment, the clock generator is not localized in one particular location on the semiconductor...
US-7,126,317 Apparatus and methods for regulated voltage
An electronic system according to various aspects of the present invention includes a memory and a supply regulation circuit having a regulated output to provide...
US-7,126,228 Apparatus for processing semiconductor devices in a singulated form
Improved methods and apparatus are provided for the handling and testing of semiconductor devices. One embodiment comprises a die carrier for one or more...
US-7,126,224 Semiconductor substrate-based interconnection assembly for semiconductor device bearing external connection...
The present invention relates to a method of forming interconnections for a temporary package, wherein the interconnections are capable of receiving solder balls...
US-7,126,205 Devices having improved capacitance and methods of their fabrication
A capacitor formed by a process using only two deposition steps and a dielectric formed by oxidizing a metal layer in an electrolytic solution. The capacitor has...
US-7,126,200 Integrated circuits with contemporaneously formed array electrodes and logic interconnects
The invention relates to interconnects for an integrated circuit memory device. Embodiments of the invention include processes to fabricate interconnects for...
US-7,126,195 Method for forming a metallization layer
A method for forming a metallization layer (30). A first layer (14) is formed outwardly from a semiconductor substrate (10). Contact vias (16) are formed through...
US-7,126,183 Programmable array logic or memory with p-channel devices and asymmetrical tunnel barriers
Structures and methods for programmable array type logic and/or memory with p-channel devices and asymmetrical low tunnel barrier intergate insulators are...
US-7,126,182 Memory circuitry
The invention includes memory circuitry. In one implementation, memory circuitry includes a memory array comprising a plurality of memory cell capacitors....
US-7,126,181 Capacitor constructions
The invention includes methods of forming circuit devices. A metal-containing material comprising a thickness of no more than 20 .ANG. (or alternatively...
US-7,126,179 Memory cell intermediate structure
A method of filling vias for a PCRAM cell with a metal is described. A PCRAM intermediate structure including a substrate, a first conductor, and an insulator...
US-7,125,815 Methods of forming a phosphorous doped silicon dioxide comprising layer
This invention includes methods of forming phosphorus doped silicon dioxide comprising layers, and methods of forming trench isolation in the fabrication of...
US-7,125,809 Method and material for removing etch residue from high aspect ratio contact surfaces
Contact openings in semiconductor substrates are formed through insulative layers using an etchant material. The etchant typically leaves behind a layer of etch...
US-7,125,804 Etching methods and apparatus and substrate assemblies produced therewith
Methods and apparatus for etching substrates such as silicon wafers are provided. In one specific approach, a surface of the substrate assembly is covered with a...
US-7,125,800 Methods for making nearly planar dielectric films in integrated circuits
In the fabrication of integrated circuits, one specific technique for making surfaces flat is chemical-mechanical planarization. However, this technique is quite...
US-7,125,781 Methods of forming capacitor devices
The invention includes semiconductor constructions, and also includes methods of forming pluralities of capacitor devices. An exemplary method of the invention...
US-7,125,768 Method for reducing single bit data loss in a memory circuit
The present invention includes a method for reducing random bit data loss in a memory circuit. The method comprises a semiconductor layer that has a surface. The...
US-7,125,749 Varied-thickness heat sink for integrated circuit (IC) packages and method of fabricating IC packages
An integrated circuit package includes a package body, such as a transfer molded plastic or preformed ceramic package body, having an integrated circuit die...
US-7,125,748 Methods of encapsulating selected locations of a semiconductor die assembly using a thick solder mask
A solder mask includes an opening through which intermediate conductive elements may be positioned to connect bond pads of a semiconductor die exposed through an...
US-7,124,384 Capacitor layout technique for reduction of fixed pattern noise in a CMOS sensor
A new capacitor architecture includes a front plate of the capacitor formed form a first polysilicon layer. The front plate is surround by a first dielectric...
US-7,124,260 Modified persistent auto precharge command protocol system and method for memory devices
A method of operating a memory device includes placing the memory device in a persistent auto precharge mode of operation, applying a disable command to the...
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