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Patent # Description
US-7,244,648 Methods of forming semiconductor constructions
The invention encompasses a method of forming a silicon nitride layer. A substrate is provided which comprises a first mass and a second mass. The first mass...
US-7,244,646 Pixel design to improve photodiode capacitance and method of forming same
A CMOS imager with two adjacent pixel active area regions without the presence of an intervening trench isolation region that typically separates two adjacent...
US-7,244,637 Chip on board and heat sink attachment methods
A process for forming a thermally enhanced Chip On Board semiconductor device with a heat sink is described. In one aspect, a thermally conductive-filled gel...
US-7,243,290 Data encoding for fast CAM and TCAM access times
A method and apparatus for operating a content addressable memory (CAM) and a ternary CAM (TCAM) are described including an encoding circuit for encoding an...
US-7,242,603 Method of operating a complementary bit resistance memory sensor
The present invention relates to a method and apparatus for sensing the resistance state of a programmable resistance memory, using complementary memory...
US-7,242,332 Column-parallel sigma-delta analog-to-digital conversion with gain and offset control
A sigma-delta modulation sensing circuit and an analog-to-digital converter for an imager that eliminate the erroneous conversion of non-zero analog voltages to...
US-7,242,213 Memory module and method having improved signal routing topology
A registered memory module includes several memory devices coupled to a register through a plurality of transmission lines forming a symmetrical tree topology....
US-7,242,067 MRAM sense layer isolation
A process for forming an MRAM element. The process comprises patterning a globally deposited sense layer and then forming a spacer about the patterned sense...
US-7,242,057 Vertical transistor structures having vertical-surrounding-gates with self-aligned features
The present inventions include a vertical transistor formed by defining a channel length of the vertical-surrounding-gate field effect transistor with...
US-7,242,049 Memory device
A floating gate transistor has a reduced barrier energy at an interface with an adjacent gate insulator, allowing faster charge transfer across the gate...
US-7,241,705 Methods of forming conductive contacts to source/drain regions and methods of forming local interconnects
The invention comprises methods of forming a conductive contact to a source/drain region of a field effect transistor, and methods of forming local...
US-7,241,673 Methods of forming silicon-doped aluminum oxide, and methods of forming transistors and memory devices
The invention encompasses a method of forming a silicon-doped aluminum oxide. Aluminum oxide and silicon monoxide are co-evaporated. Subsequently, at least some...
US-7,241,662 Reduction of field edge thinning in peripheral devices
A dielectric layer (e.g., an interpoly dielectric layer) is deposited over low and high voltage devices of a peripheral memory device. The dielectric behaves as...
US-7,241,661 Method of forming a coupling dielectric Ta.sub.2O.sub.5 in a memory device
A method of forming a coupling dielectric in a memory cell includes forming an oxide on a substrate, forming Ta.sub.2O.sub.5 on the oxide, oxidizing the...
US-7,241,658 Vertical gain cell
A high density vertical gain cell is realized for memory operation. The gain cell includes a vertical MOS transistor used as a sense transistor having a floating...
US-7,241,655 Method of fabricating a vertical wrap-around-gate field-effect-transistor for high density, low voltage logic...
A vertical transistor having a wrap-around-gate and a method of fabricating such a transistor. The wrap-around-gate (WAG) vertical transistors are fabricated by...
US-7,241,654 Vertical NROM NAND flash memory array
Memory devices, arrays, and strings are described that facilitate the use of NROM memory cells in NAND architecture memory strings, arrays, and devices. NROM...
US-D546,275 Electroacoustic transducer
US-D546,274 Electroacoustic transducer
US-7,240,316 Apparatus and method to facilitate hierarchical netlist checking
An apparatus and method are disclosed which determine locations where verification data should exist in a circuit representation and then propagates verification...
US-7,240,148 Parity-scanning and refresh in dynamic memory devices
A method and apparatus that coordinates refresh and parity-scanning in DRAM-based devices such that parity-scan operations substitute for refresh operations when...
US-7,240,147 Memory decoder and data bus for burst page read
Memory device is described that utilizes a reduced number of sense amplifiers to sense the data bits of a selected column page. The sense amplifiers are...
US-7,240,146 Random access interface in a serial memory device
A random access interface is provided to a non-volatile, serial memory array. An address multiplexer has an external address connection and a serial address...
US-7,239,933 Substrate supports for use with programmable material consolidation apparatus and systems
A programmed material consolidation apparatus includes at least one fabrication site and a material consolidation system associated with the at least one...
US-7,239,932 Methods and apparatus for calibrating programmable material consolidation apparatus
A programmed material consolidation apparatus includes at least one fabrication site and a material consolidation system associated with the at least one...
US-7,239,575 Delay-locked loop having a pre-shift phase detector
A clock generator for generating an output clock signal synchronized with an input clock signal having first and second adjustable delay lines. The first...
US-7,239,557 Program method with optimized voltage level for flash memory
A non-volatile memory device and programming process is described that increases the programming voltage of successive programming cycles in relation to the...
US-7,239,552 Non-volatile one time programmable memory
A verify operation is performed on the one time programmable memory block to determine if it has been programmed. If any bits have been programmed, further...
US-7,239,381 Particle detection method
A method for detecting on a substrate used in the fabrication of integrated devices comprises the steps of (1) contacting the substrate with a monomer, wherein...
US-7,239,152 Methods for measuring parasitic capacitance and inductance of I/O leads on an electrical component using a...
Apparatus and methods are provided for measuring the potential for mutual coupling in an integrated circuit package of any type or configuration using a network...
US-7,239,075 Nitrogen and phosphorus doped amorphous silicon as resistor for field emission display device baseplate
Described herein is a resistor layer for use in field emission display devices and the like, and its method of manufacture. The resistor layer is an amorphous...
US-7,239,029 Packages for semiconductor die
A ball grid array assembly includes a package cover that encapsulates a die and a portion of a substrate to which the die is attached, including an edge of the...
US-7,239,025 Selective deposition of solder ball contacts
Methods of forming solder ball contacts having dimensions of approximately 2.5 microns in diameter for use in C4-type connections. The methods form solder ball...
US-7,239,015 Heat sinks including nonlinear passageways
A stereolithographically fabricated heat sink may include non-linear, or convoluted passageways therethrough, through which air can flow. The heat sink may also...
US-7,239,003 Isolation techniques for reducing dark current in CMOS image sensors
Isolation methods and devices for isolating regions of a semiconductor device. The isolation method and structure include forming an isolating trench in an...
US-7,238,981 Metal-poly integrated capacitor structure
A metal-poly integrated capacitor structure that may be used in a charge pump circuit of a non-volatile memory. In one embodiment, the capacitor comprises a poly...
US-7,238,977 Wide dynamic range sensor having a pinned diode with multiple pinned voltages
A pixel cell has controlled photosensor anti-blooming leakage by having dual pinned voltage regions, one of which is used to set the anti-blooming...
US-7,238,616 Photo-assisted method for semiconductor fabrication
The present invention provides a processing system comprising a remote plasma activation region for formation of active gas species, a transparent transfer tube...
US-7,238,613 Diffusion-enhanced crystallization of amorphous materials to improve surface roughness
Methods of forming a roughened surface through diffusion-enhanced crystallization of an amorphous material are disclosed. In one aspect, conductive hemispherical...
US-7,238,599 Multi-state NROM device
An array of NROM flash memory cells configured to store at least two bits per four F.sup.2. Split vertical channels are generated along each side of adjacent...
US-7,238,544 Imaging with gate controlled charge storage
A pixel cell comprises a photo-conversion device for generating charge and a gate controlled charge storage region for storing photo-generated charge under...
US-7,238,543 Methods for marking a bare semiconductor die including applying a tape having energy-markable properties
A method used for marking a semiconductor wafer or device. The method and apparatus have particular application to wafers or devices which have been subjected to...
US-7,237,172 Error detection and correction in a CAM
An error detection and correction circuit is connected to at least one memory bank of a CAM device. During background processing (i.e., when the CAM is not...
US-7,237,158 Intelligent binning for electrically repairable semiconductor chips
The present invention relates to a system and method for testing one or more semiconductor devices (e.g., packaged chips). Test equipment performs at least tests...
US-7,237,155 Testing method for permanent electrical removal of an intergrated circuit output after packaging
An apparatus and method of disconnecting or disabling an input/output terminal of an integrated circuit after packaging. Each input/output terminal of the...
US-7,237,136 Method and apparatus for providing symmetrical output data for a double data rate DRAM
An apparatus and method is disclosed to compensate for skew and asymmetry of a locally processed system clock used to synchronize an output signal, e.g., a data...
US-7,236,415 Sample and hold memory sense amplifier
A memory sense amplifier includes a sample and hold circuit followed by a differential amplifier. The sample and hold circuit samples a reference voltage on a...
US-7,236,407 Flash memory architecture for optimizing performance of memory having multi-level memory cells
A flash memory device having a pipelined RAS/CAS architecture is logically organized as an array of rows and columns of multi-bit flash memory cells each capable...
US-7,236,400 Erase verify for non-volatile memory using a bitline current-to-voltage converter
A memory device verify system determines a state of memory cells in a memory. The memory includes a memory array having a plurality of memory cells coupled to...
US-7,236,399 Method for erase-verifying a non-volatile memory capable of identifying over-erased and under-erased memory cells
A memory device verify system determines a state of memory cells in a memory. The memory includes a memory array having a plurality of memory cells coupled to...
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