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Patent # Description
US-7,145,228 Microelectronic devices
Methods for packaging microelectronic devices and microelectronic devices formed by such methods are disclosed herein. In one embodiment, a method includes...
US-7,145,225 Interposer configured to reduce the profiles of semiconductor device assemblies and packages including the same...
An interposer includes a substrate, first and second sets of contact pads carried by the substrate, and receptacles formed in a surface of the substrate and...
US-7,145,189 Photon amplification for image sensors
A pixel cell having a substrate, photo-conversion device, and at least one dielectric layer over the photo-conversion device. The at least one dielectric layer...
US-7,145,186 Memory cell with trenched gated thyristor
One aspect of this disclosure relates to a memory cell. Various memory cell embodiments include an isolated semiconductor region separated from a bulk...
US-7,144,810 Methods for forming rough ruthenium-containing layers and structures/methods using same
A method for forming a rough ruthenium-containing layer on the surface of a substrate assembly includes providing a ruthenium-containing precursor into the...
US-7,144,779 Method of forming epitaxial silicon-comprising material
The invention includes methods of forming epitaxial silicon-comprising material and methods of forming vertical transistors. In one implementation, a method of...
US-7,144,690 Photolithographic methods of using a single reticle to form overlapping patterns
The invention includes a photolithographic method in which overlapping first and second exposure patterns are formed on a photosensitive material from light...
US-7,144,304 Method and apparatus for planarizing a microelectronic substrate with a tilted planarizing surface
A method and apparatus for planarizing a microelectronic substrate. In one embodiment, the apparatus can include an elongated, non-continuous polishing pad...
US-7,144,245 Packages for semiconductor die
A ball grid array assembly includes a package cover that encapsulates a die and a portion of a substrate to which the die is attached, including an edge of the...
US-7,143,500 Method to prevent damage to probe card
Probe cards are configured with protective circuitry suitable for use in electrical testing of semiconductor dice without damage to the probe cards. Protective...
US-7,143,255 Chip protection register lock circuit in a flash memory device
A chip protection register lock circuit uses a plurality of lock bits in a lock bit register. If the register contains N bits, N/2 bits of the register are...
US-7,142,838 Wake up device for a communications system
The present invention teaches a communications system comprising a first communications device for receiving data and a wake up signal. The first communications...
US-7,142,577 Method of forming mirrors by surface transformation of empty spaces in solid state materials and structures thereon
A multi-layered reflective mirror formed of spaced-apart plate-shaped empty space patterns formed within a substrate is disclosed. The plurality of plate-shaped...
US-7,142,543 High speed programmable counter
A digital counter allows the provision of start and stop values in order to allow it to be configurable to any length. The counter rolls over to zero at a...
US-7,142,461 Active termination control though on module register
A method and apparatus are provided for active termination control in a memory by a module register providing an active termination control signal to the memory....
US-7,142,459 Programming flash memories
A flash memory device has an array of flash memory cells, a detector for detecting an external voltage applied to the flash memory device, and a command control...
US-7,142,446 Apparatus and method to reduce undesirable effects caused by a fault in a memory device
A method and apparatus is provided for reducing the current in a memory device. Peripheral device control signals are translated to the wordline off voltage...
US-7,142,443 Reduced data line pre-fetch scheme
A memory device for reducing the number of data read lines needed in a memory device. Specifically, multiple helper flip-flops are used to prefetch data in a...
US-7,142,234 Method for mismatch detection between the frequency of illumination source and the duration of optical...
A method for achieving flickerless operation of imagers using a rolling shutter, including the steps of detecting flicker in an image frame and adjusting an...
US-7,141,997 Method for testing using a universal wafer carrier for wafer level die burn-in
A reusable burn-in/test fixture for testing unsingulated dice on a semiconductor wafer consisting of two halves. The first half of the test fixture is a wafer...
US-7,141,994 Air socket for testing integrated circuits
An electrical component testing device comprising a housing having at least one recess covered by a flexible membrane so as to form a chamber. A fluid passage...
US-7,141,850 Gated semiconductor assemblies and methods of forming gated semiconductor assemblies
In one aspect, the invention includes a method of forming a gated semiconductor assembly, comprising: a) forming a silicon nitride layer over and against a...
US-7,141,847 DRAM constructions, memory arrays and semiconductor constructions
The invention includes a method of depositing a noble metal. A substrate is provided. The substrate has a first region and a second region. The first and second...
US-7,141,841 Image sensor having a transistor for allowing increased dynamic range
Embodiments of the invention provide an image sensor having an improved dynamic range. A pixel cell comprises at least one transistor structure. The transistor...
US-7,141,824 Transistor with variable electron affinity gate
A SiC material composition is selected to establish the barrier energy between the SIC gate and a gate insulator. Various embodiments of selected SiC material...
US-7,141,511 Method and apparatus for fabricating a memory device with a dielectric etch stop layer
The present technique relates to a method and apparatus to provide a dielectric etch stop layer that prevents shorts for a buried digit layer as an interconnect....
US-7,141,472 Semiconductor processing methods of forming dynamic random access memory (DRAM) circuitry
Methods of forming dynamic random access memories (DRAM) are described. In one embodiment, an insulative layer is formed over a substrate having a plurality of...
US-7,140,122 Vacuum treatment of waste stream with anti-incrustation measures
A method of treating a waste stream comprises a vacuum treatment to promote disintegration of the waste material by "flash vapor" production, causing a swiftly...
US-RE39,413 Low friction polish-stop stratum for endpointing chemical-mechanical planarization processing of semiconductor...
The present invention is a semiconductor wafer that enhances polish-stop endpointing in chemical-mechanical planarization processes. The semiconductor wafer has...
US-7,139,896 Linear and non-linear object management
A linear and non-linear object management method and structure. A data structure on a computer-readable medium is used to store linear and non-linear objects in...
US-7,139,893 Transparent SDRAM in an embedded environment
A transparent memory array has a processor and a plurality of memory banks, each memory bank being directly connected to the processor. The memory array has...
US-7,139,867 Partially-ordered cams used in ternary hierarchical address searching/sorting
An apparatus and method that utilizes partial ordering of ternary hierarchical addresses and their associated masks entries in both binary and ternary content...
US-7,139,866 CAM with automatic writing to the next free address
A method and apparatus for automatically writing non-matching data to a non-valid location within a Content Addressable Memory (CAM) is disclosed. The non-valid...
US-7,139,852 Memory bus polarity indicator system and method for reducing the affects of simultaneous switching outputs...
A method and system transfer read data from a memory device having a data bus and a data masking pin adapted to receive a masking signal during write operations...
US-7,139,672 Dynamically adaptable semiconductor parametric testing
An apparatus, method, system, and signal-bearing medium may provide multiple maps, which may include multiple probing sequences to be called upon at run-time...
US-7,139,345 Method and circuit for adjusting the timing of output data based on the current and future states of the output...
A clock synchronization circuit receives an input clock signal along with current and future data signals. The clock synchronization circuit generates a phase...
US-7,139,209 Zero-enabled fuse-set
A method, apparatus, and system are provided for implementing a zero-enabled fuse system. An apparatus includes a first set of fuses for activating a first...
US-7,139,203 Voltage regulator and data path for a memory device
A method and apparatus provide unbalanced output drive capability, for example, to correct for output skews in subsequent output stages. In one aspect, a...
US-7,139,188 Memory architecture and method of manufacture and operation thereof
An architecture, and its method of formation and operation, containing a high density memory array of semi-volatile or non-volatile memory elements, including,...
US-7,139,182 Cutting CAM peak power by clock regioning
A CAM device architecture where CAM cells are divided into at least two arrays and each array is operated in a different clock domain so that at no time are the...
US-7,139,025 Active pixel sensor with mixed analog and digital signal integration
An active pixel sensor includes mixed analog and digital signal integration on the same substrate. The analog part of the array forms the active pixel sensor,...
US-7,138,845 Method and apparatus to set a tuning range for an analog delay
An apparatus and method for an analog fine delay line, a hybrid delay line, and a delay locked loop (DLL) is described. In the DLL, a coarse phase detector...
US-7,138,823 Apparatus and method for independent control of on-die termination for output buffers of a memory device
An apparatus and method providing independent control of on-die termination (ODT) of output buffers. The ODTs for the buffer circuits of an input/output (I/O)...
US-7,138,724 Thick solder mask for confining encapsulant material over selected locations of a substrate and assemblies...
A solder mask includes an opening through which intermediate conductive elements may be positioned to connect bond pads of a semiconductor die exposed through an...
US-7,138,719 Trench interconnect structure and formation method
Embodiments concern vertical interconnect structures having sub-micron widths for use in integrated circuits, and methods of their manufacture, which result in...
US-7,138,718 Multilevel interconnect structure with low-k dielectric
A multilevel interconnect structure with a low-k dielectric constant is fabricated in an integrated circuit structure by the steps of depositing a layer of...
US-7,138,711 Intrinsic thermal enhancement for FBGA package
A semiconductor device for dissipating heat generated by a die during operation and having a low height profile, a semiconductor die package incorporating the...
US-7,138,681 High density stepped, non-planar nitride read only memory
A non-planar, stepped NROM array is comprised of cells formed in trenches and on pillars that are etched into a substrate. Each cell has a plurality of charge...
US-7,138,653 Structures for stabilizing semiconductor devices relative to test substrates and methods for fabricating the...
Stabilizers to be disposed on a surface of a semiconductor device or test substrate and methods of fabricating and disposing the stabilizers on semiconductor...
US-7,138,334 Systems for forming insulative coatings for via holes in semiconductor devices
An insulative coating for an aperture of a semiconductor device component includes a plurality of adjacent, mutually adhered regions. The adjacent, mutually...
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