Easy To Use Patents Search & Patent Lawyer Directory

At Patents you can conduct a Patent Search, File a Patent Application, find a Patent Attorney, or search available technology through our Patent Exchange. Patents are available using simple keyword or date criteria. If you are looking to hire a patent attorney, you've come to the right place. Protect your idea and hire a patent lawyer.

Searching: micron





Search by keyword, patent number, inventor, assignee, city or state:




Patent # Description
US-7,131,195 Method for forming metal contacts on a substrate
Solder bump pads are formed on a semiconductor substrate by way of a semiconductor template that has been micromachined to receive solder paste material. The...
US-7,130,979 Dynamic volume management
A method for managing a range of memory in a flash memory space in which a plurality of data objects are stored. A volume defined for the range of memory has a...
US-7,130,239 Memory system, method and predecoding circuit operable in different modes for selectively accessing multiple...
A memory system including a non-volatile flash memory and a method for simultaneously selecting a plurality of memory blocks are disclosed. The memory system is...
US-7,130,228 Active termination control through module register
A method and apparatus are provided for active termination control in a memory by a module register providing an active termination control signal to the memory....
US-7,130,227 Adjustable timing circuit of an integrated circuit
An adjustable timing circuit includes non-volatile programmable fuses and adjustable delay elements. A propagation time of the delay element is selected with the...
US-7,130,226 Clock generating circuit with multiple modes of operation
A clock generating circuit includes a phase comparison circuit that generates a delay control signal corresponding to the relative phases of an output clock...
US-7,130,220 Write once read only memory employing floating gates
Structures and methods for write once read only memory employing floating gates are provided. The write once read only memory cell includes a floating gate...
US-7,130,216 One-device non-volatile random access memory cell
One aspect of the present subject matter relates to a one-device non-volatile memory cell. The memory cell includes a body region, a first diffusion region and a...
US-7,130,022 Methods and systems for controlling radiation beam characteristics for microlithographic processing
Methods and apparatuses for controlling characteristics of radiation directed to a microlithographic workpiece are disclosed. An apparatus in accordance with one...
US-7,129,930 Cordless computer keyboard with illuminated keys
A remote keyboard has keys which are illuminated for identification under a dim motherboard. For a first embodiment of the invention, the identifying symbol or...
US-7,129,794 Phase detector for reducing noise
The present invention provides a method and an apparatus for reducing noise. The apparatus includes a phase detector adapted to determine a phase difference...
US-7,129,761 Digital delay-locked loop circuits with hierarchical delay adjustment
Fine tuned signal phase adjustments are provided by multiple cascaded phase mixers. Each phase mixer outputs a signal having a phase between the phases of its...
US-7,129,738 Method and apparatus for calibrating driver impedance
The present invention provides a method and apparatus is provided for calibrating a driver impedance in an integrated circuit device. The method includes...
US-7,129,725 Semiconductor test interconnect with variable flexure contacts having polymer material
An interconnect for testing semiconductor components includes a substrate, and interconnect contacts on the substrate for electrically engaging terminal contacts...
US-7,129,724 Plasma probe
A plasma probe includes a substrate having substantially the same properties as those of a substrate to be processed, a bottom electrode layer located over the...
US-7,129,631 Black matrix for flat panel field emission displays
A flat panel field emission device includes a black matrix formed from an electrically insulative material such as praseodymium-manganese oxide. The insulative...
US-7,129,584 Elimination of RDL using tape base flip chip on flex for die stacking
A flexible film interposer for stacking a flip chip semiconductor die onto a second (bottom) semiconductor die, semiconductor devices and stacked die assemblies...
US-7,129,573 System having semiconductor component with encapsulated, bonded, interconnect contacts
A semiconductor component includes a die having a pattern of die contacts, and interconnect contacts bonded to the die contacts and encapsulated in an insulating...
US-7,129,567 Substrate, semiconductor die, multichip module, and system including a via structure comprising a plurality of...
Methods of forming at least one multiconductor via are disclosed. Specifically, a substrate may be provided and at least one through-hole may be formed...
US-7,129,553 Lanthanide oxide/hafnium oxide dielectrics
Dielectric layers containing a chemical vapor deposited hafnium oxide and an electron beam evaporated lanthanide oxide and a method of fabricating such a...
US-7,129,535 Capacitor constructions
The invention includes methods in which metal oxide dielectric materials are deposited over barrier layers. The barrier layers can comprise compositions of metal...
US-7,129,534 Magneto-resistive memory and method of manufacturing the same
A method of forming a magneto-resistive memory element includes forming a groove in a layer of insulating material. A liner is formed conformably within the...
US-7,129,457 Redundant imaging systems
Imaging arrays typically include thousands or millions of photodetectors that convert sensed light into corresponding electric signals, which are ultimately...
US-7,129,188 Transistor fabrication methods
A transistor gate is formed which comprises semiconductive material and conductive metal. Source/drain regions are formed proximate the transistor gate. In one...
US-7,129,180 Masking structure having multiple layers including an amorphous carbon layer
A masking structure having multiple layers is formed. The masking structure includes an amorphous carbon layer and a cap layer formed over the amorphous carbon...
US-7,129,160 Method for simultaneously removing multiple conductive materials from microelectronic substrates
A method and apparatus for simultaneously removing conductive materials from a microelectronic substrate. A method in accordance with one embodiment of the...
US-7,129,156 Method for fabricating a silicon carbide interconnect for semiconductor components using heating
An interconnect for semiconductor components includes a substrate, and interconnect contacts on the substrate for electrically engaging component contacts on the...
US-7,129,128 Method of improved high K dielectric-polysilicon interface for CMOS devices
Methods for forming dielectric layers over polysilicon substrates, useful in the construction of capacitors and other semiconductor circuit components are...
US-7,129,114 Methods relating to singulating semiconductor wafers and wafer scale assemblies
Methods relating to the singulation of dice from semiconductor wafers. Trenches or channels are formed in the bottom surface of a semiconductor wafer,...
US-7,128,842 Polyimide as a mask in vapor hydrogen fluoride etching
A layer of polyimide or polysilicon is used as a mask in vapor hydrogen fluoride etching. Both non-photosensitive and photosensitive type polyimide may be used....
US-7,128,787 Atomic layer deposition method
An atomic layer deposition method includes positioning a semiconductor substrate within an atomic layer deposition chamber. A first precursor gas is flowed to...
US-7,128,551 Surface smoothing of stereolithographically formed 3-D objects
A stereolithographic method and apparatus for forming polymeric structures comprising a plurality of overlying layers, each layer formed by polymerizing a thin...
US-7,127,622 Memory subsystem voltage control and method
A method and apparatus for providing a preferred operating voltage to a memory device as specified by a stored configuration parameter. The apparatus includes a...
US-7,127,559 Caching of dynamic arrays
Systems and methods are provided for caching dynamic arrays. According to one aspect, a cache memory device is provided for caching dynamic arrays or dynamic...
US-7,127,365 Method for identifying a defective die site
The present invention relates to the marking and identification of defective die sites on a mounting substrate. A mounting substrate is provided which is...
US-7,127,319 Reducing asymmetrically deposited film induced registration error
Methods, systems, products and apparatuses are disclosed herein relating to registration and asymmetrically deposited films, and more specifically, to reducing...
US-7,126,874 Memory system and method for strobing data, command and address signals
A memory system couples command, address or write data signals from a memory controller to a memory device and read data signals from the memory device to the...
US-7,126,871 Circuits and methods to protect a gate dielectric antifuse
According to embodiments of the present invention, an antifuse circuit is operated by coupling an elevated voltage to a first terminal of an antifuse,...
US-7,126,863 Active termination control
A method and apparatus are provided for active termination control in a memory. The memory turns on active termination based on information programmed into one...
US-7,126,394 History-based slew rate control to reduce intersymbol interference
In one aspect of the invention, a method of reducing intersymbol interference on a signal line is disclosed. A state machine records previous bits that were...
US-7,126,393 Delay circuit with reset-based forward path static delay
A delay locked loop circuit and method of operating the same. The delay locked loop circuit comprises a forward delay path having a variable delay portion and a...
US-7,126,380 Distributed clock generator for semiconductor devices and related methods of operating semiconductor devices
A distributed clock generator for a semiconductor device. In one embodiment, the clock generator is not localized in one particular location on the semiconductor...
US-7,126,317 Apparatus and methods for regulated voltage
An electronic system according to various aspects of the present invention includes a memory and a supply regulation circuit having a regulated output to provide...
US-7,126,228 Apparatus for processing semiconductor devices in a singulated form
Improved methods and apparatus are provided for the handling and testing of semiconductor devices. One embodiment comprises a die carrier for one or more...
US-7,126,224 Semiconductor substrate-based interconnection assembly for semiconductor device bearing external connection...
The present invention relates to a method of forming interconnections for a temporary package, wherein the interconnections are capable of receiving solder balls...
US-7,126,205 Devices having improved capacitance and methods of their fabrication
A capacitor formed by a process using only two deposition steps and a dielectric formed by oxidizing a metal layer in an electrolytic solution. The capacitor has...
US-7,126,200 Integrated circuits with contemporaneously formed array electrodes and logic interconnects
The invention relates to interconnects for an integrated circuit memory device. Embodiments of the invention include processes to fabricate interconnects for...
US-7,126,195 Method for forming a metallization layer
A method for forming a metallization layer (30). A first layer (14) is formed outwardly from a semiconductor substrate (10). Contact vias (16) are formed through...
US-7,126,183 Programmable array logic or memory with p-channel devices and asymmetrical tunnel barriers
Structures and methods for programmable array type logic and/or memory with p-channel devices and asymmetrical low tunnel barrier intergate insulators are...
US-7,126,182 Memory circuitry
The invention includes memory circuitry. In one implementation, memory circuitry includes a memory array comprising a plurality of memory cell capacitors....
← Previous | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 | Next →

File A Patent Application

  • Protect your idea -- Don't let someone else file first. Learn more.

  • 3 Easy Steps -- Complete Form, application Review, and File. See our process.

  • Attorney Review -- Have your application reviewed by a Patent Attorney. See what's included.