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Patent # Description
US-7,125,748 Methods of encapsulating selected locations of a semiconductor die assembly using a thick solder mask
A solder mask includes an opening through which intermediate conductive elements may be positioned to connect bond pads of a semiconductor die exposed through an...
US-7,124,384 Capacitor layout technique for reduction of fixed pattern noise in a CMOS sensor
A new capacitor architecture includes a front plate of the capacitor formed form a first polysilicon layer. The front plate is surround by a first dielectric...
US-7,124,260 Modified persistent auto precharge command protocol system and method for memory devices
A method of operating a memory device includes placing the memory device in a persistent auto precharge mode of operation, applying a disable command to the...
US-7,124,256 Memory device for burst or pipelined operation with mode selection circuitry
An integrated circuit memory device is designed for high speed data access and for compatibility with existing memory systems. An address strobe signal is used...
US-7,124,223 Routability for memory devices
A computer system provides improved routability for memory modules. Chips are placed on the back side of the module directly behind the chips on the front side,...
US-7,124,050 Method in an integrated circuit (IC) manufacturing process for identifying and redirecting IC's mis-processed...
A method of manufacturing IC devices from semiconductor wafers includes providing the wafers and fabricating ICs on the wafers. At probe, a unique fuse ID is...
US-7,123,541 Memory with address management
The present invention allows for the reduction in power consumption of memory devices. A memory device in one embodiment prohibits address signal propagation on...
US-7,123,530 AC sensing for a resistive memory
Alternating current is used to sense a logic state of a memory cell that has a resistive memory element. The memory element can be in an array and a memory...
US-7,123,525 Phase detector for all-digital phase locked and delay locked loops
A phase detector is comprised of two cross-coupled gates which are capable of phase discrimination down to a level of approximately 10 picoseconds. An arbiter...
US-7,123,522 Method and apparatus for achieving low power consumption during power down
The present technique relates to a method and apparatus to provide a deep power down mode. In a memory device, such as DRAM or SRAM, various internal voltage...
US-7,123,521 Random cache read
A non-volatile memory is described that utilizes a cache read mode of operation, where a next page of memory is being read/sensed from the memory array by the...
US-7,123,516 Erase verify for nonvolatile memory using bitline/reference current-to-voltage converters
A memory device verify system determines a state of memory cells in a memory. The memory includes a memory array having a plurality of memory cells coupled to...
US-7,123,513 Erase verify for non-volatile memory using a reference current-to-voltage converter
A memory device verify system determines a state of memory cells in a memory. The memory includes a memory array having a plurality of memory cells coupled to...
US-7,123,512 Contiguous block addressing scheme
An improved non-volatile erase block memory device apparatus and method is described that incorporates an improved addressing scheme to provide for extended...
US-7,123,503 Writing to ferroelectric memory devices
A programming voltage is applied to a first word line coupled to a control gate of a selected ferroelectric memory cell in an array of ferroelectric memory...
US-7,123,148 Wireless communication devices, radio frequency identification devices, radio frequency identification device...
The present invention provides radio frequency identification devices, remote communication devices, identification systems, communication methods, and...
US-7,123,046 Apparatus for adaptively adjusting a data receiver
Offsets and timing skews in data signals captured in a data receiver are reduced by adaptively adjusting a transition threshold of the data receiver. A data...
US-7,123,042 Methods, apparatus and systems for wafer-level burn-in stressing of semiconductor devices
A large-scale support carries semiconductor devices and at least one pair of common conductive regions in communication therewith. Each common conductive region...
US-7,123,036 Test method for electronic modules
A pass through test system for testing an electronic module includes an interface board, and test contactors movably mounted to the interface board for...
US-7,122,908 Electronic device package
An electronic device package comprises a substrate, a die, and a material having a Young's modulus of between about 0.1 megapascals and about 20 megapascals (at...
US-7,122,907 Interposer substrate and wafer scale interposer substrate member for use with flip-chip configured...
A method and apparatus for increasing the integrated circuit density in a flip chip semiconductor device assembly and decreasing the time for dielectrically...
US-7,122,906 Die-wafer package and method of fabricating same
A die-wafer package includes a singulated semiconductor die having a first plurality of bond pads on a first surface and a second plurality of bond pads on a...
US-7,122,905 Microelectronic devices and methods for mounting microelectronic packages to circuit boards
Packaged microelectronic devices, methods of manufacturing packaged microelectronic devices, and method of mounting packaged microelectronic devices to printed...
US-7,122,829 Probe look ahead: testing parts not currently under a probehead
A semiconductor substrate, probe card, and methods for stressing and testing dies on a semiconductor substrate are provided. The semiconductor substrate,...
US-7,122,819 Method and apparatus for imager die package quality testing
An apparatus and method of detecting a defect in an imager die package. The method comprises the steps of exposing the imager die package to light at a first...
US-7,122,480 Method of plasma etching a substrate
A method for controlling striations and CD loss in a plasma etching method is disclosed. During the etching process, the substrate of semiconductor material to...
US-7,122,475 Methods for using bi-modal abrasive slurries for mechanical and chemical-mechanical planarization of...
A method and apparatus for making and using slurries for planarizing microelectronic-device substrate assemblies in mechanical and/or chemical-mechanical...
US-7,122,464 Systems and methods of forming refractory metal nitride layers using disilazanes
A method of forming (and apparatus for forming) refractory metal nitride layers (including silicon nitride layers), such as a tantalum (silicon) nitride barrier...
US-7,122,453 Methods of patterning radiation, methods of forming radiation-patterning tools, and radiation-patterning tools
The invention includes a method of patterning radiation. The radiation is simultaneously passed through a structure and through a subresolution assist feature...
US-7,122,425 Methods of forming semiconductor constructions
The invention includes semiconductor constructions containing vertically-extending pillars, and methods for forming such constructions. The vertically-extending...
US-7,122,422 Methods of forming capacitors
This invention includes methods of forming capacitors. In one implementation, a first capacitor electrode material is formed over a substrate. The first...
US-7,122,420 Methods of recessing conductive material and methods of forming capacitor constructions
The invention includes a method of forming spaced conductive regions. A construction is formed which includes a first electrically conductive material over a...
US-7,122,411 SOI device with reduced drain induced barrier lowering
A CMOS device formed with a Silicon On Insulator (SOI) technology with reduced Drain Induced Barrier Lowering (DIBL) characteristics and a method for producing...
US-7,122,408 Photodiode with ultra-shallow junction for high quantum efficiency CMOS image sensor and method of formation
A pinned photodiode with an ultra-shallow highly-doped surface layer of a first conductivity type and a method of formation are disclosed. The ultra-shallow...
US-7,122,404 Techniques for packaging a multiple device component
A technique for packaging multiple devices to form a multi-chip module. Specifically, a multi-chip package is coupled to an interposer to form the multi-chip...
US-7,122,390 Methods of fabrication for flip-chip image sensor packages
The present invention provides flip-chip packaging for optically interactive devices such as image sensors and methods of assembly. In a first embodiment of the...
US-7,122,389 Method for processing semiconductor devices in a singulated form
Improved methods and apparatus are provided for the handling and testing of semiconductor devices. One embodiment comprises a die carrier for one or more...
US-7,121,926 Methods for planarization of group VIII metal-containing surfaces using a fixed abrasive article
A planarization method includes providing a Group VIII metal-containing surface (preferably, a platinum-containing surface) and positioning it for contact with a...
US-7,121,921 Methods for planarizing microelectronic workpieces
Planarizing machines and methods for accurately planarizing microelectronic workpieces. Several embodiments of the planarizing machines produce a planar surface...
US-7,121,919 Chemical mechanical polishing system and process
Chemical mechanical polishing (CMP) systems and methods are provided herein. One aspect of the present subject matter is a polishing system. One polishing system...
US-7,121,860 Pinch-style support contact, method of enabling electrical communication with and supporting an IC package, and...
A socket for removably mounting an electronic device and which has utility for testing of the electronic device. The socket includes pinch-style support contacts...
US-7,121,842 Electrical connector
An electrical connecting apparatus comprises: a plurality of plate-like probes, each of which electrically connects an electrode of a device under test and a...
US-7,120,999 Methods of forming a contact array in situ on a substrate
A substrate assembly is disclosed including a substrate and a plurality of spring-biased electrical contacts formed thereon for establishing electrical contact...
US-7,120,889 Integrated circuit schematics and layouts
Integrated circuit schematics and layouts are provided. A schematic for an integrated circuit includes a number of circuit components interconnected by lines and...
US-7,120,754 Synchronous DRAM with selectable internal prefetch size
A synchronous memory device and its method of operation which can be set to operate at a plurality of supported prefetch modes. The prefetch mode may be set by...
US-7,120,744 System and method for managing a cache memory
A processing system optimized for data string manipulations includes data string execution circuitry associated with a bus interface unit or memory controller....
US-7,120,743 Arbitration system and method for memory responses in a hub-based memory system
A memory hub includes a local queue that stores local memory responses, a bypass path that passes downstream memory responses, and a buffered queue coupled to...
US-7,120,727 Reconfigurable memory module and method
A computer system includes a controller coupled to a plurality of memory modules each of which includes a memory hub and a plurality of memory devices divided...
US-7,120,723 System and method for memory hub-based expansion bus
A system memory includes a memory hub controller, a memory module accessible by the memory hub controller, and an expansion module having a processor circuit...
US-7,120,513 Method for using data regarding manufacturing procedures integrated circuits (ICS) have undergone, such as...
An inventive method in an integrated circuit (IC) manufacturing process for using data regarding repair procedures conducted on IC's at probe to determine...
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