Easy To Use Patents Search & Patent Lawyer Directory

At Patents you can conduct a Patent Search, File a Patent Application, find a Patent Attorney, or search available technology through our Patent Exchange. Patents are available using simple keyword or date criteria. If you are looking to hire a patent attorney, you've come to the right place. Protect your idea and hire a patent lawyer.

Searching: micron





Search by keyword, patent number, inventor, assignee, city or state:




Patent # Description
US-7,123,042 Methods, apparatus and systems for wafer-level burn-in stressing of semiconductor devices
A large-scale support carries semiconductor devices and at least one pair of common conductive regions in communication therewith. Each common conductive region...
US-7,123,036 Test method for electronic modules
A pass through test system for testing an electronic module includes an interface board, and test contactors movably mounted to the interface board for...
US-7,122,908 Electronic device package
An electronic device package comprises a substrate, a die, and a material having a Young's modulus of between about 0.1 megapascals and about 20 megapascals (at...
US-7,122,907 Interposer substrate and wafer scale interposer substrate member for use with flip-chip configured...
A method and apparatus for increasing the integrated circuit density in a flip chip semiconductor device assembly and decreasing the time for dielectrically...
US-7,122,906 Die-wafer package and method of fabricating same
A die-wafer package includes a singulated semiconductor die having a first plurality of bond pads on a first surface and a second plurality of bond pads on a...
US-7,122,905 Microelectronic devices and methods for mounting microelectronic packages to circuit boards
Packaged microelectronic devices, methods of manufacturing packaged microelectronic devices, and method of mounting packaged microelectronic devices to printed...
US-7,122,829 Probe look ahead: testing parts not currently under a probehead
A semiconductor substrate, probe card, and methods for stressing and testing dies on a semiconductor substrate are provided. The semiconductor substrate,...
US-7,122,819 Method and apparatus for imager die package quality testing
An apparatus and method of detecting a defect in an imager die package. The method comprises the steps of exposing the imager die package to light at a first...
US-7,122,480 Method of plasma etching a substrate
A method for controlling striations and CD loss in a plasma etching method is disclosed. During the etching process, the substrate of semiconductor material to...
US-7,122,475 Methods for using bi-modal abrasive slurries for mechanical and chemical-mechanical planarization of...
A method and apparatus for making and using slurries for planarizing microelectronic-device substrate assemblies in mechanical and/or chemical-mechanical...
US-7,122,464 Systems and methods of forming refractory metal nitride layers using disilazanes
A method of forming (and apparatus for forming) refractory metal nitride layers (including silicon nitride layers), such as a tantalum (silicon) nitride barrier...
US-7,122,453 Methods of patterning radiation, methods of forming radiation-patterning tools, and radiation-patterning tools
The invention includes a method of patterning radiation. The radiation is simultaneously passed through a structure and through a subresolution assist feature...
US-7,122,425 Methods of forming semiconductor constructions
The invention includes semiconductor constructions containing vertically-extending pillars, and methods for forming such constructions. The vertically-extending...
US-7,122,422 Methods of forming capacitors
This invention includes methods of forming capacitors. In one implementation, a first capacitor electrode material is formed over a substrate. The first...
US-7,122,420 Methods of recessing conductive material and methods of forming capacitor constructions
The invention includes a method of forming spaced conductive regions. A construction is formed which includes a first electrically conductive material over a...
US-7,122,411 SOI device with reduced drain induced barrier lowering
A CMOS device formed with a Silicon On Insulator (SOI) technology with reduced Drain Induced Barrier Lowering (DIBL) characteristics and a method for producing...
US-7,122,408 Photodiode with ultra-shallow junction for high quantum efficiency CMOS image sensor and method of formation
A pinned photodiode with an ultra-shallow highly-doped surface layer of a first conductivity type and a method of formation are disclosed. The ultra-shallow...
US-7,122,404 Techniques for packaging a multiple device component
A technique for packaging multiple devices to form a multi-chip module. Specifically, a multi-chip package is coupled to an interposer to form the multi-chip...
US-7,122,390 Methods of fabrication for flip-chip image sensor packages
The present invention provides flip-chip packaging for optically interactive devices such as image sensors and methods of assembly. In a first embodiment of the...
US-7,122,389 Method for processing semiconductor devices in a singulated form
Improved methods and apparatus are provided for the handling and testing of semiconductor devices. One embodiment comprises a die carrier for one or more...
US-7,121,926 Methods for planarization of group VIII metal-containing surfaces using a fixed abrasive article
A planarization method includes providing a Group VIII metal-containing surface (preferably, a platinum-containing surface) and positioning it for contact with a...
US-7,121,921 Methods for planarizing microelectronic workpieces
Planarizing machines and methods for accurately planarizing microelectronic workpieces. Several embodiments of the planarizing machines produce a planar surface...
US-7,121,919 Chemical mechanical polishing system and process
Chemical mechanical polishing (CMP) systems and methods are provided herein. One aspect of the present subject matter is a polishing system. One polishing system...
US-7,121,860 Pinch-style support contact, method of enabling electrical communication with and supporting an IC package, and...
A socket for removably mounting an electronic device and which has utility for testing of the electronic device. The socket includes pinch-style support contacts...
US-7,121,842 Electrical connector
An electrical connecting apparatus comprises: a plurality of plate-like probes, each of which electrically connects an electrode of a device under test and a...
US-7,120,999 Methods of forming a contact array in situ on a substrate
A substrate assembly is disclosed including a substrate and a plurality of spring-biased electrical contacts formed thereon for establishing electrical contact...
US-7,120,889 Integrated circuit schematics and layouts
Integrated circuit schematics and layouts are provided. A schematic for an integrated circuit includes a number of circuit components interconnected by lines and...
US-7,120,754 Synchronous DRAM with selectable internal prefetch size
A synchronous memory device and its method of operation which can be set to operate at a plurality of supported prefetch modes. The prefetch mode may be set by...
US-7,120,744 System and method for managing a cache memory
A processing system optimized for data string manipulations includes data string execution circuitry associated with a bus interface unit or memory controller....
US-7,120,743 Arbitration system and method for memory responses in a hub-based memory system
A memory hub includes a local queue that stores local memory responses, a bypass path that passes downstream memory responses, and a buffered queue coupled to...
US-7,120,727 Reconfigurable memory module and method
A computer system includes a controller coupled to a plurality of memory modules each of which includes a memory hub and a plurality of memory devices divided...
US-7,120,723 System and method for memory hub-based expansion bus
A system memory includes a memory hub controller, a memory module accessible by the memory hub controller, and an expansion module having a processor circuit...
US-7,120,513 Method for using data regarding manufacturing procedures integrated circuits (ICS) have undergone, such as...
An inventive method in an integrated circuit (IC) manufacturing process for using data regarding repair procedures conducted on IC's at probe to determine...
US-7,120,336 Resonator for thermo optic device
A resonator for thermo optic devices is formed in the same process steps as a waveguide and is formed in a depression of a lower cladding while the waveguide is...
US-7,120,287 Non-lot based method for assembling integrated circuit devices
An inventive method tracks IC devices through the assembly steps in a manufacturing process. Prior to die attach, a laser scribe marks the lead frame of each of...
US-7,120,073 Integrated circuit devices having reducing variable retention characteristics
The illustrated embodiments relate to a process for improving retention time of a set of integrated circuit devices. The process comprises placing the set of...
US-7,120,068 Column/row redundancy architecture using latches programmed from a look up table
A scheme for defective memory column or row substitution is disclosed which uses a programmable look-up table to store new addresses for column selection when...
US-7,120,065 Techniques for implementing accurate operating current values stored in a database
Memory modules and methods for fabricating and implementing memory modules wherein unique operating current values corresponding to specific memory devices on...
US-7,120,060 Memory device with non-volatile reference memory cell trimming capabilities
A non-volatile memory device comprising a primary memory array, at least one non-volatile reference memory cell and sense circuitry. The primary memory array has...
US-7,120,055 Flash memory device with improved programming performance
A selected wordline that is coupled to a cell to be programmed is biased during a program operation. The unselected wordlines are biased with a negative...
US-7,120,054 Preconditioning global bitlines
A method and apparatus for discharging global bitlines in a flash memory to a voltage sufficiently low to avoid drain disturb for non-selected cells in a...
US-7,120,046 Memory array with surrounding gate access transistors and capacitors with global and staggered local bit lines
A memory array with staggered local data/bit lines extending generally in a first direction formed in an upper surface of a substrate and memory cell access...
US-7,119,839 High resolution CMOS circuit using a matched impedance output transmission line
Image sensor with CMOS output, an another circuit receiving input. The circuit operates like a transmission line, in current mode, with substantially zero...
US-7,119,812 Full-scene anti-aliasing method and system
A method and system for performing full-scene anti-aliasing for an image through a technique of rotating and unrotating rasterization of a scene and rendering a...
US-7,119,592 Delay locked loop circuit with time delay quantifier and control
A delay locked loop circuit has a quantifier for obtaining a measured delay quantity based on a time delay between an external signal and an internal signal....
US-7,119,583 Phase detector and method having hysteresis characteristics
A phase detector generates a first output signal if a feedback clock signal leads a reference clock signal by more than a first time. The phase detector...
US-7,119,568 Methods for wafer level burn-in
A method, circuit and system for determining burn-in reliability from wafer level burn-in are disclosed. The method includes recording the number of failures in...
US-7,119,563 Integrated circuit characterization printed circuit board
An integrated circuit characterization printed circuit board and method are provided for improving the uniformity of impedance introduced by a test fixture...
US-7,119,561 Electrical connecting apparatus
The electrical connecting apparatus according to the present invention includes first, second and third plate members having plate-like portions at intervals...
US-7,119,397 Double blanket ion implant method and structure
A double blanket ion implant method for forming diffusion regions in memory array devices, such as a MOSFET access device is disclosed. The method provides a...
← Previous | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 | Next →

File A Patent Application

  • Protect your idea -- Don't let someone else file first. Learn more.

  • 3 Easy Steps -- Complete Form, application Review, and File. See our process.

  • Attorney Review -- Have your application reviewed by a Patent Attorney. See what's included.