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Patent # Description
US-7,120,336 Resonator for thermo optic device
A resonator for thermo optic devices is formed in the same process steps as a waveguide and is formed in a depression of a lower cladding while the waveguide is...
US-7,120,287 Non-lot based method for assembling integrated circuit devices
An inventive method tracks IC devices through the assembly steps in a manufacturing process. Prior to die attach, a laser scribe marks the lead frame of each of...
US-7,120,073 Integrated circuit devices having reducing variable retention characteristics
The illustrated embodiments relate to a process for improving retention time of a set of integrated circuit devices. The process comprises placing the set of...
US-7,120,068 Column/row redundancy architecture using latches programmed from a look up table
A scheme for defective memory column or row substitution is disclosed which uses a programmable look-up table to store new addresses for column selection when...
US-7,120,065 Techniques for implementing accurate operating current values stored in a database
Memory modules and methods for fabricating and implementing memory modules wherein unique operating current values corresponding to specific memory devices on...
US-7,120,060 Memory device with non-volatile reference memory cell trimming capabilities
A non-volatile memory device comprising a primary memory array, at least one non-volatile reference memory cell and sense circuitry. The primary memory array has...
US-7,120,055 Flash memory device with improved programming performance
A selected wordline that is coupled to a cell to be programmed is biased during a program operation. The unselected wordlines are biased with a negative...
US-7,120,054 Preconditioning global bitlines
A method and apparatus for discharging global bitlines in a flash memory to a voltage sufficiently low to avoid drain disturb for non-selected cells in a...
US-7,120,046 Memory array with surrounding gate access transistors and capacitors with global and staggered local bit lines
A memory array with staggered local data/bit lines extending generally in a first direction formed in an upper surface of a substrate and memory cell access...
US-7,119,839 High resolution CMOS circuit using a matched impedance output transmission line
Image sensor with CMOS output, an another circuit receiving input. The circuit operates like a transmission line, in current mode, with substantially zero...
US-7,119,812 Full-scene anti-aliasing method and system
A method and system for performing full-scene anti-aliasing for an image through a technique of rotating and unrotating rasterization of a scene and rendering a...
US-7,119,592 Delay locked loop circuit with time delay quantifier and control
A delay locked loop circuit has a quantifier for obtaining a measured delay quantity based on a time delay between an external signal and an internal signal....
US-7,119,583 Phase detector and method having hysteresis characteristics
A phase detector generates a first output signal if a feedback clock signal leads a reference clock signal by more than a first time. The phase detector...
US-7,119,568 Methods for wafer level burn-in
A method, circuit and system for determining burn-in reliability from wafer level burn-in are disclosed. The method includes recording the number of failures in...
US-7,119,563 Integrated circuit characterization printed circuit board
An integrated circuit characterization printed circuit board and method are provided for improving the uniformity of impedance introduced by a test fixture...
US-7,119,561 Electrical connecting apparatus
The electrical connecting apparatus according to the present invention includes first, second and third plate members having plate-like portions at intervals...
US-7,119,397 Double blanket ion implant method and structure
A double blanket ion implant method for forming diffusion regions in memory array devices, such as a MOSFET access device is disclosed. The method provides a...
US-7,119,388 MRAM device fabricated using chemical mechanical polishing
The present invention provides a method of forming an MRAM cell which minimizes the occurrence of electrical shorts during fabrication. A first conductor is...
US-7,119,322 CMOS image sensor having pinned diode floating diffusion region
The present invention provides an image sensor having a pinned floating diffusion region in addition to a pinned photodiode. The pinned floating diffusion region...
US-7,119,321 Optical channels for multi-level metal optical imagers
The manufacture of multi-level optical imagers and the resulting imagers are described. Multiple levels of metallization are prepared, each level having a via....
US-7,119,317 Wide dynamic range imager with selective readout
A wide dynamic range imager with a dual integration, selective readout operating method that requires only one readout chain. First signals from a row of pixels...
US-7,119,034 Atomic layer deposition method of forming an oxide comprising layer on a substrate
This invention includes atomic layer deposition methods of depositing oxide comprising layers on substrates. In one implementation, a substrate is positioned...
US-7,119,033 Ion-assisted oxidation methods and the resulting structures
Oxidation methods and resulting structures including providing an oxide layer on a substrate and then re-oxidizing the oxide layer by vertical ion bombardment of...
US-7,119,031 Methods of forming patterned photoresist layers over semiconductor substrates
This invention includes methods of forming patterned photoresist layers over semiconductor substrates. In one implementation, a porous antireflective coating is...
US-7,119,025 Methods of eliminating pattern collapse on photoresist patterns
A stabilizing solution for treating photoresist patterns and methods of preventing profile abnormalities, toppling and resist footing are disclosed. The...
US-7,119,024 Method and structure for a self-aligned silicided word line and polysilicon plug during the formation of a...
A method used to form a semiconductor device provides a silicide layer on a plurality of transistor word lines and on a plurality of conductive plugs. In one...
US-7,118,966 Methods of forming conductive lines
This invention includes methods of forming conductive lines, and methods of forming conductive contacts adjacent conductive lines. In one implementation, a...
US-7,118,960 Selective polysilicon stud growth
A memory cell having a bit line contact and a method of manufacturing the memory cell is provided The memory cell may be a 6F.sup.2 or smaller memory cell. The...
US-7,118,950 Method of forming a field effect transistor
In one implementation, a method of forming a field effect transistor includes etching an opening into source/drain area of a semiconductor substrate. The opening...
US-7,118,783 Methods and apparatus for vapor processing of micro-device workpieces
CVD, ALD, and other vapor processes used in processing semiconductor workpieces often require volatilizing a liquid or solid precursor. Certain embodiments of...
US-7,118,686 Slurry for use in polishing semiconductor device conductive structures that include copper and tungsten and...
A method for substantially simultaneously polishing a copper conductive structure of a semiconductor device structure and an adjacent barrier layer. The method...
US-7,118,683 Methods of etching silicon-oxide-containing compositions
The invention encompasses a method of enhancing selectivity of etching silicon dioxide relative to one or more organic substances. A material comprising one or...
US-7,118,455 Semiconductor workpiece processing methods
Semiconductor processors, sensors, semiconductor processing systems, semiconductor workpiece processing methods, and turbidity monitoring methods are provided....
US-7,118,447 Semiconductor workpiece processing methods
Semiconductor processor systems, systems configured to provide a semiconductor workpiece process fluid, semiconductor workpiece processing methods, methods of...
US-7,118,445 Semiconductor workpiece processing methods, a method of preparing semiconductor workpiece process fluid, and a...
Semiconductor processor systems, systems configured to provide a semiconductor workpiece process fluid, semiconductor workpiece processing methods, methods of...
US-7,117,402 Background block erase check for flash memories
A flash memory erase check circuit is disclosed. One embodiment includes an on-chip circuit that quickly and reliably checks that the flash memory chip is...
US-7,117,316 Memory hub and access method having internal row caching
A computer system includes a controller coupled to a plurality of memory modules each of which includes a memory hub and a plurality of memory devices. The...
US-7,117,299 DRAM with hidden refresh
A synchronous DRAM is provided having specified time slots (e.g., every multiple of 4 clock pulses of a DRAM input clock) within which read or write commands may...
US-7,116,841 Apparatus, method, and product for downscaling an image
An average filter or filters is used in line with the output of an interpolation filter to downscale an image. The interpolation filter upscales a source image...
US-7,116,602 Method and system for controlling refresh to avoid memory cell data losses
A DRAM includes a register storing subsets of row addresses corresponding to rows containing at least one memory cell that is unable to store a data bit during a...
US-7,116,600 Memory device having terminals for transferring multiple types of data
A memory device includes a number of terminals for transferring input data and output data to and from a memory array. The memory device includes an auxiliary...
US-7,116,596 Method of apparatus for enhanced sensing of low voltage memory
A differential sensing circuit and sensing method are provided for use in a low voltage memory device. The sensing circuit includes a cross-coupled sensing...
US-7,116,590 Memory address repair without enable fuses
A memory chip design methodology is disclosed wherein fuse banks on the memory chip may be implemented without enable fuses. A fuse bank may be enabled by using...
US-7,116,589 Per-bit set-up and hold time adjustment for double-data rate synchronous DRAM
A synchronous double-data-rate semiconductor memory device is adapted to receive write data on both the rising and falling edges of a data strobe signal derived...
US-7,116,588 Low supply voltage temperature compensated reference voltage generator and method
A reference voltage generator uses a conventional forward junction voltage generating device and a conventional thermal generator to generate a thermal voltage....
US-7,116,584 Multiple erase block tagging in a flash memory device
A plurality of memory devices can be erase block tagged in parallel by issuing an erase pulse to memory devices that do not have memory blocks with erase block...
US-7,116,570 Access circuit and method for allowing external test voltage to be applied to isolated wells
An access circuit selectively couples an externally accessible terminal to each of a plurality of isolated DRAM wells in which respective DRAM arrays are...
US-7,116,368 CMOS APS pixel sensor dynamic range increase
An image sensing device, such as a CMOS Active Pixel Sensor device, including an array of pixels. Each pixel has a photoreceptor, a follower transistor connected...
US-7,116,366 CMOS aps pixel sensor dynamic range increase
An image sensing device, such as a CMOS Active Pixel Sensor device, including an array of pixels. Each pixel has a photoreceptor, a follower transistor connected...
US-7,116,143 Synchronous clock generator including duty cycle correction
A clock generator for generating an output clock signal synchronized with an input clock signal and having a corrected duty cycle. The clock generator includes...
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