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Patent # Description
US-7,151,041 Methods of forming semiconductor circuitry
The invention includes a method of forming semiconductor circuitry wherein a first semiconductor structure comprising a first monocrystalline semiconductor...
US-7,151,040 Methods for increasing photo alignment margins
Methods and structures are provided for increasing alignment margins when contacting pitch multiplied interconnect lines with other conductive features in memory...
US-7,151,037 Processes of forming stacked resistor constructions
The invention includes semiconductor constructions having a thin film stacked resistor in electrical connection with a source/drain region of a transistor...
US-7,151,030 Horizontal memory devices with vertical gates
Structures and methods for memory devices are provided which operate with lower control gate voltages than conventional floating gate transistors, and which do...
US-7,151,026 Semiconductor processing methods
Semiconductor processing methods are described which can be used to reduce the chances of an inadvertent contamination during processing. In one implementation,...
US-7,151,024 Long retention time single transistor vertical memory gain cell
A single transistor vertical memory gain cell with long data retention times. The memory cell is formed from a silicon carbide substrate to take advantage of the...
US-7,151,013 Semiconductor package having exposed heat dissipating surface and method of fabrication
A high density semiconductor package with thermally enhanced properties is described. The semiconductor package includes a pair of lead frames, each being...
US-7,150,949 Further method to pattern a substrate
The present invention relates to methods for patterning substrates, such as reticles, masks or wafers, which reduce critical dimension variations, improving CD...
US-7,150,945 Polarized reticle, photolithography system, and method of forming a pattern using a polarized reticle in...
Polarized reticles, photolithography systems utilizing a polarized reticle, and methods of using such a system are disclosed. A polarized reticle is formed...
US-7,150,789 Atomic layer deposition methods
An atomic layer deposition method includes positioning a semiconductor substrate within an atomic layer deposition chamber. A first precursor gas is flowed to...
US-7,150,390 Flip chip dip coating encapsulant
A method for underfilling and encapsulating a flip chip in one step is disclosed. The flip chip is immersed in a polymer bath to apply a coating of the polymer...
US-7,149,986 Automated load determination for partitioned simulation
A method and device for automatically generating load circuits for a netlist. A computer system having a schematic for a circuit is used to create a netlist....
US-7,149,876 Method and apparatus for a shift register based interconnection for a massively parallel processor array
A system and method for using wider data paths within Processing Elements (PEs) of a Massively Parallel Array (MPP) to speed the computational performance of the...
US-7,149,875 Data reordering processor and method for use in an active memory device
An active memory device includes a command engine that receives high level tasks from a host and generates corresponding sets of either DCU commands to a DRAM...
US-7,149,874 Memory hub bypass circuit and method
A computer system and a method used to access data from a plurality of memory devices with a memory hub. The computer system includes a plurality of memory...
US-7,149,857 Out of order DRAM sequencer
Memory access requests are successively received in a memory request queue of a memory controller. Any conflicts or potential delays between temporally proximate...
US-7,149,845 Current mode logic scheme and circuit for matchline sense amplifier design using constant current bias cascode...
A CAM device features matchlines which are coupled in series between a top current source, a bottom current source, and ground. The top current source is...
US-7,149,841 Memory devices with buffered command address bus
Circuits and methods are provided that alleviate overloading of the command address bus and limit decreases in command address bus bandwidth to allow increased...
US-7,149,824 Dynamically setting burst length of memory device by applying signal to at least one external pin during a read...
One or more external control pins and/or addressing pins on a memory device are used to set one or both of a burst length and burst type of the memory device.
US-7,149,158 Apparatus and method for providing uninterrupted continuous play during a change of sides of a dual-sided...
An apparatus and method for providing continuous uninterrupted playback of a dual sided optical disk during side-to-side changing of the optical disk. The point...
US-7,149,145 Delay stage-interweaved analog DLL/PLL
A methodology is disclosed that enables the delay stages of an analog delay locked loop (DLL) or phase locked loop (PLL) to be programmed according to the...
US-7,149,143 Decoder for memory data bus
Memory device is described that utilizes a reduced number of sense amplifiers to sense the data bits of a selected column page. The sense amplifiers are...
US-7,149,141 Memory device and method having low-power, high write latency mode and high-power, low write latency mode...
A logic circuit operates write receivers in a dynamic random access memory device in either a low-power mode, high write latency mode or a high-power mode, low...
US-7,149,124 Boosted substrate/tub programming for flash memories
A boosted substrate tub/substrate floating gate memory cell programming process is described that applies a voltage to the substrate or substrate "tub" of a NAND...
US-7,149,117 Reduction of adjacent floating gate data pattern sensitivity
The method for programming non-volatile memory cells erases the memory cells to be programmed. The memory cells are then programmed to a reduced floating gate...
US-7,149,109 Single transistor vertical memory gain cell
A high density vertical single transistor gain cell is realized for DRAM operation. The gain cell includes a vertical transistor having a source region, a drain...
US-7,149,100 Serial transistor-cell array architecture
A memory array architecture suitable for variable resistance memory that mitigates sneak path and associated problems by limiting the number of memory cells...
US-7,148,971 Apparatus for measuring the physical properties of a surface and a pattern generating apparatus for writing a...
The present invention relates to a pattern generating apparatus for writing a pattern on a surface of an object, comprising: a stage having an object having a...
US-7,148,833 Sharing operational amplifier between two stages of pipelined ADC and/or two channels of signal processing...
A mechanism for discharging parasitic capacitance at an input of an operational amplifier, which is shared between two stages of a pipelined analog-to-digital...
US-7,148,831 Variable quantization ADC for image sensors
An A/D converter suitable for use in a system in which the signal power of noise increases with the signal power of the signal, such as an imaging system,...
US-7,148,742 Power supply voltage detection circuitry and methods for use of the same
Power detection circuitry that provides a substantially constant trip-point is provided. The circuitry is immune to temperature and process variations, thus...
US-7,148,718 Articles of manufacture and wafer processing apparatuses
The present invention includes an electronic device workpiece processing apparatus and method of communicating signals within an electronic device workpiece...
US-7,148,715 Systems and methods for testing microelectronic imagers and microfeature devices
Systems and methods for testing microelectronic imagers and microfeature devices are disclosed herein. In one embodiment, a method includes providing a...
US-7,148,555 Method for enhancing electrode surface area in DRAM cell capacitors
Methods for forming the lower electrode of a capacitor in a semiconductor circuit, and the capacitors formed by such methods are provided. The lower electrode is...
US-7,148,547 Semiconductor contact device
The invention provides an advanced metallization technique for fabricating a memory cell array on a substrate. The array is fabricated by forming discrete and...
US-7,148,544 Semiconductor-on-insulator constructions
The invention includes semiconductor constructions having a thin film stacked resistor in electrical connection with a source/drain region of a transistor...
US-7,148,538 Vertical NAND flash memory array
Memory devices, arrays, and strings are described that facilitate the use of vertical floating gate memory cells in NAND architecture memory strings, arrays, and...
US-7,148,536 Memory circuitry and method of forming memory circuitry
A method of forming memory circuitry having a memory array having a plurality of memory capacitors and having peripheral memory circuitry operatively configured...
US-7,148,534 Angled implant in a fabrication technique to improve conductivity of a base material
Ion implantation may be used to break up a dielectric layer that forms during the fabrication of a memory array. More specifically, during the fabrication of...
US-7,148,528 Pinned photodiode structure and method of formation
An imager having a photodiode with a shallow doping profile with respect to the top surface of a substrate is disclosed. An imager with a graded pinned surface...
US-7,148,525 Using high-k dielectrics in isolation structures method, pixel and imager device
An imager device that has an isolation structure such that pinned photodiode characteristics are maintained without increasing doping levels. The invention...
US-7,148,462 Pixel with differential readout
An imager in which two adjacent pixels share row and reset lines and a row selection circuitry while the output transistors of the two pixels are configured as a...
US-7,148,134 Integrated circuitry and a semiconductor processing method of forming a series of conductive lines
A semiconductor processing method of forming a plurality of conductive lines includes, a) providing a substrate; b) providing a first conductive material layer...
US-7,148,118 Methods of forming metal nitride, and methods of forming capacitor constructions
The invention encompasses methods of forming metal nitride proximate dielectric materials. The metal nitride comprises two portions, with one of the portions...
US-7,148,102 Methods of forming buried bit line DRAM circuitry
A method of forming buried bit line DRAM circuitry includes collectively forming a buried bit line forming trench, bit line vias extending from the bit line...
US-7,148,083 Transfer mold semiconductor packaging processes
In one implementation, a circuit substrate includes a substrate having opposing sides. At least one of the sides is configured for transfer mold packaging and...
US-7,147,974 Methods for converting reticle configurations
The invention includes methods of converting reticles from configurations suitable for utilization with later generation (shorter wavelength) stepper radiations...
US-7,147,973 Method to recover the exposure sensitivity of chemically amplified resins from post coat delay effect
Methods of fabricating a photomask, methods of treating a chemically amplified resist-coated photomask blank, a photomask blank resulting from the methods, and...
US-7,147,543 Carrier assemblies, planarizing apparatuses including carrier assemblies, and methods for planarizing...
Carrier assemblies, planarizing machines with carrier assemblies, and methods for mechanical and/or chemical-mechanical planarization of micro-device workpieces...
US-7,146,814 Micro-machine and a method of powering a micro-machine
A rotatable micro-machine is comprised of a solvent reservoir, a porous evaporation region and a channel connecting the solvent reservoir to the evaporation...
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