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Patent # Description
US-7,119,388 MRAM device fabricated using chemical mechanical polishing
The present invention provides a method of forming an MRAM cell which minimizes the occurrence of electrical shorts during fabrication. A first conductor is...
US-7,119,322 CMOS image sensor having pinned diode floating diffusion region
The present invention provides an image sensor having a pinned floating diffusion region in addition to a pinned photodiode. The pinned floating diffusion region...
US-7,119,321 Optical channels for multi-level metal optical imagers
The manufacture of multi-level optical imagers and the resulting imagers are described. Multiple levels of metallization are prepared, each level having a via....
US-7,119,317 Wide dynamic range imager with selective readout
A wide dynamic range imager with a dual integration, selective readout operating method that requires only one readout chain. First signals from a row of pixels...
US-7,119,034 Atomic layer deposition method of forming an oxide comprising layer on a substrate
This invention includes atomic layer deposition methods of depositing oxide comprising layers on substrates. In one implementation, a substrate is positioned...
US-7,119,033 Ion-assisted oxidation methods and the resulting structures
Oxidation methods and resulting structures including providing an oxide layer on a substrate and then re-oxidizing the oxide layer by vertical ion bombardment of...
US-7,119,031 Methods of forming patterned photoresist layers over semiconductor substrates
This invention includes methods of forming patterned photoresist layers over semiconductor substrates. In one implementation, a porous antireflective coating is...
US-7,119,025 Methods of eliminating pattern collapse on photoresist patterns
A stabilizing solution for treating photoresist patterns and methods of preventing profile abnormalities, toppling and resist footing are disclosed. The...
US-7,119,024 Method and structure for a self-aligned silicided word line and polysilicon plug during the formation of a...
A method used to form a semiconductor device provides a silicide layer on a plurality of transistor word lines and on a plurality of conductive plugs. In one...
US-7,118,966 Methods of forming conductive lines
This invention includes methods of forming conductive lines, and methods of forming conductive contacts adjacent conductive lines. In one implementation, a...
US-7,118,960 Selective polysilicon stud growth
A memory cell having a bit line contact and a method of manufacturing the memory cell is provided The memory cell may be a 6F.sup.2 or smaller memory cell. The...
US-7,118,950 Method of forming a field effect transistor
In one implementation, a method of forming a field effect transistor includes etching an opening into source/drain area of a semiconductor substrate. The opening...
US-7,118,783 Methods and apparatus for vapor processing of micro-device workpieces
CVD, ALD, and other vapor processes used in processing semiconductor workpieces often require volatilizing a liquid or solid precursor. Certain embodiments of...
US-7,118,686 Slurry for use in polishing semiconductor device conductive structures that include copper and tungsten and...
A method for substantially simultaneously polishing a copper conductive structure of a semiconductor device structure and an adjacent barrier layer. The method...
US-7,118,683 Methods of etching silicon-oxide-containing compositions
The invention encompasses a method of enhancing selectivity of etching silicon dioxide relative to one or more organic substances. A material comprising one or...
US-7,118,455 Semiconductor workpiece processing methods
Semiconductor processors, sensors, semiconductor processing systems, semiconductor workpiece processing methods, and turbidity monitoring methods are provided....
US-7,118,447 Semiconductor workpiece processing methods
Semiconductor processor systems, systems configured to provide a semiconductor workpiece process fluid, semiconductor workpiece processing methods, methods of...
US-7,118,445 Semiconductor workpiece processing methods, a method of preparing semiconductor workpiece process fluid, and a...
Semiconductor processor systems, systems configured to provide a semiconductor workpiece process fluid, semiconductor workpiece processing methods, methods of...
US-7,117,402 Background block erase check for flash memories
A flash memory erase check circuit is disclosed. One embodiment includes an on-chip circuit that quickly and reliably checks that the flash memory chip is...
US-7,117,316 Memory hub and access method having internal row caching
A computer system includes a controller coupled to a plurality of memory modules each of which includes a memory hub and a plurality of memory devices. The...
US-7,117,299 DRAM with hidden refresh
A synchronous DRAM is provided having specified time slots (e.g., every multiple of 4 clock pulses of a DRAM input clock) within which read or write commands may...
US-7,116,841 Apparatus, method, and product for downscaling an image
An average filter or filters is used in line with the output of an interpolation filter to downscale an image. The interpolation filter upscales a source image...
US-7,116,602 Method and system for controlling refresh to avoid memory cell data losses
A DRAM includes a register storing subsets of row addresses corresponding to rows containing at least one memory cell that is unable to store a data bit during a...
US-7,116,600 Memory device having terminals for transferring multiple types of data
A memory device includes a number of terminals for transferring input data and output data to and from a memory array. The memory device includes an auxiliary...
US-7,116,596 Method of apparatus for enhanced sensing of low voltage memory
A differential sensing circuit and sensing method are provided for use in a low voltage memory device. The sensing circuit includes a cross-coupled sensing...
US-7,116,590 Memory address repair without enable fuses
A memory chip design methodology is disclosed wherein fuse banks on the memory chip may be implemented without enable fuses. A fuse bank may be enabled by using...
US-7,116,589 Per-bit set-up and hold time adjustment for double-data rate synchronous DRAM
A synchronous double-data-rate semiconductor memory device is adapted to receive write data on both the rising and falling edges of a data strobe signal derived...
US-7,116,588 Low supply voltage temperature compensated reference voltage generator and method
A reference voltage generator uses a conventional forward junction voltage generating device and a conventional thermal generator to generate a thermal voltage....
US-7,116,584 Multiple erase block tagging in a flash memory device
A plurality of memory devices can be erase block tagged in parallel by issuing an erase pulse to memory devices that do not have memory blocks with erase block...
US-7,116,570 Access circuit and method for allowing external test voltage to be applied to isolated wells
An access circuit selectively couples an externally accessible terminal to each of a plurality of isolated DRAM wells in which respective DRAM arrays are...
US-7,116,368 CMOS APS pixel sensor dynamic range increase
An image sensing device, such as a CMOS Active Pixel Sensor device, including an array of pixels. Each pixel has a photoreceptor, a follower transistor connected...
US-7,116,366 CMOS aps pixel sensor dynamic range increase
An image sensing device, such as a CMOS Active Pixel Sensor device, including an array of pixels. Each pixel has a photoreceptor, a follower transistor connected...
US-7,116,143 Synchronous clock generator including duty cycle correction
A clock generator for generating an output clock signal synchronized with an input clock signal and having a corrected duty cycle. The clock generator includes...
US-7,116,133 Apparatus and method for adjusting clock skew
The present invention provides a clock signal input circuit that is able to provide inverse internal clock signals generated by the same input buffer as the...
US-7,116,129 Temperature-compensated output buffer method and circuit
A temperature-compensated output buffer circuit is disclosed, which includes a pull-up circuit including a first pull-up transistor for providing a first pull-up...
US-7,116,124 Apparatus to prevent damage to probe card
Probe cards are configured with protective circuitry suitable for use in electrical testing of semiconductor dice without damage to the probe cards. Protective...
US-7,116,122 Method for ball grid array chip packages having improved testing and stacking characteristics
A stackable ball grid array (BGA) or fine ball grid array (FBGA) semiconductor package particularly suitable for board-on-chip or chip-on-board applications in...
US-7,116,118 Method and apparatus for testing semiconductor circuitry for operability and method of forming apparatus for...
A method of engaging electrically conductive test pads on a semiconductor substrate having integrated circuitry for operability testing thereof includes: a)...
US-7,116,042 Flow-fill structures
A preferred embodiment of the invention is directed to support structures such as spacers used to provide a uniform distance between two layers of a device. In...
US-7,116,001 Bumped die and wire bonded board-on-chip package
An apparatus for making a semiconductor assembly and, specifically, interconnecting a semiconductor die to a carrier substrate. The carrier substrate includes a...
US-7,116,000 Underfilled, encapsulated semiconductor die assemblies and methods of fabrication
An apparatus and method for packaging a semiconductor die and a carrier substrate to substantially prevent trapped moisture therebetween and provide a robust,...
US-7,115,998 Multi-component integrated circuit contacts
An integrated circuit connection is describe that includes a first, securing member and a second, connection member. The first member, in an embodiment, is a...
US-7,115,992 Electrode structure for use in an integrated circuit
An electrode structure includes a first layer of conductive material and a dielectric layer formed on a surface of the first layer. An opening is formed in the...
US-7,115,990 Bumped die and wire bonded board-on-chip package
An apparatus for making a semiconductor assembly and, specifically, interconnecting a semiconductor die to a carrier substrate. The carrier substrate includes a...
US-7,115,986 Flexible ball grid array chip scale packages
A method and apparatus for increasing the integrated circuit density in a semiconductor assembly. The assembly includes a flexible interposer substrate attached...
US-7,115,984 Semiconductor devices including peripherally located bond pads, intermediates thereof, assemblies, and packages...
A semiconductor device package is disclosed which is substantially die-sized with respect to each of the X, Y and Z axes. The package includes outer connectors...
US-7,115,982 Semiconductor component having stiffener, stacked dice and circuit decals
A semiconductor component includes a stiffener, a circuit decal attached to the stiffener, and a semiconductor die attached to the stiffener. The circuit decal...
US-7,115,981 Semiconductor device assemblies including interposers with dams protruding therefrom
A dam for substantially laterally confining a quantity of encapsulant material over a region of a substrate, such as an interposer. The dam is configured to...
US-7,115,976 Method and apparatus for epoxy LOC die attachment
A plurality of lead frames is supplied in a lead frame-by-lead frame sequence. A curable adhesive, preferably a 505 Epoxy, is applied to one surface of each lead...
US-7,115,970 Capacitor for use in an integrated circuit
Capacitors for use in an integrated circuit are provided. One aspect of this disclosure relates to a method of making a capacitor. According to various...
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