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Patent # Description
US-7,114,532 Liner for use in processing chamber
A container for use in a processing chamber to lessen the amount of contaminant particles found within the chamber after processing. The container fits closely...
US-7,114,404 System and method for detecting flow in a mass flow controller
Systems and methods are provided for detecting flow in a mass flow controller (MFC). The position of a gate in the MFC is sensed or otherwise determined to...
US-7,114,248 Method of handling an electrical component
A method of handling an electrical component is disclosed. The method includes initiating a first engagement between the electrical component and a conveyor,...
US-7,114,084 Data controlled programmable power supply
A power supply, and a method of controlling the power supply, in which more or less power capacity of the power supply is activated depending on the state of a...
US-7,114,082 Data security for digital data storage
A computing system includes data encryption in the data path between a data source and data storage devices. The data encryption may utilize a key which is...
US-7,114,034 Caching of dynamic arrays
Systems and methods are provided for caching dynamic arrays. According to one aspect, a cache memory device is provided for caching dynamic arrays or dynamic...
US-7,113,435 Data compression read mode for memory testing
Memory devices having a normal mode of operation and a test mode of operation are useful in quality programs. The test mode of operation includes a data...
US-7,113,429 Nor flash memory cell with high storage density
Structures and methods for NOR flash memory cells, arrays and systems are provided. The NOR flash memory cell includes a vertical floating gate transistor...
US-7,112,986 Method for testing using a universal wafer carrier for wafer level die burn-in
A reusable burn-in/test fixture for testing unsingulated dice on a semiconductor wafer consisting of two halves. The first half of the test fixture is a wafer...
US-7,112,985 Method for testing using a universal wafer carrier for wafer level die burn-in
A reusable burn-in/test fixture for testing unsingulated dice on a semiconductor wafer consisting of two halves. The first half of the test fixture is a wafer...
US-7,112,980 System and method for testing devices utilizing capacitively coupled signaling
An apparatus and method for testing a semiconductor device in an AC test regime. The test apparatus includes a test plate capacitively couple to the signal...
US-7,112,878 Die stacking scheme
An improved die stacking scheme is provided. In accordance with one embodiment of the present invention, a multiple die semiconductor assembly is provided...
US-7,112,876 Interposers and other carriers including a slot with laterally recessed area at an end thereof and...
An interposer includes a substantially planar substrate with a slot therethrough. The slot includes a laterally recessed area in only a portion of a periphery...
US-7,112,841 Graded composition metal oxide tunnel barrier interpoly insulators
Structures and methods for programmable array type logic and/or memory devices with graded composition metal oxide tunnel barrier intergate insulators are...
US-7,112,815 Multi-layer memory arrays
Multi-layer memory arrays and methods are provided. A memory array has two or more layers of memory material, each layer of memory material having an array of...
US-7,112,544 Method of atomic layer deposition on plural semiconductor substrates simultaneously
The invention includes a method for treating a plurality of discrete semiconductor substrates. The discrete semiconductor substrates are placed within a reactor...
US-7,112,543 Methods of forming assemblies comprising silicon-doped aluminum oxide
The invention encompasses a method of forming a silicon-doped aluminum oxide. Aluminum oxide and silicon monoxide are co-evaporated. Subsequently, at least some...
US-7,112,542 Methods of forming materials between conductive electrical components, and insulating materials
Methods of forming insulating materials between conductive elements include forming a material adjacent a conductive electrical component comprising: partially...
US-7,112,533 Plasma etching system and method
A system and a process for plasma etching a semiconductor device. The technique comprises periodically applying a heightened voltage bias during the plasma...
US-7,112,531 Silicon oxide co-deposition/etching process
Methods of providing silicon oxide on a substrate in a single process step by simultaneously introducing both a silicon source gas and an etch gas into a CVD...
US-7,112,520 Semiconductor die packages with recessed interconnecting structures and methods for assembling the same
Apparatus and methods relating to semiconductor assemblies. A semiconductor assembly includes an interposer which may be constructed from a flexible material,...
US-7,112,513 Sub-micron space liner and densification process
A method of depositing dielectric material into sub-micron spaces and resultant structures is provided. After a trench is etched in the surface of a wafer, an...
US-7,112,508 Method for forming conductive material in opening and structure regarding same
Method and structure use support layers to assist in planarization processes to form conductive materials (e.g., a Group VIII metal) in an opening. Further, such...
US-7,112,503 Enhanced surface area capacitor fabrication methods
A capacitor fabrication method may include atomic layer depositing a conductive barrier layer to oxygen diffusion over the first electrode. A method may instead...
US-7,112,494 Write once read only memory employing charge trapping in insulators
Structures and methods for write once read only memory employing charge trapping in insulators are provided. The write once read only memory cell includes a...
US-7,112,491 Methods of forming field effect transistors including floating gate field effect transistors
The invention includes methods of forming field effect transistors. In one implementation, a method of forming a field effect transistor having a gate comprising...
US-7,112,488 Source lines for NAND memory devices
Methods and apparatus are provided. A NAND memory device has a source line connected to two or more columns of serially-connected floating-gate transistors. The...
US-7,112,485 Systems and methods for forming zirconium and/or hafnium-containing layers
A method of forming (and apparatus for forming) a zirconium and/or hafnium-containing layer on a substrate, particularly a semiconductor substrate or substrate...
US-7,112,484 Thin film diode integrated with chalcogenide memory cell
An integrated programmable conductor memory cell and diode device in an integrated circuit comprises a diode and a glass electrolyte element, the glass...
US-7,112,482 Method of forming a field effect transistor
A method of forming a field effect transistor includes forming a channel region within bulk semiconductive material of a semiconductor substrate. Source/drain...
US-7,112,479 Methods of forming gatelines and transistor devices
The invention includes semiconductor constructions, methods of forming gatelines, and methods of forming transistor structures. The invention can include, for...
US-7,112,471 Leadless packaging for image sensor devices and methods of assembly
A leadless image sensor package and methods for its assembly. In a first embodiment, an image sensor chip is mounted within a bottom-side cavity of a package...
US-7,112,454 System and method for reducing shorting in memory cells
An MRAM device includes an array of magnetic memory cells having an upper conductive layer and a lower conductive layer separated by a barrier layer. To reduce...
US-7,112,252 Assembly method for semiconductor die and lead frame
A LOC die assembly is disclosed including a die dielectrically adhered to the underside of a lead frame. The lead frame has stress relief slots formed in the...
US-7,112,245 Apparatuses for forming a planarizing pad for planarization of microlectronic substrates
A planarizing pad for planarizing a microelectronic substrate, and a method and apparatus for forming the planarizing pad. In one embodiment, planarizing pad...
US-7,112,122 Methods and apparatus for removing conductive material from a microelectronic substrate
A method and apparatus for removing conductive material from a microelectronic substrate is disclosed. One method includes disposing an electrolytic liquid...
US-7,112,121 Methods and apparatus for electrical, mechanical and/or chemical removal of conductive material from a...
A method and apparatus for removing conductive material from a microelectronic substrate. In one embodiment, the method can include engaging a microelectronic...
US-7,112,048 BOC BGA package for die with I-shaped bond pad layout
Semiconductor die units for forming BOC BGA packages, methods of encapsulating a semiconductor die unit, a mold for use in the method, and resulting encapsulated...
US-7,111,261 Method of determining library parameters using timing surface planarity
The present invention relates to a characterizing a timing delay curve of a circuit component, said timing delay curve having a first region and a second region....
US-7,111,185 Synchronization device with delay line control circuit to control amount of delay added to input signal and...
A method and apparatus for synchronizing signals. For memory devices, such as SDRAMs, implementing a synchronization device to synchronize one signal, such as an...
US-7,110,854 Numerical control apparatus for machine tool and numerical control method for machine tool
A numerical control apparatus for machine tool, including: an NC program storage portion; an electronic cam data transformation unit which transforms an NC...
US-7,110,598 Automatic color constancy for image sensors
An electronic imaging system operates as closely as possible to the cone spectral response space to obtain a human eye-like long, medium, short (LMS) wavelength...
US-7,110,319 Memory devices having reduced coupling noise between wordlines
Memory devices configured to reduce coupling noise between adjacent wordlines in a memory array. More specifically, wordline drivers are interleaved such that...
US-7,110,299 Transistor with nanocrystalline silicon gate structure
A memory is described which has memory cells that store data using hot electron injection. The data is erased through electron tunneling. The memory cells are...
US-7,110,159 Method and apparatus for patterning a workpiece and methods of manufacturing the same
An apparatus for patterning a work piece including a source, and at least one reflective tilting surface adapted to induce a phase difference using at least one...
US-7,110,060 Assemblies and methods for illuminating a display
A computer display is disclosed. The computer display includes a LCD housing, a light source coupled to the LCD housing, and a LCD coupled to the LCD housing....
US-7,109,807 Phase detector for reducing noise
The present invention provides a method and an apparatus for reducing noise. The apparatus includes a phase detector adapted to determine a phase difference...
US-7,109,588 Method and apparatus for attaching microelectronic substrates and support members
A microelectronic package and method for forming such packages. In one embodiment, the package can be formed by providing a support member having a first...
US-7,109,576 Semiconductor component having encapsulated die stack
A semiconductor component includes a substrate and multiple stacked, encapsulated semiconductor dice on the substrate. A first die is back bonded to the...
US-7,109,572 Quad flat no lead (QFN) grid array package
A quad flat no-lead (QFN) grid array semiconductor package and method for making the same is disclosed. The package includes a semiconductor die and a lead frame...
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