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Patent # Description
US-7,136,958 Multiple processor system and method including multiple memory hub modules
A processor-based electronic system includes several memory modules arranged in first and second ranks. The memory modules in the first rank are directly...
US-7,136,316 Method and apparatus for data compression in memory devices
A test circuit for a memory device having a pair of arrays each of which includes a plurality of memory cells arranged in rows and columns. A pair of...
US-7,136,307 Write state machine architecture for flash memory internal instructions
A system and method for a write state machine for non-volatile memory is disclosed. The write state machine has an associated read only memory for storing...
US-7,136,302 Integrated circuit memory device and method
Structures and methods for DEAPROM memory with low tunnel barrier intergate insulators are provided. The DEAPROM memory includes a first source/drain region and...
US-7,136,157 Method and apparatus for testing image sensors
Methods and apparatuses for testing image sensors are disclosed. Desirable apparatuses of the present invention include image sensor testing devices comprising a...
US-7,135,780 Semiconductor substrate for build-up packages
The present invention provides techniques to fabricate build-up single or multichip modules. In one embodiment, this is accomplished by dispensing die-attach...
US-7,135,763 Technique for attaching die to leads
A semiconductor die assembly comprising a semiconductor die with bond pads, a plurality of leads which extend across the semiconductor die and terminate over...
US-7,135,734 Graded composition metal oxide tunnel barrier interpoly insulators
Structures and methods for programmable array type logic and/or memory devices with graded composition metal oxide tunnel barrier intergate insulators are...
US-7,135,444 Cleaning composition useful in semiconductor integrated circuit fabrication
A composition for use in semiconductor processing wherein the composition comprises water, phosphoric acid, and an organic acid; wherein the organic acid is...
US-7,135,421 Atomic layer-deposited hafnium aluminum oxide
A dielectric film containing HfAlO.sub.3 and a method of fabricating such a dielectric film produce a reliable gate dielectric having an equivalent oxide...
US-7,135,417 Method of forming a semiconductor device
In the formation of semiconductor devices, a processing method is provided, including steps for forming an oxide layer. The embodied methods involve a series of...
US-7,135,401 Methods of forming electrical connections for semiconductor constructions
The invention includes methods for forming electrical connections associated with semiconductor constructions. A semiconductor substrate is provided which has a...
US-7,135,381 Wet etching method of removing silicon from a substrate and method of forming trench isolation
A wet etching method of removing silicon from a substrate includes depositing a layer comprising silicon in elemental form over a substrate. The layer is exposed...
US-7,135,369 Atomic layer deposited ZrAl.sub.xO.sub.y dielectric layers including Zr.sub.4AlO.sub.9
An atomic layer deposited ZrAl.sub.xO.sub.y dielectric layer and a method of fabricating such a dielectric layer produce a reliable dielectric layer having an...
US-7,135,363 Semiconductor processing methods of forming integrated circuitry
Semiconductor processing methods of forming integrated circuitry are described. In one embodiment, memory circuitry and peripheral circuitry are formed over a...
US-7,135,345 Methods for processing semiconductor devices in a singulated form
Improved methods and apparatus are provided for the handling and testing of semiconductor devices. One embodiment comprises a die carrier for one or more...
US-7,134,944 Apparatus and method for conditioning a contact surface of a processing pad used in processing microelectronic...
Conditioning devices, systems and methods for conditioning a contact surface of a processing pad used in processing microelectronic workpieces. One embodiment of...
US-7,134,934 Methods and apparatus for electrically detecting characteristics of a microelectronic substrate and/or...
Methods and apparatuses for detecting characteristics of a microelectronic substrate. A method in accordance with an embodiment of the invention includes...
US-7,134,390 Method and stencil for extruding material on a substrate
A stencil for use in fabricating semiconductor devices is disclosed that has an aperture having a first portion extending from a first side thereof and a second...
US-7,133,999 Method and system for local memory addressing in single instruction, multiple data computer system
A single instruction, multiple data ("SIMD") computer system includes a central control unit coupled to 256 processing elements ("PEs") and to 32 static random...
US-7,133,998 Active memory processing array topography and method
An integrated active memory device includes an array of processing elements coupled to a dynamic random access memory device and to a component supplying...
US-7,133,992 Burst counter controller and method in a memory device operable in a 2-bit prefetch mode
A burst counter generates all but the least significant bit ("LSB") of a sequence of column addresses in a 2-bit prefetch dynamic random access memory ("DRAM")....
US-7,133,991 Method and system for capturing and bypassing memory transactions in a hub-based memory system
A memory hub includes a reception interface that receives data words and captures the data words in response to a first clock signal in a first time domain. The...
US-7,133,972 Memory hub with internal cache and/or memory access prediction
A computer system includes a memory hub for coupling a processor to a plurality of synchronous dynamic random access memory ("SDRAM") devices. The memory hub...
US-7,133,445 System and method for testing a modem
A testing device and methods for operating the device to test a modem in a personal computer are described. A modem tester includes a signal reporting circuit...
US-7,133,323 Memory system, method and predecoding circuit operable in different modes for selectively accessing multiple...
A memory system including a non-volatile flash memory and a method for simultaneously selecting a plurality of memory blocks are disclosed. The memory system is...
US-7,133,321 Sense amplifier circuit
The disclosed embodiments relate to an equalization circuit, which may include a first sense amplifier having an input, the input being electrically isolated...
US-7,133,315 Write once read only memory employing charge trapping in insulators
Structures and methods for write once read only memory employing charge trapping in insulators are provided. The write once read only memory cell includes a...
US-7,133,307 Resistive memory element sensing using averaging
A system for determining the logic state of a resistive memory cell element, for example an MRAM resistive cell element. The system includes a controlled voltage...
US-7,133,076 Contoured surface cover plate for image sensor array
A cover for an image sensor array is disclosed. The cover includes a plate formed of substantially transparent material and placed adjacent to the image sensor...
US-7,132,898 Phase detector for reducing noise
The present invention provides a method and an apparatus for reducing noise. The apparatus includes a phase detector adapted to determine a phase difference...
US-7,132,750 Semiconductor component having conductors with wire bondable metalization layers
A semiconductor component includes a semiconductor die, a low k polymer layer on the die and redistribution conductors on the polymer layer. The component also...
US-7,132,734 Microelectronic component assemblies and microelectronic component lead frame structures
The present invention provides microelectronic component assemblies and lead frame structures that may be useful in such assemblies. For example, one such lead...
US-7,132,731 Semiconductor component and assembly having female conductive members
A semiconductor component includes back side pin contacts fabricated using a circuit side fabrication method. The component also includes a thinned semiconductor...
US-7,132,711 Programmable array logic or memory with p-channel devices and asymmetrical tunnel barriers
Structures and methods for programmable array type logic and/or memory with p-channel devices and asymmetrical low tunnel barrier intergate insulators are...
US-7,132,696 Intermeshed guard bands for multiple voltage supply structures on an integrated circuit, and methods of making same
The present invention is generally directed to intermeshed guard bands for multiple voltage supply regions or structures on an integrated circuit, and methods of...
US-7,132,675 Programmable conductor memory cell structure and method therefor
In programmable conductor memory cells, metal ions precipitate out of a glass electrolyte element in response to an applied electric field in one direction only,...
US-7,132,371 Dopant barrier for doped glass in memory devices
A semiconductor device has a diffusion barrier formed between a doped glass layer and surface structures formed on a substrate. The diffusion barrier includes...
US-7,132,366 Method for fabricating semiconductor components using conductive layer and grooves
A method for fabricating semiconductor components such as printed circuit boards, multi chip modules, chip scale packages, and test carriers is provided. The...
US-7,132,355 Method of forming a layer comprising epitaxial silicon and a field effect transistor
This invention includes methods of forming layers comprising epitaxial silicon, and field effect transistors. In one implementation, a method of forming a layer...
US-7,132,348 Low k interconnect dielectric using surface transformation
Systems, devices and methods are provided to improve performance of integrated circuits by providing a low-k insulator. One aspect is an integrated circuit...
US-7,132,299 Method of forming a magnetic random access memory structure
A method for forming an MRAM bit is described that includes providing a covering layer over an integrated circuit structure. In one embodiment, the covering...
US-7,132,201 Transparent amorphous carbon structure in semiconductor devices
A transparent amorphous carbon layer is formed. The transparent amorphous carbon layer has a low absorption coefficient such that the amorphous carbon is...
US-7,132,035 Methods, apparatuses, and substrate assembly structures for fabricating microelectronic components using...
Methods, apparatuses and substrate assembly structures for mechanical and chemical-mechanical planarizing processes used in the manufacturing ...
US-7,131,891 Systems and methods for mechanical and/or chemical-mechanical polishing of microfeature workpieces
Systems and methods for polishing microfeature workpieces. In one embodiment, a method includes determining a status of a characteristic of a microfeature...
US-7,131,889 Method for planarizing microelectronic workpieces
Planarizing machines and methods for accurately planarizing microelectronic workpieces. Several embodiments of the planarizing machines produce a planar surface...
US-7,131,568 Methods for lead penetrating clamping system
An apparatus and method of forming improved wire bonds between the contact pads on semiconductor devices and individual lead frame fingers of a lead frame. The...
US-7,131,391 Plasma reaction chamber liner comprising ruthenium
The invention encompasses a method of enhancing selectivity of etching silicon dioxide relative to one or more organic substances. A material comprising one or...
US-7,131,211 Method and apparatus for measurement of thickness and warpage of substrates
An apparatus comprises one or more pairs of mutually coaxial and opposing linear measuring devices including movable, biased fingers for simultaneously...
US-7,131,195 Method for forming metal contacts on a substrate
Solder bump pads are formed on a semiconductor substrate by way of a semiconductor template that has been micromachined to receive solder paste material. The...
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