Easy To Use Patents Search & Patent Lawyer Directory

At Patents you can conduct a Patent Search, File a Patent Application, find a Patent Attorney, or search available technology through our Patent Exchange. Patents are available using simple keyword or date criteria. If you are looking to hire a patent attorney, you've come to the right place. Protect your idea and hire a patent lawyer.

Searching: micron





Search by keyword, patent number, inventor, assignee, city or state:




Patent # Description
US-7,107,675 Methods for retaining an electrical connector in a receptacle on an electrical component in a computer
Methods for preventing disengagement of electrical connectors in computers are disclosed herein. A method in accordance with one embodiment of the invention...
US-7,107,671 Method of processing a strip of lead frames
A method of processing a strip of lead frames is disclosed. The method includes engaging the strip with a lead frame advancement system, advancing the strip to a...
US-7,107,572 Methods of forming patterned reticles
The invention includes methods of forming patterned reticles. Design features can be introduced into a layout for a reticle prior to optical proximity...
US-7,107,554 Line width check in layout database
A machine-readable medium has a set of machine-readable instructions for causing a computer to perform a method. The method includes checking a layout having a...
US-7,107,415 Posted write buffers and methods of posting write requests in memory modules
A memory module includes a memory hub coupled to several memory devices. The memory hub includes a posted write buffer that stores write requests so that...
US-7,107,412 Distributed processor memory module and method
A memory module for a computer system is removably coupled to a computer system mother-board having a data bus and an address bus. The memory module includes a...
US-7,107,392 Content addressable memory (CAM) device employing a recirculating shift register for data storage
A content addressable memory (CAM) device is described including a plurality of storage locations, each arranged as a recirculating shift register, and plurality...
US-7,107,391 Automatic learning in a CAM
A CAM array which enables a learning process to be an extension of a search process is disclosed. When a search fails to find a matching data in the CAM array,...
US-7,107,390 Parity-scanning and refresh in dynamic memory devices
A method and apparatus that coordinates refresh and parity-scanning in DRAM-based devices such that parity-scan operations substitute for refresh operations when...
US-7,107,117 Sorting a group of integrated circuit devices for those devices requiring special testing
A method for sorting integrated circuit (IC) devices of the type having a fuse identification (ID) into those devices requiring enhanced reliability testing and...
US-7,107,019 Methods of operating microelectronic devices, and methods of providing microelectronic devices
Microelectronic devices, methods of operating microelectronic devices, and methods of providing microelectronic devices are described. In one embodiment, a...
US-7,106,655 Multi-phase clock signal generator and method having inherently unlimited frequency capability
A delay-lock loop includes several delay lines, all but the first of which is composed of at least one variable delay unit that provides a fixed delay and a...
US-7,106,646 Circuit and method for controlling a clock synchronizing circuit for low power refresh operation
A method and apparatus is provided for idling a clock synchronizing circuit during at least a portion of time during execution of a refresh operation in a memory...
US-7,106,638 Active termination circuit and method for controlling the impedance of external integrated circuit terminals
An active termination circuit is used to set the input impedance of a plurality of input terminals. Each of the input terminals is coupled to a supply voltage...
US-7,106,637 Asynchronous interface circuit and method for a pseudo-static memory device
An asynchronous address interface circuit and method for converting unrestricted randomly scheduled address transitions of memory address signals into scheduled...
US-7,106,611 Wavelength division multiplexed memory module, memory system and method
A computer system includes a controller linked to a plurality of memory modules each of which has an optical memory hub and several memory devices coupled to the...
US-7,106,490 Methods and systems for improved boundary contrast
The present invention relates to methods and systems that define feature boundaries in a radiation sensitive medium on a workpiece using a diffraction-type...
US-7,106,367 Integrated CMOS imager and microcontroller
A method and apparatus providing a CMOS imager with an integrated controller on a common integrated circuit substrate. Also integrated on the common substrate...
US-7,106,201 Communication devices, remote intelligent communication devices, electronic communication devices, methods of...
The present invention provides electronic communication devices, methods of forming electrical communication devices, and communications methods. An electronic...
US-7,105,997 Field emitter devices with emitters having implanted layer
Structures and methods to ease electron emission and limit outgassing so as to inhibit degradation to the electron beam of a field emitter device are described....
US-7,105,992 Field emission device having insulated column lines and method of manufacture
An FED and a method of manufacture are provided. The FED includes a cathode assembly containing an improved column line structure. The column line structure...
US-7,105,930 Semiconductor substrates including I/O redistribution using wire bonds and anisotropically conductive film,...
Methods and apparatus for eliminating wire sweep and shorting while avoiding the use of under-bump metallization and high cost attendant to the use of...
US-7,105,921 Semiconductor assemblies having electrophoretically insulated vias
Methods are provided for creating lined vias in semiconductor substrates. Using electrophoretic deposition techniques, micelles of a lining material are...
US-7,105,918 Interposer with flexible solder pad elements and methods of manufacturing the same
Various embodiments of an interposer for mounting a semiconductor die, as well as methods for forming the interposer, are disclosed. The interposer includes...
US-7,105,914 Integrated circuit and seed layers
Structures are provided which improve performance in integrated circuits. The structures include a diffusion barrier and a seed layer in an integrated circuit...
US-7,105,899 Transistor structure having reduced transistor leakage attributes
Undesirable transistor leakage in transistor structures becomes greatly reduced in substrates having a doped implant region formed via pulling back first and...
US-7,105,884 Memory circuitry with plurality of capacitors received within an insulative layer well
A method of forming memory circuitry having a memory array having a plurality of memory capacitors and having peripheral memory circuitry operatively configured...
US-7,105,881 DRAMS constructions and DRAM devices
The invention includes a DRAM device. The device has an access transistor construction, and the access transistor construction has a pair of source/drain...
US-7,105,864 Non-volatile zero field splitting resonance memory
A low-volatility or non-volatility memory device utilizing zero field splitting properties to store data. In response to an electrical pulse or a light pulse, in...
US-7,105,841 Photolithographic techniques for producing angled lines
The present subject matter allows non-orthogonal lines to be formed at the same thickness as the orthogonal lines so as to promote compact designs, to be formed...
US-7,105,793 CMOS pixels for ALC and CDS and methods of forming the same
Embodiments of the invention provide pixel cells that allow both automatic light control and correlated double sampling operations. The pixel cell includes first...
US-7,105,461 Composite dielectric forming methods and composite dielectrics
A composite dielectric forming method includes atomic layer depositing alternate layers of hafnium oxide and lanthanum oxide over a substrate. The hafnium oxide...
US-7,105,441 Preheating of chemical vapor deposition precursors
Chemical vapor deposition systems include elements to preheat reactant gases prior to reacting the gases to form layers of a material on a substrate, which...
US-7,105,437 Methods for creating electrophoretically insulated vias in semiconductive substrates
Methods are provided for creating lined vias in semiconductor substrates. Using electrophoretic deposition techniques, micelles of a lining material are...
US-7,105,432 Method of locating conductive spheres utilizing screen and hopper of solder balls
Methods for placing conductive spheres on prefluxed bond pads of a substrate using a stencil plate with a pattern of through-holes positioned over the bond pads....
US-7,105,431 Masking methods
The invention includes masking methods. In one implementation, a masking material comprising boron doped amorphous carbon is formed over a feature formed on a...
US-7,105,411 Methods of forming a transistor gate
A method of forming a transistor gate includes forming a gate oxide layer over a semiconductive substrate. Chlorine is provided within the gate oxide layer. A...
US-7,105,405 Rugged metal electrodes for metal-insulator-metal capacitors
Thin film metal-insulator-metal capacitors having enhanced surface area are formed by a substituting metal for silicon in a preformed electrode geometry. The...
US-7,105,403 Double sided container capacitor for a semiconductor device and method for forming same
A method for forming a double sided container capacitor comprises forming a first capacitor top plate layer within a recess in a dielectric layer, then forming a...
US-7,105,402 Semiconductor constructions, and methods of forming semiconductor constructions
The invention includes a DRAM array having a structure therein which includes a first material separated from a second material by an intervening insulative...
US-7,105,388 Method of forming at least one interconnection to a source/drain region in silicon-on-insulator integrated...
In one aspect, the invention provides a method of forming an electrical connection in an integrated circuitry device. According to one preferred implementation,...
US-7,105,386 High density SRAM cell with latched vertical transistors
High density static memory cells and arrays containing gated lateral bipolar transistors which can be latched in a bistable on state. Each transistor memory cell...
US-7,105,380 Method of temporarily securing a die to a burn-in carrier
A method of using adhesive tape to temporarily retain a die being temporarily held in a fixture during testing and burn-in. The method of the present invention...
US-7,105,366 Method for in-line testing of flip-chip semiconductor assemblies
Flip-chip semiconductor assemblies, each including integrated circuit (IC) dice and an associated substrate, are electrically tested before encapsulation using...
US-7,105,278 Pattern mask with features to minimize the effect of aberrations
A semiconductor pattern mask that might otherwise exhibit three-fold symmetry, which could give rise to distorted semiconductor features in the presence of...
US-7,105,208 Methods and processes utilizing microwave excitation
The invention includes methods and processes in which microwave radiation is utilized to activate at least one component within a reaction chamber during...
US-7,105,065 Metal layer forming methods and capacitor electrode forming methods
A capacitor electrode forming method includes chemisorbing a layer of at least one metal precursor at least one monolayer thick on a substrate, the layer...
US-7,104,748 Methods for use with tray-based integrated circuit device handling systems
A stack processing tray for use with tray-based integrated circuit device handling systems. The stack processing tray has a plurality of cells, each cell being...
US-7,103,791 Interleaved delay line for phase locked and delay locked loops
An interleaved delay line for use in phase locked and delay locked loops is comprised of a first portion providing a variable amount of delay substantially...
US-7,103,742 Burst/pipelined edo memory device
An integrated circuit memory device is designed for high speed data access and for compatibility with existing memory systems. An address strobe signal is used...
← Previous | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 | Next →

File A Patent Application

  • Protect your idea -- Don't let someone else file first. Learn more.

  • 3 Easy Steps -- Complete Form, application Review, and File. See our process.

  • Attorney Review -- Have your application reviewed by a Patent Attorney. See what's included.