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Patent # Description
US-7,101,586 Method to increase the emission current in FED displays through the surface modification of the emitters
A system and method for fabricating a FED device is disclosed. The system and method provide for use of PECVD hydrogenation followed by nitrogen plasma treatment...
US-7,101,435 Methods for epitaxial silicon growth
Methods of cleaning substrates and growing epitaxial silicon thereon are provided. Wafers are exposed to a plasma for a sufficient time prior to epitaxial...
US-7,099,992 Distributed programmable priority encoder capable of finding the longest match in a single operation
A distributed, hierarchically-structured, programmable priority encoder for a content addressable memory (CAM) device including at least one section, the section...
US-7,099,989 System and technique to reduce cycle time by performing column redundancy checks during a delay to accommodate...
A memory device includes a memory cell array, an addressing circuit, a data communication circuit and a control circuit. The addressing circuit receives first...
US-7,099,221 Memory controller method and system compensating for memory cell data losses
A computer system includes a memory controller coupled to a memory module containing several DRAMs. The memory module also includes a non-volatile memory storing...
US-7,099,220 Methods for erasing flash memory
Methods for erasing flash memory using a decrease in magnitude of a source voltage of a first polarity to increase the magnitude of a control gate voltage of a...
US-7,099,212 Embedded ROM device using substrate leakage
A ROM embedded DRAM provides ROM cells that can be programmed to a single state. The ROM cells include capacitors having a storage node. The storage node is...
US-7,099,195 Methods for neutralizing holes in tunnel oxides of floating-gate memory cells and devices
Methods for neutralizing holes in tunnel oxides of floating-gate memory cells and devices using a decrease in magnitude of a source voltage of a first polarity...
US-7,099,174 Metal wiring pattern for memory devices
A memory integrated circuit having three layers of metallic traces disposed over a substrate assembly including various active devices. The traces are arranged...
US-7,099,172 Static content addressable memory cell
A static content addressable memory (CAM) cell. The CAM cell includes a latch having complementary data nodes capacitively coupled to ground, first and second...
US-7,098,724 Forward biasing protection circuit
A forward biasing protection circuit is provided. More specifically, there is provided a device comprising a transistor, a resistive element coupled to the body...
US-7,098,714 Centralizing the lock point of a synchronous circuit
A system and method to establish the lock point of a digital synchronous circuit (e.g., a DLL) at the center of or close to the center of its delay line is...
US-7,098,587 Preventing junction leakage in field emission devices
An apparatus and a method for stabilizing the threshold voltage in an active matrix field emission device are disclosed. The method includes the formation of...
US-7,098,527 Integrated circuit package electrical enhancement with improved lead frame design
A configuration for a conventional lead frame for conserving limited leads and for allowing the location of bond pads anywhere on the periphery of the...
US-7,098,503 Circuitry and capacitors comprising roughened platinum layers
In one aspect, the invention includes a method of forming a roughened layer of platinum, comprising: a) providing a substrate within a reaction chamber; b)...
US-7,098,475 Apparatuses configured to engage a conductive pad
A method of engaging electrically conductive test pads on a semiconductor substrate having integrated circuitry for operability testing thereof includes: a)...
US-7,098,128 Method for filling electrically different features
Methods of electroless filling electrically different features such as contact openings to form interconnects and conductive contacts, and semiconductor devices,...
US-7,098,122 Method of fabricating a vertically integrated memory cell
A unique cell structure for use in flash memory cell and a method of fabricating the memory cell. More particularly, a vertically integrated transistor having a...
US-7,098,105 Methods for forming semiconductor structures
The invention includes a semiconductor structure having a gateline lattice surrounding vertical source/drain regions. In some aspects, the source/drain regions...
US-7,098,068 Method of forming a chalcogenide material containing device
Embodiments of the invention provide a method of forming a chalcogenide material containing device, and particularly resistance variable memory elements. A stack...
US-7,097,782 Method of exposing a substrate to a surface microwave plasma, etching method, deposition method, surface...
In certain implementations, methods and apparatus include an antenna assembly having at least two overlapping and movable surface microwave plasma antennas. The...
US-7,097,546 System and method for reducing surface defects in integrated circuits
The fabrication of integrated circuits entails the repeated application of many basic processing steps, for instance, planarization--the process of making a...
US-7,097,526 Method of forming nitrogen and phosphorus doped amorphous silicon as resistor for field emission display device...
Described herein is a resistor layer for use in field emission display devices and the like, and its method of manufacture. The resistor layer is an amorphous...
US-7,097,373 Printer
A printer including a cutting portion including a plate-shaped fixed blade, a plate-shaped movable blade and a driving unit, which drives the movable blade back...
US-7,096,452 Method and device for checking lithography data
Devices and methods are provided that include advantages such as the ability to identify sizes, shapes and locations of frequently unwanted additional features...
US-7,096,446 Hierarchical semiconductor design
Hierarchical semiconductor structure design is disclosed. One aspect of the invention is a computerized system that includes a semiconductor structure (such as a...
US-7,096,370 Data security for digital data storage
A computer system encrypts user generated data with an encryption process, wherein the encryption process is defined at least in part with information assigned...
US-7,096,304 Apparatus and method for managing voltage buses
The present technique relates to a method and apparatus for managing voltage buses. In a memory device, such as SRAM or DRAM, a periphery voltage bus may supply...
US-7,096,283 Synchronous flash memory with status burst output
A synchronous flash memory includes an array of non-volatile memory cells. The memory array is arranged in rows and columns, and can be further arranged in...
US-7,095,885 Method for measuring registration of overlapping material layers of an integrated circuit
A method and apparatus for measuring registration between two or more integrated circuit layers is disclosed. Images of actual operative circuitry of different...
US-7,095,667 Noise resistant small signal sensing circuit for a memory device
Apparatus and method for data sensing circuitry that uses averaging to sense small differences in signal levels representing data states. The apparatus...
US-7,095,660 Sending signal through integrated circuit during setup time
A memory device includes a control circuit for initiating a read operation and a write operation in response to a combination of input signals during a setup...
US-7,095,658 Flash memory data bus for synchronous burst read page
Memory device is described that utilizes a reduced number of sense amplifiers to sense the data bits of a selected column page. The sense amplifiers are...
US-7,095,653 Common wordline flash array architecture
The memory area on a die required for row (X) and column (Y) decoders is reduced by a plurality of memory array blocks sharing wordlines to a single row decoder....
US-7,095,440 Photodiode-type pixel for global electronic shutter and reduced lag
Operation for global electronic shutter photodiode-type pixels. In a first mode of operation, lag is reduced through global reset of the photodiode array and...
US-7,095,261 Clock capture in clock synchronization circuitry
Clock capturing synchronization circuitry first generates a synchronized clock signal from a reference clock signal, then captures the synchronized clock signal,...
US-7,095,242 In-tray burn-in board, device and test assembly for testing integrated circuit devices in situ on processing trays
A burn-in board for burn-in and electrical testing of a plurality of integrated circuit devices that are disposed in one or more processing trays may include a...
US-7,095,122 Reduced-dimension microelectronic component assemblies with wire bonds and methods of making same
The present disclosure suggests various microelectronic component assembly designs and methods for manufacturing microelectronic component assemblies. In one...
US-7,095,115 Circuit substrates, semiconductor packages, and ball grid arrays
In one implementation, a circuit substrate includes a substrate having opposing sides. At least one of the sides is configured for transfer mold packaging and...
US-7,095,106 Collars, support structures, and forms for protruding conductive structures
Collars, support structures, or forms for protruding conductive structures include apertures or receptacles through which the conductive structure may extend....
US-7,095,097 Integrated circuit device having reduced bow and method for making same
An integrated circuit device includes a semiconductor component coupled with a lead frame, and an integrated circuit package encompassing at least a portion of...
US-7,095,095 Semiconductor constructions
The invention includes a semiconductor construction. The construction has a semiconductor material die with a front surface, a back surface in opposing relation...
US-7,095,088 System and device including a barrier layer
Systems and devices are disclosed utilizing a silicon-containing barrier layer. A semiconductor device is disclosed and includes a substrate, a gate oxide, a...
US-7,095,083 Methods for making semiconductor structures having high-speed areas and high-density areas
Methods for making a semiconductor structure are discussed. The methods include forming openings in a high-density area and a high-speed area, and forming a...
US-7,095,075 Apparatus and method for split transistor memory having improved endurance
The present invention includes floating gate transistor structures used in non-volatile memory devices such as flash memory devices. In one embodiment, a system...
US-7,094,700 Plasma etching methods and methods of forming memory devices comprising a chalcogenide comprising layer...
In one implementation, a plasma etching method comprises forming a Ge.sub.xSe.sub.y chalcogenide comprising layer over a substrate. A mask comprising an organic...
US-7,094,699 Etch aided by electrically shorting upper and lower sidewall portions during the formation of a semiconductor...
A method used to fabricate a semiconductor device comprises etching a dielectric which results in an undesirable charge buildup along a sidewall formed in the...
US-7,094,695 Apparatus and method for conditioning a polishing pad used for mechanical and/or chemical-mechanical planarization
Conditioning apparatuses and methods for conditioning polishing pads used for mechanical and/or chemical-mechanical planarization of micro-device workpieces are...
US-7,094,690 Deposition methods and apparatuses providing surface activation
A deposition method includes, at a first temperature, contacting a substrate with a surface activation agent and adsorbing a first layer over the substrate. At a...
US-7,094,682 Coating of copper and silver air bridge structures to improve electromigration resistance and other applications
An improved electrical interconnect for an integrated circuit and methods for providing the same are disclosed. The electrical interconnect includes an air...
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