Easy To Use Patents Search & Patent Lawyer Directory

At Patents you can conduct a Patent Search, File a Patent Application, find a Patent Attorney, or search available technology through our Patent Exchange. Patents are available using simple keyword or date criteria. If you are looking to hire a patent attorney, you've come to the right place. Protect your idea and hire a patent lawyer.

Searching: micron





Search by keyword, patent number, inventor, assignee, city or state:




Patent # Description
US-7,129,128 Method of improved high K dielectric-polysilicon interface for CMOS devices
Methods for forming dielectric layers over polysilicon substrates, useful in the construction of capacitors and other semiconductor circuit components are...
US-7,129,114 Methods relating to singulating semiconductor wafers and wafer scale assemblies
Methods relating to the singulation of dice from semiconductor wafers. Trenches or channels are formed in the bottom surface of a semiconductor wafer,...
US-7,128,842 Polyimide as a mask in vapor hydrogen fluoride etching
A layer of polyimide or polysilicon is used as a mask in vapor hydrogen fluoride etching. Both non-photosensitive and photosensitive type polyimide may be used....
US-7,128,787 Atomic layer deposition method
An atomic layer deposition method includes positioning a semiconductor substrate within an atomic layer deposition chamber. A first precursor gas is flowed to...
US-7,128,551 Surface smoothing of stereolithographically formed 3-D objects
A stereolithographic method and apparatus for forming polymeric structures comprising a plurality of overlying layers, each layer formed by polymerizing a thin...
US-7,127,622 Memory subsystem voltage control and method
A method and apparatus for providing a preferred operating voltage to a memory device as specified by a stored configuration parameter. The apparatus includes a...
US-7,127,559 Caching of dynamic arrays
Systems and methods are provided for caching dynamic arrays. According to one aspect, a cache memory device is provided for caching dynamic arrays or dynamic...
US-7,127,365 Method for identifying a defective die site
The present invention relates to the marking and identification of defective die sites on a mounting substrate. A mounting substrate is provided which is...
US-7,127,319 Reducing asymmetrically deposited film induced registration error
Methods, systems, products and apparatuses are disclosed herein relating to registration and asymmetrically deposited films, and more specifically, to reducing...
US-7,126,874 Memory system and method for strobing data, command and address signals
A memory system couples command, address or write data signals from a memory controller to a memory device and read data signals from the memory device to the...
US-7,126,871 Circuits and methods to protect a gate dielectric antifuse
According to embodiments of the present invention, an antifuse circuit is operated by coupling an elevated voltage to a first terminal of an antifuse,...
US-7,126,863 Active termination control
A method and apparatus are provided for active termination control in a memory. The memory turns on active termination based on information programmed into one...
US-7,126,394 History-based slew rate control to reduce intersymbol interference
In one aspect of the invention, a method of reducing intersymbol interference on a signal line is disclosed. A state machine records previous bits that were...
US-7,126,393 Delay circuit with reset-based forward path static delay
A delay locked loop circuit and method of operating the same. The delay locked loop circuit comprises a forward delay path having a variable delay portion and a...
US-7,126,380 Distributed clock generator for semiconductor devices and related methods of operating semiconductor devices
A distributed clock generator for a semiconductor device. In one embodiment, the clock generator is not localized in one particular location on the semiconductor...
US-7,126,317 Apparatus and methods for regulated voltage
An electronic system according to various aspects of the present invention includes a memory and a supply regulation circuit having a regulated output to provide...
US-7,126,228 Apparatus for processing semiconductor devices in a singulated form
Improved methods and apparatus are provided for the handling and testing of semiconductor devices. One embodiment comprises a die carrier for one or more...
US-7,126,224 Semiconductor substrate-based interconnection assembly for semiconductor device bearing external connection...
The present invention relates to a method of forming interconnections for a temporary package, wherein the interconnections are capable of receiving solder balls...
US-7,126,205 Devices having improved capacitance and methods of their fabrication
A capacitor formed by a process using only two deposition steps and a dielectric formed by oxidizing a metal layer in an electrolytic solution. The capacitor has...
US-7,126,200 Integrated circuits with contemporaneously formed array electrodes and logic interconnects
The invention relates to interconnects for an integrated circuit memory device. Embodiments of the invention include processes to fabricate interconnects for...
US-7,126,195 Method for forming a metallization layer
A method for forming a metallization layer (30). A first layer (14) is formed outwardly from a semiconductor substrate (10). Contact vias (16) are formed through...
US-7,126,183 Programmable array logic or memory with p-channel devices and asymmetrical tunnel barriers
Structures and methods for programmable array type logic and/or memory with p-channel devices and asymmetrical low tunnel barrier intergate insulators are...
US-7,126,182 Memory circuitry
The invention includes memory circuitry. In one implementation, memory circuitry includes a memory array comprising a plurality of memory cell capacitors....
US-7,126,181 Capacitor constructions
The invention includes methods of forming circuit devices. A metal-containing material comprising a thickness of no more than 20 .ANG. (or alternatively...
US-7,126,179 Memory cell intermediate structure
A method of filling vias for a PCRAM cell with a metal is described. A PCRAM intermediate structure including a substrate, a first conductor, and an insulator...
US-7,125,815 Methods of forming a phosphorous doped silicon dioxide comprising layer
This invention includes methods of forming phosphorus doped silicon dioxide comprising layers, and methods of forming trench isolation in the fabrication of...
US-7,125,809 Method and material for removing etch residue from high aspect ratio contact surfaces
Contact openings in semiconductor substrates are formed through insulative layers using an etchant material. The etchant typically leaves behind a layer of etch...
US-7,125,804 Etching methods and apparatus and substrate assemblies produced therewith
Methods and apparatus for etching substrates such as silicon wafers are provided. In one specific approach, a surface of the substrate assembly is covered with a...
US-7,125,800 Methods for making nearly planar dielectric films in integrated circuits
In the fabrication of integrated circuits, one specific technique for making surfaces flat is chemical-mechanical planarization. However, this technique is quite...
US-7,125,781 Methods of forming capacitor devices
The invention includes semiconductor constructions, and also includes methods of forming pluralities of capacitor devices. An exemplary method of the invention...
US-7,125,768 Method for reducing single bit data loss in a memory circuit
The present invention includes a method for reducing random bit data loss in a memory circuit. The method comprises a semiconductor layer that has a surface. The...
US-7,125,749 Varied-thickness heat sink for integrated circuit (IC) packages and method of fabricating IC packages
An integrated circuit package includes a package body, such as a transfer molded plastic or preformed ceramic package body, having an integrated circuit die...
US-7,125,748 Methods of encapsulating selected locations of a semiconductor die assembly using a thick solder mask
A solder mask includes an opening through which intermediate conductive elements may be positioned to connect bond pads of a semiconductor die exposed through an...
US-7,124,384 Capacitor layout technique for reduction of fixed pattern noise in a CMOS sensor
A new capacitor architecture includes a front plate of the capacitor formed form a first polysilicon layer. The front plate is surround by a first dielectric...
US-7,124,260 Modified persistent auto precharge command protocol system and method for memory devices
A method of operating a memory device includes placing the memory device in a persistent auto precharge mode of operation, applying a disable command to the...
US-7,124,256 Memory device for burst or pipelined operation with mode selection circuitry
An integrated circuit memory device is designed for high speed data access and for compatibility with existing memory systems. An address strobe signal is used...
US-7,124,223 Routability for memory devices
A computer system provides improved routability for memory modules. Chips are placed on the back side of the module directly behind the chips on the front side,...
US-7,124,050 Method in an integrated circuit (IC) manufacturing process for identifying and redirecting IC's mis-processed...
A method of manufacturing IC devices from semiconductor wafers includes providing the wafers and fabricating ICs on the wafers. At probe, a unique fuse ID is...
US-7,123,541 Memory with address management
The present invention allows for the reduction in power consumption of memory devices. A memory device in one embodiment prohibits address signal propagation on...
US-7,123,530 AC sensing for a resistive memory
Alternating current is used to sense a logic state of a memory cell that has a resistive memory element. The memory element can be in an array and a memory...
US-7,123,525 Phase detector for all-digital phase locked and delay locked loops
A phase detector is comprised of two cross-coupled gates which are capable of phase discrimination down to a level of approximately 10 picoseconds. An arbiter...
US-7,123,522 Method and apparatus for achieving low power consumption during power down
The present technique relates to a method and apparatus to provide a deep power down mode. In a memory device, such as DRAM or SRAM, various internal voltage...
US-7,123,521 Random cache read
A non-volatile memory is described that utilizes a cache read mode of operation, where a next page of memory is being read/sensed from the memory array by the...
US-7,123,516 Erase verify for nonvolatile memory using bitline/reference current-to-voltage converters
A memory device verify system determines a state of memory cells in a memory. The memory includes a memory array having a plurality of memory cells coupled to...
US-7,123,513 Erase verify for non-volatile memory using a reference current-to-voltage converter
A memory device verify system determines a state of memory cells in a memory. The memory includes a memory array having a plurality of memory cells coupled to...
US-7,123,512 Contiguous block addressing scheme
An improved non-volatile erase block memory device apparatus and method is described that incorporates an improved addressing scheme to provide for extended...
US-7,123,503 Writing to ferroelectric memory devices
A programming voltage is applied to a first word line coupled to a control gate of a selected ferroelectric memory cell in an array of ferroelectric memory...
US-7,123,148 Wireless communication devices, radio frequency identification devices, radio frequency identification device...
The present invention provides radio frequency identification devices, remote communication devices, identification systems, communication methods, and...
US-7,123,046 Apparatus for adaptively adjusting a data receiver
Offsets and timing skews in data signals captured in a data receiver are reduced by adaptively adjusting a transition threshold of the data receiver. A data...
US-7,123,042 Methods, apparatus and systems for wafer-level burn-in stressing of semiconductor devices
A large-scale support carries semiconductor devices and at least one pair of common conductive regions in communication therewith. Each common conductive region...
← Previous | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 | Next →

File A Patent Application

  • Protect your idea -- Don't let someone else file first. Learn more.

  • 3 Easy Steps -- Complete Form, application Review, and File. See our process.

  • Attorney Review -- Have your application reviewed by a Patent Attorney. See what's included.