Easy To Use Patents Search & Patent Lawyer Directory

At Patents you can conduct a Patent Search, File a Patent Application, find a Patent Attorney, or search available technology through our Patent Exchange. Patents are available using simple keyword or date criteria. If you are looking to hire a patent attorney, you've come to the right place. Protect your idea and hire a patent lawyer.

Searching: micron





Search by keyword, patent number, inventor, assignee, city or state:




Patent # Description
US-7,103,719 System and method for managing a cache memory
A processing system optimized for data string manipulations includes data string execution circuitry associated with a bus interface unit or memory controller....
US-7,103,682 Apparatus and methods for transmitting data to a device having distributed configuration storage
Systems and methods, for providing distributed configuration storage are presented. The configuration storage is divided into distributed configuration target...
US-7,103,598 Software distribution method and apparatus
The present invention provides for a method and apparatus for distributing digital information, such as software applications, to application users. By providing...
US-7,103,126 Method and circuit for adjusting the timing of output data based on the current and future states of the output...
A clock synchronization circuit receives an input clock signal along with current and future data signals. The clock synchronization circuit generates a phase...
US-7,102,957 Reduction of fusible links and associated circuitry on memory dies
The number of fusible links and other circuit components required to provide memory cell redundancy are reduced by sharing physical memory locations among...
US-7,102,956 Reduction of fusible links and associated circuitry on memory dies
The number of fusible links and other circuit components required to provide memory cell redundancy are reduced by sharing physical memory locations among...
US-7,102,955 Reduction of fusible links and associated circuitry on memory dies
The number of fusible links and other circuit components required to provide memory cell redundancy are reduced by sharing physical memory locations among...
US-7,102,937 Solution to DQS postamble ringing problem in memory chips
The disclosed system and method significantly reduce or eliminate DQS postamble ringing problem in modern high-speed memory chips, allowing the memory chips to...
US-7,102,932 Input and output buffers having symmetrical operating characteristics and immunity from voltage variations
A pair of self-biased differential amplifiers having a non-symmetrical topology are combined to provide a self-biased differential amplifier having a symmetrical...
US-7,102,913 Sensing scheme for programmable resistance memory using voltage coefficient characteristics
A method and apparatus for sensing the resistance state of data in a resistance memory cell by using the voltage coefficient of the cell instead of only its...
US-7,102,907 Wavelength division multiplexed memory module, memory system and method
A computer system includes a controller linked to a plurality of memory modules each of which has an optical memory hub and several memory devices coupled to the...
US-7,102,906 Logic and memory device integration
Memory devices are adapted for direct interface or virtual integration with a processor or other logic device through a local bus and isolated from a system bus....
US-7,102,737 Method and apparatus for automated, in situ material detection using filtered fluoresced, reflected, or...
A method and apparatus for detection of a particular material, such as photo-resist material, on a sample surface are disclosed. A narrow beam of light is...
US-7,102,450 Method and apparatus for providing clock signals at different locations with minimal clock skew
A tapped phase shift ring oscillator may be used to provide multiple clock signals having variable phase delays. Phase delays may be selected to compensate for...
US-7,102,361 Delay lock circuit having self-calibrating loop
A delay lock circuit includes a measuring path, a forward path, and a feedback path. The measuring path samples a pulse with a reference signal in a measurement...
US-7,102,217 Interposer substrates with reinforced interconnect slots, and semiconductor die packages including same
A board-on-chip (BOC) semiconductor package includes a multisegmented, longitudinally slotted interposer substrate through which an elongate row of die bond pads...
US-7,102,191 Memory device with high dielectric constant gate dielectrics and metal floating gates
A memory cell transistor includes a high dielectric constant tunnel insulator, a metal floating gate, and a high dielectric constant inter-gate insulator...
US-7,102,184 Image device and photodiode structure
The invention provides a photodiode with an increased charge collection area, laterally spaced from an adjacent isolation region. Dopant ions of a first...
US-7,102,180 CMOS imager pixel designs
A charge storage capacitor which is connected to various light sensitive and/or electrical elements of a CMOS imager, as well as methods of formation, are...
US-7,102,151 Small electrode for a chalcogenide switching device and method for fabricating same
A memory cell and a method of fabricating the memory cell having a small active area. By forming a spacer in a window that is sized at the photolithographic...
US-7,101,815 Method for improving thickness uniformity of deposited ozone-TEOS silicate glass layers
A method for depositing highly conformal silicate glass layers via chemical vapor deposition through the reaction of TEOS and O.sub.3 is provided, comprising...
US-7,101,814 Masking without photolithography during the formation of a semiconductor device
A method for forming a semiconductor device comprises forming a dielectric layer over a semiconductor wafer substrate assembly having closely-spaced regions,...
US-7,101,813 Atomic layer deposited Zr-Sn-Ti-O films
A dielectric film containing atomic layer deposited Zr--Sn--Ti--O and a method of fabricating such a dielectric film produce a reliable dielectric layer having...
US-7,101,792 Methods of plating via interconnects
Methods for filling high aspect ratio vias with conductive material. At least one high aspect ratio via is formed in the backside of a semiconductor substrate....
US-7,101,779 Method of forming barrier layers
Mixed metal aluminum nitride and boride diffusion barriers and electrodes for integrated circuits, particularly for DRAM cell capacitors. Also provided are...
US-7,101,778 Transmission lines for CMOS integrated circuits
Improved methods and structures are provided for impedance-controlled low-loss lines in CMOS integrated circuits. The present invention offers a reduction in...
US-7,101,771 Spin coating for maximum fill characteristic yielding a planarized thin film surface
A method for spinning a material onto a semiconductor device structure so as to substantially fill recesses formed in a surface of the semiconductor device...
US-7,101,770 Capacitive techniques to reduce noise in high speed interconnections
Improved methods and structures are provided using capacitive techniques to reduce noise in high speed interconnections, such as in CMOS integrated circuits. The...
US-7,101,767 Methods of forming capacitors
In one implementation, an opening within a capacitor electrode forming layer is formed over a substrate. A spacing layer is deposited over the capacitor...
US-7,101,756 Methods for enhancing capacitors having roughened features to increase charge-storage capacity
Structures and methods for making a semiconductor structure are discussed. The semiconductor structure includes a rough surface having protrusions formed from an...
US-7,101,747 Dual work function metal gates and methods of forming
Complementary transistors and methods of forming the complementary transistors on a semiconductor assembly are described. The transistors can be formed from a...
US-7,101,738 Gate dielectric antifuse circuit to protect a high-voltage transistor
According to embodiments of the present invention, circuits have elements to protect a high-voltage transistor in a gate dielectric antifuse circuit. An antifuse...
US-7,101,737 Method of encapsulating interconnecting units in packaged microelectronic devices
Methods and apparatuses for encapsulating a microelectronic die or other components in the fabrication of packaged microelectronic devices. In one aspect of the...
US-7,101,730 Method of manufacturing a stackable ball grid array
A method of manufacturing a stackable package to create a 3-dimensional memory array using ball grid array technology. Specifically, memory chips are coupled to...
US-7,101,727 Passivation planarization
A pixel cell is formed by locating a first passivation layer over the final layer of metal lines. Subsequently, the uneven, non-uniform passivation layer is...
US-7,101,594 Methods of forming capacitor constructions
The invention includes a method of treating a predominantly inorganic dielectric material on a semiconductor wafer. A laser is utilized to generate activated...
US-7,101,586 Method to increase the emission current in FED displays through the surface modification of the emitters
A system and method for fabricating a FED device is disclosed. The system and method provide for use of PECVD hydrogenation followed by nitrogen plasma treatment...
US-7,101,435 Methods for epitaxial silicon growth
Methods of cleaning substrates and growing epitaxial silicon thereon are provided. Wafers are exposed to a plasma for a sufficient time prior to epitaxial...
US-7,099,992 Distributed programmable priority encoder capable of finding the longest match in a single operation
A distributed, hierarchically-structured, programmable priority encoder for a content addressable memory (CAM) device including at least one section, the section...
US-7,099,989 System and technique to reduce cycle time by performing column redundancy checks during a delay to accommodate...
A memory device includes a memory cell array, an addressing circuit, a data communication circuit and a control circuit. The addressing circuit receives first...
US-7,099,221 Memory controller method and system compensating for memory cell data losses
A computer system includes a memory controller coupled to a memory module containing several DRAMs. The memory module also includes a non-volatile memory storing...
US-7,099,220 Methods for erasing flash memory
Methods for erasing flash memory using a decrease in magnitude of a source voltage of a first polarity to increase the magnitude of a control gate voltage of a...
US-7,099,212 Embedded ROM device using substrate leakage
A ROM embedded DRAM provides ROM cells that can be programmed to a single state. The ROM cells include capacitors having a storage node. The storage node is...
US-7,099,195 Methods for neutralizing holes in tunnel oxides of floating-gate memory cells and devices
Methods for neutralizing holes in tunnel oxides of floating-gate memory cells and devices using a decrease in magnitude of a source voltage of a first polarity...
US-7,099,174 Metal wiring pattern for memory devices
A memory integrated circuit having three layers of metallic traces disposed over a substrate assembly including various active devices. The traces are arranged...
US-7,099,172 Static content addressable memory cell
A static content addressable memory (CAM) cell. The CAM cell includes a latch having complementary data nodes capacitively coupled to ground, first and second...
US-7,098,724 Forward biasing protection circuit
A forward biasing protection circuit is provided. More specifically, there is provided a device comprising a transistor, a resistive element coupled to the body...
US-7,098,714 Centralizing the lock point of a synchronous circuit
A system and method to establish the lock point of a digital synchronous circuit (e.g., a DLL) at the center of or close to the center of its delay line is...
US-7,098,587 Preventing junction leakage in field emission devices
An apparatus and a method for stabilizing the threshold voltage in an active matrix field emission device are disclosed. The method includes the formation of...
US-7,098,527 Integrated circuit package electrical enhancement with improved lead frame design
A configuration for a conventional lead frame for conserving limited leads and for allowing the location of bond pads anywhere on the periphery of the...
← Previous | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 | Next →

File A Patent Application

  • Protect your idea -- Don't let someone else file first. Learn more.

  • 3 Easy Steps -- Complete Form, application Review, and File. See our process.

  • Attorney Review -- Have your application reviewed by a Patent Attorney. See what's included.