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Patent # Description
US-7,115,528 Systems and method for forming silicon oxide layers
A method of forming (and apparatus for forming) a metal oxide layer, preferably a dielectric layer, on a substrate, particularly a semiconductor substrate or...
US-7,115,527 Methods of etching an aluminum oxide comprising substrate, and methods of forming a capacitor
This invention methods of etching an aluminum oxide comprising substrate, and methods of forming capacitors. In one implementation, a method of etching an...
US-7,115,525 Method for integrated circuit fabrication using pitch multiplication
Different sized features in the array and in the periphery of an integrated circuit are patterned on a substrate in a single step. In particular, a mixed...
US-7,115,524 Methods of processing a semiconductor substrate
The invention includes methods of processing semiconductor substrates. In one implementation, a semiconductor substrate is provided which has an outer surface....
US-7,115,515 Methods for forming capacitor structures
The invention includes methods of forming capacitor structures and removing organic material. An organic material, such as a photoresist, is disposed on a...
US-7,115,512 Methods of forming semiconductor constructions
The invention includes methods by which a fuse box of a semiconductor construction is fabricated to have a substantially uniform layer over fuses extending...
US-7,115,509 Method for forming polysilicon local interconnects
Methods and apparatus are described to facilitate forming memory devices with low resistance polysilicon local interconnects that allow a smaller array feature...
US-7,115,506 Method of making a contact structure
A method and structure are disclosed that are advantageous for aligning a contact plug within a bit line contact corridor (BLCC) to an active area of a DRAM that...
US-7,115,504 Method of forming electrode structure for use in an integrated circuit
An electrode structure includes a first layer of conductive material and a dielectric layer formed on a surface of the first layer. An opening is formed in the...
US-7,115,495 Methods of making projected contact structures for engaging bumped semiconductor devices
A bumped semiconductor device contact structure is disclosed including at least one non-planar contact pad having a plurality of projections extending therefrom...
US-7,115,493 Antifuse structures, methods, and applications
A typical integrated circuit includes millions of microscopic transistors, resistors, and other components interconnected to define a circuit, for example a...
US-7,115,492 Technique for elimination of pitting on silicon substrate during gate stack etch using material in a...
A method for forming a gate stack which minimizes or eliminates damage to the gate dielectric layer and/or silicon substrate during the gate stack formation by...
US-7,115,489 Methods of growing epitaxial silicon
Methods for growing epitaxial silicon are provided. Methods for controlling bottom stacking fault propagation in epitaxial silicon are also provided.
US-7,115,480 Micromechanical strained semiconductor by wafer bonding
One aspect disclosed herein relates to a method for forming a strained semiconductor structure. In various embodiments of the method, a number of recesses are...
US-7,115,458 Gate coupling in floating-gate memory cells
Methods and apparatus utilizing a stepped floating gate structure to facilitate reduced spacing between adjacent cells without significantly impacting parasitic...
US-7,115,451 Methods of forming semiconductor circuitry
The invention includes a method of forming semiconductor circuitry wherein a first semiconductor structure comprising a first monocrystalline semiconductor...
US-7,115,422 Separation apparatus including porous silicon column
A sample separation apparatus including a porous, or rough, capillary column. The porous capillary column includes a matrix which defines pores, and may be...
US-7,115,166 Systems and methods for forming strontium- and/or barium-containing layers
A method of forming (and apparatus for forming) a layer, such as a strontium titanate, barium titanate, or barium-strontium titanate layer, on a substrate by...
US-7,115,016 Apparatus and method for mechanical and/or chemical-mechanical planarization of micro-device workpieces
Planarizing machines and methods for mechanical and/or chemical-mechanical planarization of micro-device workpieces are disclosed herein. In one embodiment, a...
US-7,114,976 Test socket and test system for semiconductor components with easily removable nest
A test socket (52) for a semiconductor component (12) includes a base (54), a movable lid (56), socket contacts (68) for electrically engaging terminal contacts...
US-7,114,669 Methods of operating a liquid vaporizer
The present invention is generally directed to a vaporizer with positive liquid shut-off. In one illustrative embodiment, the vaporizer is comprised of a body, a...
US-7,114,532 Liner for use in processing chamber
A container for use in a processing chamber to lessen the amount of contaminant particles found within the chamber after processing. The container fits closely...
US-7,114,404 System and method for detecting flow in a mass flow controller
Systems and methods are provided for detecting flow in a mass flow controller (MFC). The position of a gate in the MFC is sensed or otherwise determined to...
US-7,114,248 Method of handling an electrical component
A method of handling an electrical component is disclosed. The method includes initiating a first engagement between the electrical component and a conveyor,...
US-7,114,084 Data controlled programmable power supply
A power supply, and a method of controlling the power supply, in which more or less power capacity of the power supply is activated depending on the state of a...
US-7,114,082 Data security for digital data storage
A computing system includes data encryption in the data path between a data source and data storage devices. The data encryption may utilize a key which is...
US-7,114,034 Caching of dynamic arrays
Systems and methods are provided for caching dynamic arrays. According to one aspect, a cache memory device is provided for caching dynamic arrays or dynamic...
US-7,113,435 Data compression read mode for memory testing
Memory devices having a normal mode of operation and a test mode of operation are useful in quality programs. The test mode of operation includes a data...
US-7,113,429 Nor flash memory cell with high storage density
Structures and methods for NOR flash memory cells, arrays and systems are provided. The NOR flash memory cell includes a vertical floating gate transistor...
US-7,112,986 Method for testing using a universal wafer carrier for wafer level die burn-in
A reusable burn-in/test fixture for testing unsingulated dice on a semiconductor wafer consisting of two halves. The first half of the test fixture is a wafer...
US-7,112,985 Method for testing using a universal wafer carrier for wafer level die burn-in
A reusable burn-in/test fixture for testing unsingulated dice on a semiconductor wafer consisting of two halves. The first half of the test fixture is a wafer...
US-7,112,980 System and method for testing devices utilizing capacitively coupled signaling
An apparatus and method for testing a semiconductor device in an AC test regime. The test apparatus includes a test plate capacitively couple to the signal...
US-7,112,878 Die stacking scheme
An improved die stacking scheme is provided. In accordance with one embodiment of the present invention, a multiple die semiconductor assembly is provided...
US-7,112,876 Interposers and other carriers including a slot with laterally recessed area at an end thereof and...
An interposer includes a substantially planar substrate with a slot therethrough. The slot includes a laterally recessed area in only a portion of a periphery...
US-7,112,841 Graded composition metal oxide tunnel barrier interpoly insulators
Structures and methods for programmable array type logic and/or memory devices with graded composition metal oxide tunnel barrier intergate insulators are...
US-7,112,815 Multi-layer memory arrays
Multi-layer memory arrays and methods are provided. A memory array has two or more layers of memory material, each layer of memory material having an array of...
US-7,112,544 Method of atomic layer deposition on plural semiconductor substrates simultaneously
The invention includes a method for treating a plurality of discrete semiconductor substrates. The discrete semiconductor substrates are placed within a reactor...
US-7,112,543 Methods of forming assemblies comprising silicon-doped aluminum oxide
The invention encompasses a method of forming a silicon-doped aluminum oxide. Aluminum oxide and silicon monoxide are co-evaporated. Subsequently, at least some...
US-7,112,542 Methods of forming materials between conductive electrical components, and insulating materials
Methods of forming insulating materials between conductive elements include forming a material adjacent a conductive electrical component comprising: partially...
US-7,112,533 Plasma etching system and method
A system and a process for plasma etching a semiconductor device. The technique comprises periodically applying a heightened voltage bias during the plasma...
US-7,112,531 Silicon oxide co-deposition/etching process
Methods of providing silicon oxide on a substrate in a single process step by simultaneously introducing both a silicon source gas and an etch gas into a CVD...
US-7,112,520 Semiconductor die packages with recessed interconnecting structures and methods for assembling the same
Apparatus and methods relating to semiconductor assemblies. A semiconductor assembly includes an interposer which may be constructed from a flexible material,...
US-7,112,513 Sub-micron space liner and densification process
A method of depositing dielectric material into sub-micron spaces and resultant structures is provided. After a trench is etched in the surface of a wafer, an...
US-7,112,508 Method for forming conductive material in opening and structure regarding same
Method and structure use support layers to assist in planarization processes to form conductive materials (e.g., a Group VIII metal) in an opening. Further, such...
US-7,112,503 Enhanced surface area capacitor fabrication methods
A capacitor fabrication method may include atomic layer depositing a conductive barrier layer to oxygen diffusion over the first electrode. A method may instead...
US-7,112,494 Write once read only memory employing charge trapping in insulators
Structures and methods for write once read only memory employing charge trapping in insulators are provided. The write once read only memory cell includes a...
US-7,112,491 Methods of forming field effect transistors including floating gate field effect transistors
The invention includes methods of forming field effect transistors. In one implementation, a method of forming a field effect transistor having a gate comprising...
US-7,112,488 Source lines for NAND memory devices
Methods and apparatus are provided. A NAND memory device has a source line connected to two or more columns of serially-connected floating-gate transistors. The...
US-7,112,485 Systems and methods for forming zirconium and/or hafnium-containing layers
A method of forming (and apparatus for forming) a zirconium and/or hafnium-containing layer on a substrate, particularly a semiconductor substrate or substrate...
US-7,112,484 Thin film diode integrated with chalcogenide memory cell
An integrated programmable conductor memory cell and diode device in an integrated circuit comprises a diode and a glass electrolyte element, the glass...
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