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Patent # Description
US-9,343,114 Memory arrays and methods of forming electrical contacts
Some embodiments include methods of forming electrical contacts. A row of semiconductor material projections may be formed, with the semiconductor material...
US-9,342,443 Systems and methods for memory system management based on thermal information of a memory system
Methods of mapping memory regions to processes based on thermal data of memory regions are described. In some embodiments, a memory controller may receive a...
US-9,342,371 Boot partitions in memory devices and systems
The present disclosure includes boot partitions in memory devices and systems, and methods associated therewith. One or more embodiments include an array of...
US-9,341,787 Apparatus providing simplified alignment of optical fiber in photonic integrated circuits
A structure for optically aligning an optical fiber to a photonic device and method of fabrication of same. The structure optically aligns an optical fiber to...
US-9,341,651 Probe card and method for manufacturing the same
A probe card for an electric test of a device under test on a working table incorporating a heat source includes a circuit base plate including conductive paths...
US-RE46,005 Method and apparatus for enabling a timing synchronization circuit
A timing control circuit includes a synchronization circuit and a detection circuit. The synchronization circuit includes a main delay line configured to...
US-9,337,776 High-input common-mode differential amplifiers
The present invention discloses a level-shifting circuit to provide an initial stage to a differential amplifier circuit, a differential amplifier circuit, and...
US-9,337,366 Textured optoelectronic devices and associated methods of manufacture
Textured optoelectronic devices and associated methods of manufacture are disclosed herein. In several embodiments, a method of manufacturing a solid state...
US-9,337,333 Transistors with an extension region having strips of differing conductivity type
A transistor includes a gate dielectric over a semiconductor having a first conductivity type, a control gate over the gate dielectric, source and drain regions...
US-9,337,266 Methods and apparatuses including an active area of a tap intersected by a boundary of a well
Apparatuses and methods are disclosed. One such apparatus includes a well having a first type of conductivity formed within a semiconductor structure having a...
US-9,337,237 Methods, structures and devices for increasing memory density
Non-volatile memory devices comprising a memory string including a plurality of vertically superimposed diodes. Each of the diodes may be arranged at different...
US-9,337,210 Vertical ferroelectric field effect transistor constructions, constructions comprising a pair of vertical...
A vertical ferroelectric field effect transistor construction comprises an isolating core. A transition metal dichalcogenide material encircles the isolating...
US-9,337,201 Memory cells, arrays of memory cells, and methods of forming memory cells
A memory cell includes a vertically oriented transistor having an elevationally outer source/drain region, an elevationally inner source/drain region, and a...
US-9,337,162 Multi-component integrated circuit contacts
An integrated circuit connection is describe that includes a first, securing member and a second, connection member. The first member, in an embodiment, is a...
US-9,337,119 Stacked semiconductor die assemblies with high efficiency thermal paths and associated systems
Semiconductor die assemblies having high efficiency thermal paths. In one embodiment, a semiconductor die assembly comprises a package support substrate, a...
US-9,337,064 Methods of protecting peripheries of in-process semiconductor wafers and related in-process wafers and systems
Methods of processing semiconductor wafers may involve, for example, encapsulating an active surface and each side surface of a wafer of semiconductor material,...
US-9,337,053 Method of forming contacts for a memory device
The present invention is generally directed to a method of forming contacts for a memory device. In one illustrative embodiment, the method includes forming a...
US-9,336,875 Memory systems and memory programming methods
Memory systems and memory programming methods are described. In one arrangement, a memory system includes a memory cell configured to have a plurality of...
US-9,336,874 Mixed mode programming for phase change memory
Subject matter disclosed herein relates to a memory device, and more particularly to write performance of a phase change memory.
US-9,336,856 Device and apparatus having address and command input paths
A device includes a plurality of input terminals, a control circuit, and a plurality of signal buses. Each of the signal buses is coupled between the control...
US-9,336,843 Program-disturb decoupling for adjacent wordlines of a memory device
Subject matter disclosed herein relates to memory operations regarding programming bits into a memory array.
US-9,336,837 Low voltage sensing scheme having reduced active power down standby current
A low voltage sensing scheme reduces active power down standby leakage current in a memory device. A clamping device or diode is used between a Psense amplifier...
US-9,336,410 Nonvolatile memory internal signature generation
A nonvolatile memory device generates a signature using a private key and contents within the memory device. The signature is stored in a secure area within the...
US-9,336,086 Apparatuses and methods including error correction code organization
Some embodiments include apparatuses and methods having first memory cells, a first access line configured to access the first memory cells, second memory...
US-9,336,084 Error detection for multi-bit memory
Systems, methods, and devices are disclosed, including a device that includes a plurality of data locations, a quantizing circuit coupled to the plurality of...
US-9,336,083 Apparatus and methods of programming memory cells using adjustable charge state level(s)
Apparatus and methods are disclosed, including a method of programming involving determining an error rate for the memory cells, and programming the memory...
US-9,336,082 Validating persistent memory content for processor main memory
Subject matter disclosed herein relates to validating memory content in persistent main memory of a processor.
US-9,335,372 Apparatus and methods for delay line testing
This disclosure relates to delay line test circuits and methods. In one aspect, an integrated circuit (IC) can include a plurality of delay lines, a selection...
US-D755,657 Mobile electronic emergency responder
US-9,331,989 Secure shared key sharing systems and methods
Systems and methods used to securely communicate a shared key to devices. One embodiment describes a method to securely communicate a shared key to a first...
US-9,331,702 Apparatuses and methods for compensating for power supply sensitivities of a circuit in a clock path
Apparatuses and methods for compensating for differing power supply sensitivities of a circuit in a clock path. One such method includes altering signal timing...
US-9,331,699 Level shifters, memory systems, and level shifting methods
Level shifters, memory systems, and level shifting methods are described. According to one arrangement, a level shifter includes an input configured to receive...
US-9,331,646 Input buffer apparatuses and methods
Apparatuses and methods are disclosed, including an apparatus with a first differential amplifier to amplify an input signal into a first output signal, a...
US-9,331,275 Switching device structures and methods
Switching device structures and methods are described herein. A switching device can include a vertical stack comprising a material formed between a first and a...
US-9,331,269 Spin transfer torque memory cells
Spin transfer torque memory cells and methods of forming the same are described herein. As an example, spin transfer torque memory cells may include an...
US-9,331,252 Wavelength converters, including polarization-enhanced carrier capture converters, for solid state lighting...
Wavelength converters, including polarization-enhanced carrier capture converters, for solid state lighting devices, and associated systems and methods are...
US-9,331,236 Engineered substrates having epitaxial formation structures with enhanced shear strength and associated systems...
Engineered substrates having epitaxial formation structures with enhanced shear strength and associated systems and methods are disclosed herein. In several...
US-9,331,203 Devices with cavity-defined gates and methods of making the same
Disclosed are methods, systems and devices, including a method that includes the acts of forming a semiconductor fin, forming a sacrificial material adjacent...
US-9,331,083 Techniques for providing a semiconductor memory device
Techniques for providing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as an apparatus...
US-9,330,975 Integrated circuit substrates comprising through-substrate vias and methods of forming through-substrate vias
A method of forming a through-substrate via includes forming a through-substrate via opening at least partially through a substrate from one of opposing sides...
US-9,330,934 Methods of forming patterns on substrates
Methods of forming a pattern on a substrate include forming carbon-comprising material over a base material, and spaced first features over the...
US-9,330,932 Methods of fabricating features associated with semiconductor substrates
Some embodiments include a method in which a mixture of polynucleotide structures comprises a set of surface shapes. Surface shapes of some polynucleotide...
US-9,330,914 Methods of forming line patterns in substrates
A method including forming a line pattern in a substrate includes using a plurality of longitudinally spaced projecting features formed along respective guide...
US-9,330,794 DRAM-based anti-fuse cells
Apparatuses and methods for programming and reading from anti-fuse cells are disclosed herein. For example, a semiconductor device may include a plurality of...
US-9,330,789 Short-checking methods
In an embodiment, a short-checking method includes charging a data line to an initial voltage while activating a memory cell coupled to the data line, allowing...
US-9,330,777 Memory program disturb reduction
Some embodiments include a memory device and a method of programming memory cells of the memory device. One such method can include applying, during a first...
US-9,330,756 Apparatuses and methods for sensing using an integration component
The present disclosure includes apparatuses and methods for sensing a resistance variable memory cell. A number of embodiments include circuitry to provide a...
US-9,329,990 Host controlled enablement of automatic background operations in a memory device
A host that is coupled to a memory device is configured to read a status register of the memory device to determine if the memory device supports host...
US-9,329,623 Apparatuses, integrated circuits, and methods for synchronizing data signals with a command signal
Apparatuses, integrated circuits, and methods are disclosed for synchronizing data signals with a command signal. In one such example apparatus, an input...
US-9,329,336 Method of forming a hermetically sealed fiber to chip connection
Disclosed are methods of providing a hermetically sealed optical connection between an optical fiber and an optical element of a chip and a photonic-integrated...
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