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Patent # Description
US-9,966,347 Under-bump metal structures for interconnecting semiconductor dies or packages and associated systems and methods
The present technology is directed to manufacturing semiconductor dies with under-bump metal (UBM) structures for die-to-die and/or package-to-package...
US-9,966,127 Compensating for variations in selector threshold voltages
Methods, systems, and devices are described for operating a memory array. A first voltage may be applied to a memory cell to activate a selection component of...
US-9,966,116 Apparatuses and methods for storing a data value in a sensing circuitry element
The present disclosure includes apparatuses and methods related to storing a data value in a sensing circuitry element. An example method comprises sensing a...
US-9,960,346 Magnetic tunnel junctions
A magnetic tunnel junction has a conductive first magnetic electrode comprising magnetic recording material. A conductive second magnetic electrode is spaced...
US-9,960,258 Methods of forming transistor gates
Some embodiments include methods of forming charge storage transistor gates and standard FET gates in Which common processing is utilized for fabrication of at...
US-9,960,150 Semiconductor device assembly with through-mold cooling channel formed in encapsulant
Semiconductor device assemblies having stacked semiconductor dies and thermal transfer devices that include vapor chambers are disclosed herein. In one...
US-9,960,148 Methods for transferring heat from stacked microfeature devices
Methods and apparatuses for transferring heat from stacked microfeature devices are disclosed herein. In one embodiment, a microfeature device assembly...
US-9,960,114 Structure of integrated circuitry and a method of forming a conductive via
A method of forming a conductive via comprises forming a structure comprising an elevationally-extending-conductive via and a conductive line electrically...
US-9,960,094 Packaged semiconductor components having substantially rigid support members and methods of packaging...
Packaged semiconductor components having substantially rigid support member are disclosed. The packages can include a semiconductor die and a support member...
US-9,959,931 Programming a memory device in response to its program history
A method includes determining, internal to a memory device, a number of program pulses required to program a sample of memory cells of the memory device during...
US-9,959,929 Memory device and method having on-board processing logic for facilitating interface with multiple processors,...
A memory device includes an on-board processing system that facilitates the ability of the memory device to interface with a plurality of processors operating...
US-9,959,923 Apparatuses and methods to reverse data stored in memory
Apparatuses and methods are provided for reversing data stored in memory. An example apparatus comprises an array of memory cells, a first plurality of sensing...
US-9,959,921 Apparatuses and methods for refresh control
Apparatuses and methods of for refresh control of a semiconductor device are described. An example apparatus includes a command control circuit that provides a...
US-9,959,913 Apparatuses and methods for performing logical operations using sensing circuitry
The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an...
US-9,959,732 Method and system for fall detection
The present disclosure provides a method and a system for fall detection. Measurement signals are received from a plurality of sensors to monitor user...
US-9,959,474 Bus translator
Disclosed are methods and devices, among which is a device including a bus translator. In some embodiments, the device also includes a core module and a core...
US-9,959,220 Memory tile access and selection patterns
In one embodiment, an apparatus, such as a memory device, is disclosed. The apparatus includes multiple memory tiles and selection circuitry. Each memory tile...
US-9,958,887 Device having internal voltage generating circuit
A device includes an amplifying circuit having first and second input terminals and an output terminal, a ground terminal, a variable resistance circuit, and a...
US-9,958,624 Apparatus providing simplified alignment of optical fiber in photonic integrated circuits
A structure for optically aligning an optical fiber to a protonic device and method of fabrication of same. The structure optically aligns an optical fiber to...
US-9,954,517 Apparatuses and methods for duty cycle adjustment
Apparatuses, duty cycle adjustment circuits, adjustment circuits, and methods for duty cycle adjustment are disclosed herein. An example duty cycle adjustment...
US-9,954,437 Charge pump
One charge pump includes at least one delay element, a number of inverters, and a flip flop coupled in series, with an output of one inverter coupled in a...
US-9,954,075 Thyristor random access memory device and method
Memory devices and methods of making memory devices are shown. Methods and configurations as shown provide folded and vertical memory devices for increased...
US-9,953,842 Methods of forming a portion of a memory array having a conductor having a variable concentration of germanium
An embodiment of a method of forming a portion of a memory array includes forming a conductor with a concentration of germanium that decreases with an...
US-9,953,724 Memory devices and methods for managing error regions
Memory devices and methods are described that include a stack of memory dies and a logic die. Method and devices described include those that provide for...
US-9,953,718 Programming memory cells to be programmed to different levels to an intermediate level from a lowest level
First memory cells are programmed to an intermediate level from a lowest level, corresponding to a lowest data state, where the first memory cells are to be...
US-9,953,711 Methods of operating memory under erase conditions
Methods of operating a memory include applying a first voltage level to a first semiconductor material of a first conductivity type forming a channel region for...
US-9,953,710 Memory devices with a connecting region having a band gap lower than a band gap of a body region
Memory devices are shown that include a body region and a connecting region that is formed from a semiconductor with a lower band gap than the body region....
US-9,952,925 Error code calculation on sensing circuitry
Examples of the present disclosure provide apparatuses and methods for error code calculation. The apparatus can include an array of memory cells that are...
US-9,952,077 Self-aligning brace bar
A brace bar, a flow conduit assembly including a brace bar, and a method for assembling a vibrating flowmeter including a brace bar are provided. The brace bar...
US-9,950,464 Forming a carbon nano-tube dispersion
Various embodiments disclose a molding compound comprising a resin, a filler, and a carbon nano-tube dispersion and methods of forming a package using the...
US-9,948,300 Apparatuses and methods for partial bit de-emphasis
Apparatuses and methods for partial bit de-emphasis are provided. An example apparatus includes an output driver and control circuit. The output driver includes...
US-9,947,721 Thermal insulation for three-dimensional memory arrays
Methods, systems, and devices for a three-dimensional memory array are described. Memory cells may transform when exposed to elevated temperatures, including...
US-9,947,720 Three-dimensional memory apparatuses and methods of use
A three dimensional (3D) memory array may include a plurality of memory cells. An example 3D memory array may include an electrode plane and a memory material...
US-9,947,719 Memory including a selector switch on a variable resistance memory cell
Embodiments include but are not limited to apparatuses and systems including memory having a memory cell including a variable resistance memory layer, and a...
US-9,947,687 Memory cells comprising a programmable field effect transistor having a reversibly programmable gate insulator
A memory cell comprises an elevationally extending programmable field effect transistor comprising a gate insulator that is reversibly programmable into two...
US-9,947,666 Semiconductor device structures including buried digit lines and related methods
Methods of forming semiconductor device structures include forming trenches in an array region and in a buried digit line end region, forming a metal material...
US-9,947,418 Boosted channel programming of memory
Methods of operating a memory include generating a programming pulse for a programming operation having a plurality of steps prior to a program voltage level of...
US-9,947,376 Vertical bit vector shift in memory
Examples of the present disclosure provide apparatuses and methods for vertical bit vector shift in a memory. An example method comprises storing a vertical bit...
US-9,947,375 Methods and apparatuses for providing a program voltage responsive to a voltage determination
Apparatuses and methods for providing a program voltage responsive to a voltage determination are described. An example apparatus includes a memory array...
US-9,946,612 Data encoding using spare channels
Implementations of encoding techniques are disclosed. In one embodiment, an encoding system includes a codec device, a switching network, a rerouting circuit, a...
US-9,942,074 Wireless devices and systems including examples of mixing coefficient data specific to a processing mode selection
Examples described herein include systems and methods which include wireless devices and systems with examples of mixing input data with coefficient data...
US-9,941,870 Adjustable delay circuit for optimizing timing margin
The present invention relates to timing margin adjustment circuits using adjustable delay circuits. An example adjustable delay circuit may include a signal...
US-9,941,466 Magnetic tunnel junctions, methods used while forming magnetic tunnel junctions, and methods of forming...
A method used while forming a magnetic tunnel junction comprises forming non-magnetic tunnel insulator material over magnetic electrode material. The tunnel...
US-9,941,298 Methods of forming integrated structures comprising vertical channel material and having conductively-doped...
Some embodiments include an integrated structure having vertically-stacked conductive levels. Upper conductive levels are memory cell levels, and a lower...
US-9,941,238 Wiring with external terminal
Apparatuses for providing external terminals of a semiconductor device are described. An example apparatus includes: a connection wiring of a ring-shape having...
US-9,941,155 Methods for isolating portions of a loop of pitch-multiplied material and related structures
Different portions of a continuous loop of semiconductor material are electrically isolated from one another. In some embodiments, the end of the loop is...
US-9,941,053 Structure and methods of forming the structure
Capacitors, apparatus including a capacitor, and methods for forming a capacitor are provided. One such capacitor may include a first conductor a second...
US-9,941,022 Setting a default read signal based on error correction
A number of methods can include reading a page of data from a group of memory cells with a first discrete read signal and error correcting at least one codeword...
US-9,941,021 Plate defect mitigation techniques
Methods, systems, techniques, and devices for operating a ferroelectric memory cell or cells are described. Groups of cells may be operated in different ways...
US-9,940,990 Data shift apparatuses and methods
The present disclosure includes data shift apparatuses and methods. An example apparatus includes a memory device. The example memory device includes an array...
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