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Patent # Description
US-D752,762 External transmit modulator for an implantable neural stimulator
US-D752,761 External transit modulator for implantable neural stimulator
US-9,294,105 Delay line off-state control with power reduction
A method and apparatus is provided for controlling a delay line for achieving power reduction. The device comprises a delay lock loop to provide an output...
US-9,294,095 Apparatuses and methods for input buffer having combined output
Apparatuses and methods are disclosed, including an apparatus that includes a first differential amplifier to amplify a difference between an input signal and a...
US-9,294,072 Semiconductor device and method for adjusting impedance of output circuit
An impedance adjustment circuit includes a counter circuit outputting a count value thereof as a plurality of first impedance adjustment signals, a mode...
US-9,293,678 Solid-state light emitters having substrates with thermal and electrical conductivity enhancements and method...
Solid-state lighting devices (SSLDs) including a carrier substrate with conductors and methods of manufacturing SSLDs. The conductors can provide (a) improved...
US-9,293,639 Vertical solid-state transducers and high voltage solid-state transducers having buried contacts and associated...
Solid-state transducers ("SSTs") and vertical high voltage SSTs having buried contacts are disclosed herein. An SST die in accordance with a particular...
US-9,293,638 Self-identifying solid-state transducer modules and associated systems and methods
Self-identifying solid-state transducer (SST) modules and associated systems and methods are disclosed herein. In several embodiments, for example, an SST...
US-9,293,367 Conductive interconnect structures and formation methods using supercritical fluids
Conductive interconnect structures and formation methods using supercritical fluids are disclosed. A method in accordance with one embodiment of the invention...
US-9,293,342 Patterned bases, and patterning methods
Some embodiments include methods of patterning a base. First and second masking features are formed over the base. The first and second masking features include...
US-9,293,328 Semiconductor device structures comprising a polymer bonded to a base material and methods of fabrication
Methods for adhering materials and methods for enhancing adhesion between materials are disclosed. In some embodiments, a polymer brush material is bonded to a...
US-9,293,319 Removal of metal
Methods of removing metal from a portion of a substrate are useful in integrated circuit fabrication. Methods include exposing the substrate to an oxidizing...
US-9,293,214 Determining and using soft data in memory devices and systems
The present disclosure includes methods, devices, and systems for determining and using soft data in memory devices and systems. One or more embodiments include...
US-9,293,213 Sensing data stored in memory
The present disclosure includes apparatuses and methods for sensing data stored in memory. A number of embodiments include an array of memory cells, and a...
US-9,293,196 Memory cells, memory systems, and memory programming methods
Memory cells, memory systems and methods are described. In one embodiment, a memory cell includes electrodes and a memory element, and a first electrically...
US-9,293,191 Apparatuses and methods for multi-memory array accesses
Methods and apparatuses are disclosed for multi-memory array access. One example apparatus includes a pair of input/output lines, and a first array coupled to...
US-9,293,185 Apparatus including a capacitor-less memory cell and related methods
A capacitor-less memory cell, memory device, system and process of forming the capacitor-less memory cell include forming the capacitor-less memory cell in an...
US-9,293,176 Power management
Methods, and apparatus configured to perform such methods, providing peak power management are useful in mitigating excessive current levels within a multi-die...
US-9,293,170 Configurable bandwidth memory devices and methods
Memory devices and methods are described, such as those that include a stack of memory dies and an attached logic die. Method and devices described provide for...
US-9,292,383 Multilevel encoding with error correction
Embodiments of the present disclosure provide methods, systems, and apparatuses related to multilevel encoding with error correction. In some embodiments, a...
US-9,292,382 Codewords that span pages of memory
The present disclosure includes apparatuses and methods for codewords that span pages of memory. A number of methods include writing a first portion of a...
US-9,291,907 Methods for forming resist features and arrays of aligned, elongate resist features
Methods of forming resist features, resist patterns, and arrays of aligned, elongate resist features are disclosed. The methods include addition of a compound,...
US-9,290,857 Methods and apparatus for sorting and/or depositing nanotubes
Methods and apparatus for forming devices using nanotubes. In one embodiment, an apparatus for depositing nanotubes onto a workpiece comprises a vessel...
US-9,287,859 Flexible input/output transceiver
An I/O transceiver includes a driver with a feedback circuit having a mode select signal input, a serial data signal input, and a driver output signal input....
US-9,287,502 Resistance variable memory cell structures and methods
Resistance variable memory cell structures and methods are described herein. One or more resistance variable memory cell structures include a first electrode...
US-9,287,500 Memory cells and methods of forming memory cells
Some embodiments include a memory cell having an electrode and a switching material over the electrode. The electrode is a first composition which includes a...
US-9,287,452 Solid state lighting devices with dielectric insulation and methods of manufacturing
Solid state lighting devices and associated methods of manufacturing are disclosed herein. In one embodiment, a solid state lighting device includes a first...
US-9,287,379 Memory arrays
Some embodiments include a memory array which has a stack of alternating first and second levels. Channel material pillars extend through the stack, and...
US-9,287,284 Semiconductor field-effect transistor, memory cell and memory device
Semiconductor device formed by a first conductive strip of semiconductor material; a control gate region of semiconductor material, facing a channel portion of...
US-9,287,275 Semiconductor constructions
Some embodiments include methods of forming flash memory cells and semiconductor constructions, and some embodiments include semiconductor constructions. Some...
US-9,287,271 Vertical transistor devices, memory arrays, and methods of forming vertical transistor devices
A vertical transistor device includes a line of active area adjacent a line of dielectric isolation. A buried data/sense line obliquely angles relative to the...
US-9,287,260 Transistors having one or more dummy lines with different collective widths coupled thereto
In an embodiment, an array of transistors has a first line coupled to a first transistor. The first line extends over a second transistor that is successively...
US-9,287,240 Stacked semiconductor die assemblies with thermal spacers and associated systems and methods
Stacked semiconductor die assemblies with thermal spacers and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die...
US-9,287,207 Methods for forming conductive vias in semiconductor device components
A method for forming conductive vias in a substrate of a semiconductor device component includes forming one or more holes, or apertures or cavities, in the...
US-9,287,184 Apparatuses and methods for die seal crack detection
Apparatuses and methods can include a die seal between an integrated circuit region of a die and a periphery of the die. A via chain(s) may be arranged around...
US-9,286,977 Semiconductor device
A semiconductor device including: a resistive memory element; a data line electrically coupled to the resistive memory element; a control line; a power supply...
US-9,286,161 Memory system and method using partial ECC to achieve low power refresh and fast access to data
A DRAM memory device includes several banks of memory cells each of which are divided into first and second sets of memory cells. The memory cells in the first...
US-9,281,682 Apparatuses and method for over-voltage event protection
Circuits, integrated circuits, apparatuses, and methods, such as those for protecting circuits against electrostatic discharge events are disclosed. An example...
US-9,281,478 Phase change memory cell with constriction structure
Some embodiments include methods of forming memory cells. Such methods can include forming a first electrode, a second electrode, and a memory element directly...
US-9,281,471 Phase change memory stack with treated sidewalls
Memory devices and methods for fabricating memory devices have been disclosed. One such memory device includes a first electrode material formed on a word line...
US-9,281,466 Memory cells, semiconductor structures, semiconductor devices, and methods of fabrication
A magnetic cell includes a magnetic region formed from a precursor magnetic material comprising a diffusive species and at least one other species. An amorphous...
US-9,281,402 Methods of fabricating fin structures
There is provided fin methods for fabricating fin structures. More specifically, fin structures are formed in a substrate. The fin structures may include two...
US-9,281,309 Cross-hair cell wordline formation
Methods and devices depicting fabrication of non-planar access devices having fins and narrow trenches, among which is a method that includes wet etching a...
US-9,281,241 Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces formed using...
Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces formed using such methods are disclosed herein. One embodiment,...
US-9,281,078 Program operations with embedded leak checks
Methods of operating a memory device having embedded leak checks may mitigate data loss events due to access line defects, and may facilitate improved power...
US-9,281,073 Methods of operating a memory device having a buried boosting plate
Memory devices are disclosed, such as those that include a semiconductor-on-insulator (SOI) NAND memory array having a boosting plate. The boosting plate may be...
US-9,281,066 Dynamically configurable MLC state assignment
Memory devices facilitating a data conditioning scheme for multilevel memory cells. For example, one such memory device is capable of inverting the lower page...
US-9,281,064 Fast programming memory device
In an embodiment of a memory device including a matrix of memory cells wherein the memory cells are arranged in a plurality of memory cells strings each one...
US-9,281,062 Systems, and devices, and methods for programming a resistive memory cell
Embodiments disclosed herein may relate to programming a memory cell with a programming pulse that comprises a quenching period having different portions.
US-9,281,061 Methods and apparatuses having a voltage generator with an adjustable voltage drop for representing a voltage...
Apparatus and methods utilize a replica circuit to generate a voltage for programming of a memory cell, such as a memory cell of a phase-change memory (PCM)....
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