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Patent # Description
US-9,378,157 Security memory access method and apparatus
Various embodiments comprise apparatuses and methods to allow access to a memory device by an external device. A method includes receiving, at the memory...
US-9,374,902 Package including an underfill material in a portion of an area between the package and a substrate or another...
Embodiments include but are not limited to apparatuses and systems including semiconductor packages, e.g. memory packages, having a substrate or a first...
US-9,374,343 Bitwise operations and apparatus in a multi-level system
A system uses multi-level encoding where each symbol of a plurality of symbols represents more than one bit of information in a user data symbol stream for...
US-9,373,779 Magnetic tunnel junctions
A magnetic tunnel junction includes a conductive first magnetic electrode that includes magnetic recording material. A conductive second magnetic electrode is...
US-9,373,775 Methods of forming magnetic memory cells
Methods of forming memory cells, magnetic memory cell structures, and arrays of magnetic memory cell structures are disclosed. Embodiments of the methods...
US-9,373,716 Impact ionization devices, and methods of forming impact ionization devices
Impact ionization devices including vertical and recessed impact ionization metal oxide semiconductor field effect transistor (MOSFET) devices and methods of...
US-9,373,715 Semiconductor devices including vertical memory cells and methods of forming same
A semiconductor device may include a memory array including vertical memory cells connected to a digit line, word lines, and a body connection line. A row or...
US-9,373,661 Solid state transducer devices, including devices having integrated electrostatic discharge protection, and...
Solid state transducer devices having integrated electrostatic discharge protection and associated systems and methods are disclosed herein. In one embodiment,...
US-9,373,636 Methods of forming semiconductor constructions
Some embodiments include a semiconductor construction having a stack containing alternating levels of control gate material and intervening dielectric material....
US-9,373,404 Sensing memory cells coupled to different access lines in different blocks of memory cells
In an embodiment, a target memory cell in a first block of memory cells of a memory device and a target memory cell in a second block of memory cells of the...
US-9,373,399 Resistance variable element methods and apparatuses
Apparatus and methods are disclosed, including a method that performs a first operation on a first resistance variable element using a common source voltage, a...
US-9,373,392 Memory cells with rectifying device
Memory devices and methods described are shown that provide improvements, including improved cell isolation for operations such as read and write. Further,...
US-9,373,377 Apparatuses, integrated circuits, and methods for testmode security systems
Apparatuses, integrated circuits, and methods are disclosed for testmode security systems. In one such example apparatus, a data storage is configured to store...
US-9,373,371 Dynamic burst length output control in a memory
A memory, a system and a method for controlling dynamic burst length control data can generate clocks for both an upstream counter and a downstream counter by...
US-D759,727 Electric high pressure decompressor
US-9,368,714 Memory cells, methods of operation and fabrication, semiconductor device structures, and memory systems
A magnetic cell core includes at least one stressor structure proximate to a magnetic region (e.g., a free region or a fixed region). The magnetic region may be...
US-9,368,669 Method and apparatus for reducing signal loss in a photo detector
Photonic structures and methods of formation are disclosed in which a photo detector interface having crystalline misfit dislocations is displaced with respect...
US-9,368,581 Integrated circuitry components, switches, and memory cells
A switch includes a graphene structure extending longitudinally between a pair of electrodes and being conductively connected to both electrodes of said pair....
US-9,368,554 Apparatuses and methods including memory access in cross point memory
Some embodiments include apparatuses and methods having a memory cell, first and second conductive lines configured to access the memory cell, and a switch...
US-9,368,444 Self-aligned nano-structures
A method for creating structures in a semiconductor assembly is provided. The method includes etching apertures into a dielectric layer and applying a polymer...
US-9,368,216 Interconnections for 3D memory
Apparatuses and methods for interconnections for 3D memory are provided. One example apparatus can include a stack of materials including a plurality of pairs...
US-9,368,212 Memory with temperature coefficient trimming
A device includes an array of memory cells, a temperature sensor to provide a temperature output, and a circuit. The circuit provides a bias voltage to bias a...
US-9,368,202 Apparatuses, sense circuits, and methods for compensating for a wordline voltage increase
Apparatuses, sense circuits, and methods for compensating for a voltage increase on a wordline in a memory is described. An example apparatus includes a...
US-9,368,185 Semiconductor device
A semiconductor device includes a plurality of memory cells, an access circuit configured to perform a data read operation, a data write operation and a data...
US-9,368,184 Memory refresh methods, memory section control circuits, and apparatuses
Apparatuses, memory section control circuits, and methods of refreshing memory are disclosed. An example apparatus includes a plurality of memory sections and a...
US-9,368,163 Power consumption control
The present disclosure includes apparatuses and methods for power consumption control. A number of embodiments include determining power consumption information...
US-9,367,391 Error correction operations in a memory device
Memory devices configured to determine if an error exists in read data and to respond to determined errors, as well as methods of operating such memory devices....
US-9,362,911 Apparatus and methods for leakage current reduction in integrated circuits
This disclosure relates to leakage current reduction in integrated circuits (ICs). In one aspect, an IC can include a digital logic circuit and a polarization...
US-9,362,908 Semiconductor apparatus including output buffer
An output circuit includes first, second and third transistors. The first transistor includes first and second diffusion layers. The third transistor includes...
US-9,362,495 Confined resistance variable memory cells and methods
Methods, devices, and systems associated with resistance variable memory device structures can include a method of forming a confined resistance variable memory...
US-9,362,494 Array of cross point memory cells and methods of forming an array of cross point memory cells
An array of cross point memory cells comprises spaced elevationally inner first lines, spaced elevationally outer second lines which cross the first lines, and...
US-9,362,418 Semiconductor structures including bodies of semiconductor material and methods of forming same
Semiconductor structures that include bodies of a semiconductor material spaced apart from an underlying substrate. The bodies may be physically separated from...
US-9,362,300 Apparatuses and methods for forming multiple decks of memory cells
Some embodiments include apparatuses and methods having multiple decks of memory cells and associated control gates. A method includes forming a first deck...
US-9,362,260 Stacked packaged integrated circuit devices, and methods of making same
A device is disclosed which includes a first packaged integrated circuit device, a second packaged integrated circuit device positioned above the first packaged...
US-9,362,259 Discontinuous patterned bonds for semiconductor devices and associated systems and methods
Discontinuous bonds for semiconductor devices are disclosed herein. A device in accordance with a particular embodiment includes a first substrate and a second...
US-9,362,208 Packaged semiconductor components having substantially rigid support members and methods of packaging...
Packaged semiconductor components having substantially rigid support member are disclosed. The packages can include a semiconductor die and a support member...
US-9,362,194 Semiconductor chip covered with sealing resin having a filler material
A semiconductor device includes a wiring substrate, a sealing resin layer formed on the wiring substrate out of a filler-containing resin and having a one-sided...
US-9,362,143 Methods for forming semiconductor device packages with photoimageable dielectric adhesive material, and related...
Methods for forming semiconductor device packages include applying a photoimageable dielectric adhesive material to a major surface of a semiconductor die and...
US-9,362,141 Microelectronic devices, stacked microelectronic devices, and methods for manufacturing such devices
Stacked microelectronic devices and methods for manufacturing such devices are disclosed herein. In one embodiment, a stacked microelectronic device assembly...
US-9,361,996 Inferring threshold voltage distributions associated with memory cells via interpolation
Apparatuses and methods for inferring threshold voltage distributions associated with memory cells via interpolation are described herein. An example includes...
US-9,361,981 Methods of forming and programming memory devices with isolation structures
Methods of programming and forming memory devices. Methods of programming include biasing a control gate of a selected memory cell of the memory device to a...
US-9,361,979 Apparatuses including cross point memory arrays and biasing schemes
Memory devices comprise a plurality of memory cells, each memory cell including a memory element and a selection device. A plurality of first (e.g., row)...
US-9,361,966 Thyristors
Some embodiments include thyristors having first and second electrode regions, first and second base regions, and material having a bandgap of at least 1.2 eV...
US-9,361,181 Error protection for memory devices
Subject matter disclosed herein relates to methods and/or apparatuses, such as an apparatus that includes first and second groups of memory cells. The first...
US-9,360,627 Method and apparatus providing compensation for wavelength drift in photonic structures
A method and apparatus are described which provide for wavelength drift compensation in a photonic waveguide by application of an electric field to a waveguide...
US-9,358,753 Substrates and methods of forming a pattern on a substrate
Substrates and methods of forming a pattern on a substrate. The pattern includes a repeating pattern region and a pattern-interrupting region adjacent to the...
US-D758,596 Flexible circuit for an implantable neural stimulator
US-9,356,237 Forming resistive random access memories together with fuse arrays
A resistive random access memory array may be formed on the same substrate with a fuse array. The random access memory and the fuse array may use the same...
US-9,356,229 Memory cells and methods of fabrication
Memory cells are disclosed. Magnetic regions within the memory cells include an alternating structure of magnetic sub-regions and coupler sub-regions. The...
US-9,356,157 Semiconductor devices comprising floating gate transistors and methods of forming such semiconductor devices
Semiconductor devices include one or more transistors having a floating gate and a control gate. In at least one embodiment, the floating gate comprises an...
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