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Patent # Description
US-9,269,695 Semiconductor device assemblies including face-to-face semiconductor dice and related methods
Methods of manufacturing semiconductor device assemblies include attaching a back side of a first semiconductor die to a substrate and structurally and...
US-9,269,646 Semiconductor die assemblies with enhanced thermal management and semiconductor devices including same
A semiconductor die assembly comprises a plurality of semiconductor dice in a stack. Another semiconductor die is adjacent to the stack and has a region, which...
US-9,269,586 Selective metal deposition over dielectric layers
Selective deposition of metal over dielectric layers in a manner that minimizes or eliminates keyhole formation is provided. According to one embodiment, a...
US-9,269,452 Determining system lifetime characteristics
Methods and systems for determining system lifetime characteristics are described. A number of embodiments include a number of memory devices and a controller...
US-9,269,450 Methods, devices, and systems for adjusting sensing voltages in devices
The present disclosure includes methods, devices, and systems for adjusting sensing voltages in devices. One or more embodiments include memory cells, and a...
US-9,269,432 Memory systems and memory programming methods
Memory systems and memory programming methods are described. According to one arrangement, a memory system includes a memory array comprising a plurality of...
US-9,269,431 Configurable reference current generation for non volatile memory
This disclosure relates to generating a reference current for a memory device. In one aspect, a non-volatile memory device, such as a phase change memory...
US-9,269,410 Leakage measurement systems
Described examples include leakage measurement systems and methods for measuring leakage current between a word line at a boosted voltage and a word line at a...
US-9,269,403 Independent control of stacked electronic modules
Various embodiments of apparatuses are disclosed to allow independent control of stacked modules. In one embodiment, an apparatus may include a plurality of...
US-9,268,690 Circuits and methods for providing data to and from arrays of memory cells
A memory device uses a global input/output line or a pair of complementary global input/output lines to couple write data signals and read data signals to and...
US-9,268,629 Dual mapping between program states and data patterns
The present disclosure includes methods and apparatuses for dual mapping between program states and data patterns. One apparatus includes a memory and a...
US-9,268,210 Double-exposure mask structure and photolithography method thereof
Double-exposure mask structure and photolithography method for performing a photolithography process on a substrate are provided. The substrate has a central...
US-9,267,980 Capacitance evaluation apparatuses and methods
Apparatus and methods for evaluating leakage currents of capacitances are described. Capacitances having excessive leakage currents may be disabled from use. An...
US-9,264,068 Deflate compression algorithm
A compression algorithm replaces duplicative strings with a copy pair indicating a location and length of a preceding identical string that is within a window...
US-9,264,050 Apparatuses and methods for delaying signals using a delay line with homogenous architecture and integrated...
Apparatuses and methods for delaying signals using a delay line are described. An example apparatus includes a controller configured to in a first mode, set a...
US-9,263,675 Switching components and memory units
Some embodiments include a switching component which includes a selector region between a pair of electrodes. The selector region contains silicon doped with...
US-9,263,674 ETCH bias homogenization
Methods and memory devices formed using etch bias homogenization are provided. One example method of forming a memory device using etch bias homogenization...
US-9,263,672 Transistors, memory cells and semiconductor constructions
Some embodiments include a semiconductor construction having a gate extending into a semiconductor base. Conductively-doped source and drain regions are within...
US-9,263,577 Ferroelectric field effect transistors, pluralities of ferroelectric field effect transistors arrayed in row...
A ferroelectric field effect transistor comprises a semiconductive channel comprising opposing sidewalls and an elevationally outermost top. A source/drain...
US-9,263,461 Apparatuses including memory arrays with source contacts adjacent edges of sources
Various apparatuses, including three-dimensional (3D) memory devices and systems including the same, are described herein. In one embodiment, a 3D memory device...
US-9,263,460 Methods and apparatuses including a select transistor having a body region including monocrystalline...
Some embodiments include apparatuses and methods having a memory cell string including memory cells located in different levels of the apparatuses and a select...
US-9,263,455 Methods of forming an array of conductive lines and methods of forming an array of recessed access gate lines
An array of recessed access gate lines includes active area regions having dielectric trench isolation material there-between. The trench isolation material...
US-9,263,341 Methods of forming transistors
Some embodiments include methods of forming transistors. Recesses are formed to extend into semiconductor material. The recesses have upper regions lined with...
US-9,263,133 Techniques for providing a semiconductor memory device
Techniques for providing a semiconductor memory device are disclosed. In one particular embodiment, the techniques may be realized as a semiconductor memory...
US-9,263,130 Memory device page buffer configuration and methods
Memory devices and methods are described that include communication circuitry between page buffers in a memory array. Examples include communication circuitry...
US-9,263,128 Methods and apparatuses for programming memory cells
Methods and apparatus for programming memory cells in a memory array are disclosed. A most recent programming time is determined, the most recent programming...
US-9,263,115 Semiconductor device
A method includes measuring a first pulse width of a resistance variable memory cell coupled between a first terminal and a second terminal, the first pulse...
US-9,263,111 Sub-block disabling in 3D memory
Some embodiments relate to apparatuses and methods associated with blocks of memory cells. The blocks of memory cells may include two or more sub-blocks of...
US-9,263,104 Semiconductor device
Disclosed herein is an apparatus that includes: a first terminal configured to receive a serial write data signal that includes at least four bits transferred...
US-9,263,095 Memory having buried digit lines and methods of making the same
A memory array having memory cells and methods of forming the same. The memory array may have a buried digit line formed in a first horizontal planar volume, a...
US-9,262,335 Re-building mapping information for memory devices
Memory modules and methods of operating memory modules re-build mapping information from data read from last valid physical pages. Corruption of mapping...
US-9,262,317 Non-volatile configuration for serial non-volatile memory
Example embodiments for configuring a serial non-volatile memory device may comprise a non-volatile configuration register to store a configuration value...
US-9,262,261 Memory devices facilitating differing depths of error detection and/or error correction coverage
Memory devices facilitating differing depths of error detection and/or error correction coverage for differing portions of a memory array.
US-9,259,683 Methods and apparatus for treating fluorinated greenhouse gases in gas streams
A method for removing fluorinated greenhouse gas from a gas stream comprises reacting at least one fluorinated greenhouse gas in a gas stream with at least one...
US-9,257,995 Apparatuses and methods for mitigating uneven circuit degradation of delay circuits
Apparatuses and methods for mitigating uneven circuit degradation of delay circuits are disclosed. In an example method, an imbalance in transistor threshold...
US-9,257,648 Memory cells, methods of forming memory cells, and methods of programming memory cells
Some embodiments include methods in which a memory cell is formed to have programmable material between first and second access lines, with the programmable...
US-9,257,646 Methods of forming memory cells having regions containing one or both of carbon and boron
Some embodiments include a memory cell having a first electrode, and an intermediate material over and directly against the first electrode. The intermediate...
US-9,257,431 Memory cell with independently-sized electrode
Memory cell architectures and methods of forming the same are provided. An example memory cell can include a switch element and a memory element. A middle...
US-9,257,430 Semiconductor construction forming methods
Memory device constructions include a first column line extending parallel to a second column line, the first column line being above the second column line; a...
US-9,257,294 Methods and apparatuses for energetic neutral flux generation for processing a substrate
Apparatuses and methods for processing substrates are disclosed. A processing apparatus includes a chamber for generating a plasma therein, an electrode...
US-9,257,256 Templates including self-assembled block copolymer films
Methods for fabricating sublithographic, nanoscale microstructures arrays including openings and linear microchannels utilizing self-assembling block...
US-9,257,203 Setting a default read signal based on error correction
Apparatuses and methods related to setting a default read signal based on error correction include reading a page of data from a group of memory cells with a...
US-9,257,197 Apparatuses and/or methods for operating a memory cell as an anti-fuse
Embodiments disclosed herein relate to operating a memory cell as an anti-fuse, such as for use in phase change memory, for example.
US-9,257,182 Memory devices and their operation having trim registers associated with access operation commands
Methods, and apparatus configured to perform methods, including loading trim settings into a trim register of a memory device associated with a command for an...
US-9,257,180 Random telegraph signal noise reduction scheme for semiconductor memories
Embodiments are provided that include a method including providing a first pulsed gate signal to a selected memory cell, wherein the pulsed gate signal...
US-9,257,155 Integrated circuit having voltage generation circuitry for memory cell array, and method of operating and/or...
A method of generating a voltage as well as an integrated circuit device (e.g., a logic device or a memory device) having a memory cell array which includes (i)...
US-9,257,154 Methods and apparatuses for compensating for source voltage
Apparatuses and methods for compensating for source voltage is described. An example apparatus includes a source coupled to a memory cell and a read-write...
US-9,257,136 Magnetic tunnel junctions
A magnetic tunnel junction comprises a conductive first magnetic electrode comprising magnetic recording material. A conductive second magnetic electrode is...
US-9,256,577 Apparatuses and related methods for overflow detection and clamping with parallel operand processing
A method and apparatus for overflow detection and clamping with parallel operand processing for fixed-point multipliers is disclosed. The disclosure predicts...
US-9,255,964 Electronic apparatus having IC temperature control
The use of a power sink function in IC testing results in a simple and rapid method for testing ICs, and assembled modules, at elevated temperature profiles...
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