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Patent # Description
US-7,095,115 Circuit substrates, semiconductor packages, and ball grid arrays
In one implementation, a circuit substrate includes a substrate having opposing sides. At least one of the sides is configured for transfer mold packaging and...
US-7,095,106 Collars, support structures, and forms for protruding conductive structures
Collars, support structures, or forms for protruding conductive structures include apertures or receptacles through which the conductive structure may extend....
US-7,095,097 Integrated circuit device having reduced bow and method for making same
An integrated circuit device includes a semiconductor component coupled with a lead frame, and an integrated circuit package encompassing at least a portion of...
US-7,095,095 Semiconductor constructions
The invention includes a semiconductor construction. The construction has a semiconductor material die with a front surface, a back surface in opposing relation...
US-7,095,088 System and device including a barrier layer
Systems and devices are disclosed utilizing a silicon-containing barrier layer. A semiconductor device is disclosed and includes a substrate, a gate oxide, a...
US-7,095,083 Methods for making semiconductor structures having high-speed areas and high-density areas
Methods for making a semiconductor structure are discussed. The methods include forming openings in a high-density area and a high-speed area, and forming a...
US-7,095,075 Apparatus and method for split transistor memory having improved endurance
The present invention includes floating gate transistor structures used in non-volatile memory devices such as flash memory devices. In one embodiment, a system...
US-7,094,700 Plasma etching methods and methods of forming memory devices comprising a chalcogenide comprising layer...
In one implementation, a plasma etching method comprises forming a Ge.sub.xSe.sub.y chalcogenide comprising layer over a substrate. A mask comprising an organic...
US-7,094,699 Etch aided by electrically shorting upper and lower sidewall portions during the formation of a semiconductor...
A method used to fabricate a semiconductor device comprises etching a dielectric which results in an undesirable charge buildup along a sidewall formed in the...
US-7,094,695 Apparatus and method for conditioning a polishing pad used for mechanical and/or chemical-mechanical planarization
Conditioning apparatuses and methods for conditioning polishing pads used for mechanical and/or chemical-mechanical planarization of micro-device workpieces are...
US-7,094,690 Deposition methods and apparatuses providing surface activation
A deposition method includes, at a first temperature, contacting a substrate with a surface activation agent and adsorbing a first layer over the substrate. At a...
US-7,094,682 Coating of copper and silver air bridge structures to improve electromigration resistance and other applications
An improved electrical interconnect for an integrated circuit and methods for providing the same are disclosed. The electrical interconnect includes an air...
US-7,094,673 Etch stop layer in poly-metal structures
In accordance with one embodiment of the present invention, a method of forming an etch stop layer in a semiconductor structure is provided. A polysilicon layer...
US-7,094,657 Method for protecting against oxidation of a conductive layer in said device
In a semiconductor device including a first conductive layer, the first conductive layer is treated with a nitrogen/hydrogen plasma before an additional layer is...
US-7,094,636 Method of forming a conductive line
A method of forming a conductive line includes forming conductive material received over a semiconductor substrate into a line having opposing sidewalls....
US-7,094,631 Methods for designing bond pad rerouting elements for use in stacked semiconductor device assemblies and for...
A rerouting element for a semiconductor device that includes a dielectric film that carries conductive vias, conductive elements, and contact pads. The...
US-7,094,628 Underfill compounds including electrically charged filler elements, microelectronic devices having underfill...
Underfill compounds including electrically charged filler elements, microelectronic devices having underfill compounds including electrically charged filler...
US-7,094,618 Methods for marking a packaged semiconductor die including applying tape and subsequently marking the tape
The present invention provides a method and apparatus for marking a semiconductor wafer or device. The method and apparatus have particular application to wafers...
US-7,094,131 Microelectronic substrate having conductive material with blunt cornered apertures, and associated methods for...
A microelectronic substrate and method for removing conductive material from a microelectronic substrate. In one embodiment, the microelectronic substrate...
US-7,094,117 Electrical contacts with dielectric cores
An electrical contact for use with a semiconductor device, a carrier, a probe card, or another substrate includes a dielectric core and a conductive coating on...
US-7,094,108 Apparatus for forming modular sockets using flexible interconnects and resulting structures
A modular bare die socket assembly is provided for attaching a plurality of miniature semiconductor dice to a substrate. The socket assembly is comprised of a...
US-7,094,065 Device for establishing non-permanent electrical connection between an integrated circuit device lead element...
A spring contact for establishing electrical contact between a lead element of an IC device and a substrate. The spring contact generally comprises a contact...
US-7,094,046 Mold assembly for a package stack via bottom-leaded plastic (BLP) packaging
A packaged semiconductor device has bottom surface leads having portions of the package adjacent the lead edges excised. The outer leads may take the form of...
US-7,093,704 Printed circuit board support
A printed circuit board conveying system is provided comprising a printed circuit board conveyor and a printed circuit board support. The printed circuit board...
US-7,093,622 Apparatus for deforming resilient contact structures on semiconductor components
A method for testing and burning-in semiconductor components such as semiconductor dice on a semiconductor wafer, is provided. The method includes the step of...
US-7,093,559 Method for PECVD deposition of selected material films
A process for PECVD of selected material films on a substrate comprising the steps of placing a substrate in a PECVD chamber and maintaining the chamber under...
US-7,093,358 Method for fabricating an interposer
An interposer including a fence that receives and aligns a semiconductor device, such as a flip-chip type semiconductor device, with an interposer substrate. The...
US-7,093,227 Methods of forming patterned reticles
The invention includes methods of forming patterned reticles. Design features can be introduced into a layout for a reticle prior to optical proximity...
US-7,093,173 Synchronous flash memory with test code input
A synchronous non-volatile memory device has address input connections and data input/output connections. A test operation can be initiated that use signals...
US-7,093,098 Multi-drive virtual mass storage device and method of operating same
A virtual mass storage device implements a data manager for storing information on multiple physical mass storage devices. The virtual mass storage device is...
US-7,093,095 Double data rate scheme for data output
Systems, devices, and methods for a double data rate memory device includes a storage element, a first pipeline, and a second pipeline. The pipelines are...
US-7,093,093 Cache management system
A processing system optimized for data string manipulations includes data string execution circuitry associated with a bus interface unit or memory controller....
US-7,093,066 Method for bus capacitance reduction
Data bus capacitance is reduced by decoupling unaccessed memory circuits from a data bus during data transfers to or from other memory circuits.
US-7,093,062 Flash memory data bus for synchronous burst read page
Memory device is described that utilizes a reduced number of sense amplifiers to sense the data bits of a selected column page. The sense amplifiers are...
US-7,092,312 Pre-emphasis for strobe signals in memory device
A memory device has a number of data terminals for transferring data signals and a number of strobe terminals for transferring strobe signals representing timing...
US-7,092,285 State save-on-power-down using GMR non-volatile elements
The semiconductor industry seeks to reduce the risk of traditional volatile storage devices with improved non-volatile storage devices. The increased demand for...
US-7,092,271 CAM memory architecture and a method of forming and operating a device according to a CAM memory architecture
A method for operating a content addressable memory that includes receiving a first data value for evaluation at a first memory block during a first time...
US-7,092,234 DRAM cells and electronic systems
The invention includes capacitor constructions which have a layer of aluminum oxide between a high-k dielectric material and a layer containing titanium and...
US-7,092,233 Capacitor electrode having an interface layer of different chemical composition formed on a bulk layer
An improved capacitor that is less susceptible to the depletion effect and methods for providing the same. The capacitor comprises a first and second electrode...
US-7,092,021 Frame shuttering scheme for increased frame rate
A frame shutter apparatus comprising a controller for controlling multiple groups of pixels and for reading out values corresponding to the charge collected by...
US-7,091,828 Interrogators, methods of operating a coherent interrogator, backscatter communication methods, interrogation...
The present invention includes phase shifters, interrogators, methods of shifting a phase angle of a signal, and methods of operating an interrogator. One aspect...
US-7,091,654 Field emission tips, arrays, and devices
A method for fabricating field emitters from a conductive or semiconductive substrate. A layer of low work function material may be formed on the substrate....
US-7,091,622 Semiconductor device, ball grid array connection system, and method of making
A semiconductor device is provided with a metal stiffening layer between the die and a multilayer structure comprising at least two insulating layers each having...
US-7,091,611 Multilevel copper interconnects with low-k dielectrics and air gaps
Structures and methods are provided for an improved multilevel wiring interconnect in an integrated circuit assembly. The present invention provides for a...
US-7,091,584 Semiconductor package assembly and method for electrically isolating modules
A semiconductor package assembly and method for electrically isolating modules, having a capacitor within the semiconductor package assembly. The package...
US-7,091,575 Open pattern inductor
The invention includes a stacked open pattern inductor fabricated above a semiconductor substrate. The stacked open pattern inductor includes a plurality of...
US-7,091,549 Programmable memory devices supported by semiconductor substrates
The invention includes a memory device supported by a semiconductor substrate and comprising in ascending order from the substrate: a floating gate, a dielectric...
US-7,091,536 Isolation process and structure for CMOS imagers
A barrier implanted region of a first conductivity type located below an isolation region of a pixel sensor cell and spaced from a doped region of a second...
US-7,091,531 High dynamic range pixel amplifier
A pixel cell with increased dynamic range is formed by providing a floating diffusion region having a variable capacitance, controlled by at least one gate...
US-7,091,513 Cathode assemblies
In one aspect, the invention encompasses a method of treating the end portions of an array of substantially upright silicon-comprising structures. A substrate...
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