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Patent # Description
US-7,091,060 Circuit and substrate encapsulation methods
A ball grid array assembly includes a package cover that encapsulates a die and a portion of a substrate to which the die is attached, including an edge of the...
US-7,091,059 Method of forming a photosensor comprising a plurality of trenches
A method of forming a multiple-trench photosensor for use in a CMOS imager having an improved charge capacity. The multi-trench photosensor may be either a...
US-7,090,815 Nanometer engineering of metal-support catalysts
A method of forming a catalyst body by forming a first layer of hemispherical grain polysilicon over a substrate, and oxidizing at least a portion of the first...
US-7,090,750 Plating
An apparatus and method for treating a substrate to deposit, clean or etch material on a substrate using a first horizontal chuck to which a plurality of...
US-7,090,727 Heated gas line body feedthrough for vapor and gas delivery systems and methods for employing same
A feedthrough device for use in deposition chambers such as chemical vapor deposition chambers and atomic layer deposition chambers and methods using the same in...
US-7,089,449 Recovering a system that has experienced a fault
A method and system of recovering a system that has experienced a fault includes a backup device to enable access of a network through the interface in response...
US-7,089,438 Circuit, system and method for selectively turning off internal clock drivers
The present invention includes a circuit, system and method for selectively turning off internal clock drivers to reduce operating current. The present invention...
US-7,089,375 Device and method for configuring a cache tag in accordance with burst length
In a cache tag integrated on an SRAM with a memory cache, laser fuses are programmed to indicate which, if any, tag subarrays in the cache tag are not...
US-7,089,352 CAM modified to be used for statistic calculation in network switches and routers
A content addressable memory (CAM) device includes a plurality of entries each having an associated counter. When a CAM entry matches a search word stored in the...
US-7,088,625 Distributed write data drivers for burst access memories
An address strobe latches a first address. A burst cycle increments the address internally with additional address strobes. A new memory address is only required...
US-7,088,619 Method for programming and erasing an NROM cell
A nitride read only memory (NROM) cell can be programmed by applying a ramp voltage to the gate input, a constant voltage to one of the two source/drain regions,...
US-7,088,604 Multi-bank memory
A multi-bank memory device includes rows and columns of memory cores. Each row includes memory cores from one bank interleaved with memory cores from another...
US-7,088,603 DRAM CAM memory
A CAM device combines a folded bit line architecture with a standard six transistor DRAM based CAM cell and includes a sensing scheme where the active and...
US-7,088,590 Soldermask opening to prevent delamination
A multilayer circuit board includes a base layer, a conductive layer and a soldermask. The soldermask layer has two sets of openings. One of the openings are...
US-7,088,468 Data-conversion method for a multibeam laser writer for very complex microlithographic patterns
The invention relates to microlithography, in particular to the writing of photomasks for computer displays, microelectronic devices, and precision photoetching....
US-7,088,394 Charge mode active pixel sensor read-out circuit
An apparatus such as an imager includes groups of sensors each of which includes subgroups of sensors. Subgroup select circuits are coupled to outputs from...
US-7,088,156 Delay-locked loop having a pre-shift phase detector
A clock generator for generating an output clock signal synchronized with an input clock signal having first and second adjustable delay lines. The first...
US-7,088,037 Field emission display device
A system and method for fabricating a FED device is disclosed. The system and method provide for use of PECVD hydrogenation followed by nitrogen plasma treatment...
US-7,087,995 Microelectronic device packages and methods for controlling the disposition of non-conductive materials in such...
A microelectronic package and method for forming such a package. In one embodiment, the package can include a microelectronic substrate having first connection...
US-7,087,994 Microelectronic devices including underfill apertures
Supports (40) of microelectronic devices (10) are provided with underfill apertures (60) which facilitate filling underfill gaps (70) with underfill material...
US-7,087,992 Multichip wafer level packages and computing systems incorporating same
The present invention defines a packaging implementation providing a multichip multilayer system on a chip solution. Greater integration of a plurality and...
US-7,087,984 Methods for protecting intermediate conductive elements of semiconductor device assemblies
A method for protecting intermediate conductive elements, such as bond wires, of semiconductor device assemblies, includes sequentially fabricating one or more...
US-7,087,954 In service programmable logic arrays with low tunnel barrier interpoly insulators
Structures and methods for in service programmable logic arrays with low tunnel barrier interpoly insulators are provided. The in-service programmable logic...
US-7,087,949 Selective hemispherical silicon grain (HSG) conversion inhibitor for use during the manufacture of a...
A method used to form a semiconductor device comprises forming a layer such as a container capacitor layer having a bottom plate layer. The bottom plate layer is...
US-7,087,944 Image sensor having a charge storage region provided within an implant region
A deep implanted region of a first conductivity type located below a transistor array of a pixel sensor cell and adjacent a doped region of a second conductivity...
US-7,087,919 Layered resistance variable memory device and method of fabrication
The invention is related to methods and apparatus for providing a resistance variable memory element with improved data retention and switching characteristics....
US-7,087,561 Cleaning composition useful in semiconductor integrated circuit fabrication
A composition for use in semiconductor processing wherein the composition comprises water, phosphoric acid, and an organic acid; wherein the organic acid is...
US-7,087,535 Deposition methods
A deposition method includes contacting a substrate with a first initiation precursor and forming a first portion of an initiation layer on the substrate. At...
US-7,087,534 Semiconductor substrate cleaning
Methods for removing titanium-containing layers from a substrate surface where those titanium-containing layers are formed by chemical vapor deposition (CVD)...
US-7,087,527 Extended kalman filter incorporating offline metrology
An algorithm uses offline metrology to control a process by passing information from an outer control loop to an inner control loop, extended Kalman filter...
US-7,087,525 Methods of forming layers over substrates
The invention includes methods of forming films over substrates. A substrate is provided within a reaction chamber, and a mixture is also provided within the...
US-7,087,511 Method for conducting heat in a flip-chip assembly
A method and apparatus for thermally conducting heat from a semiconductor device, namely, a flip-chip assembly. In one embodiment, a heat sink, such as a diamond...
US-7,087,490 Method and composite for decreasing charge leakage
A dielectric insulating composite for insulating a floating gate from a control gate in a non-volatile memory is described. A material, such as an undoped...
US-7,087,481 Systems and methods for forming metal oxides using metal compounds containing aminosilane ligands
A method of forming (and an apparatus for forming) a metal oxide layer on a substrate, particularly a semiconductor substrate or substrate assembly, using a...
US-7,087,478 Methods of forming semiconductor constructions
The invention includes a semiconductor construction having a pair of channel regions that have sub-regions doped with indium and surrounded by boron. A pair of...
US-7,087,468 Method for forming conductors in semiconductor devices
A memory device wherein a diode is serially connected to a programmable resistor and is in electrical communication with a buried digit line. An electrically...
US-7,087,460 Methods for assembly and packaging of flip chip configured dice with interposer
A method for assembly and packaging of one or more flip chip-configured semiconductor dice with an interposer substrate to form a flip chip-type semiconductor...
US-7,087,454 Fabrication of single polarity programmable resistance structure
A resistance variable memory element with improved data retention and switching characteristics switched between resistance memory states upon the application of...
US-7,087,182 Process of forming an electrically erasable programmable read only memory with an oxide layer exposed to...
The present invention provides a flash memory integrated circuit and a method of fabricating the same. A tunnel dielectric in an erasable programmable read only...
US-7,087,133 Methods for application of adhesive tape to semiconductor devices
A method and apparatus for application of adhesive tape to semiconductor devices are discolsed. A first adhesively coated tape material length is supplied to a...
US-7,087,119 Atomic layer deposition with point of use generated reactive gas species
An apparatus for atomic layer deposition preventing mixing of a precursor gas and an input gas. From the apparatus a flow of the input gas is provided over a...
US-7,087,116 Apparatus for modifying the configuration of an exposed surface of a viscous fluid
A method and apparatus for achieving a level exposed surface of a viscous material pool for applying viscous material to at least one semiconductor component by...
US-7,087,111 Method of forming a refractory metal silicide
A method of forming a crystalline phase material includes, a) providing a stress inducing material within or operatively adjacent a crystalline material of a...
US-7,086,927 Methods and systems for planarizing workpieces, e.g., microelectronic workpieces
This disclosure provides methods and apparatus for predictably changing the thickness of a microfeature workpiece. One implementation provides a planarizing...
US-7,086,562 Methods and apparatus for retaining a tray stack having a plurality of trays for carrying microelectronic devices
Devices and methods for holding a tray stack having a plurality of trays configured to carry and store microelectronic devices. Several devices in accordance...
US-7,086,031 Methods of forming patterned reticles
The invention includes methods of forming patterned reticles. Design features can be introduced into a layout for a reticle prior to optical proximity...
US-7,085,975 Method and apparatus for generating expect data from a captured bit pattern, and memory device using same
Expect data signals are generated for a series of applied data signals having a known sequence to determine if groups of the data signals were properly captured....
US-7,085,912 Sequential nibble burst ordering for data
Methods of operating a memory device comprised of a plurality of arrays of memory cells and peripheral devices for reading and writing information to the memory...
US-7,085,908 Linear object management for a range of flash memory
Data object management for a range of memory. The range of memory has first and second opposite ends. A plurality of data objects are written to a first...
US-7,085,880 Method and apparatus for address FIFO for high-bandwidth command/address busses in digital storage system
A method of buffering a data stream in an electronic device using a first-in first-out (FIFO) buffer system wherein the first read latch signal does not change...
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