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Patent # Description
US-7,102,361 Delay lock circuit having self-calibrating loop
A delay lock circuit includes a measuring path, a forward path, and a feedback path. The measuring path samples a pulse with a reference signal in a measurement...
US-7,102,217 Interposer substrates with reinforced interconnect slots, and semiconductor die packages including same
A board-on-chip (BOC) semiconductor package includes a multisegmented, longitudinally slotted interposer substrate through which an elongate row of die bond pads...
US-7,102,191 Memory device with high dielectric constant gate dielectrics and metal floating gates
A memory cell transistor includes a high dielectric constant tunnel insulator, a metal floating gate, and a high dielectric constant inter-gate insulator...
US-7,102,184 Image device and photodiode structure
The invention provides a photodiode with an increased charge collection area, laterally spaced from an adjacent isolation region. Dopant ions of a first...
US-7,102,180 CMOS imager pixel designs
A charge storage capacitor which is connected to various light sensitive and/or electrical elements of a CMOS imager, as well as methods of formation, are...
US-7,102,151 Small electrode for a chalcogenide switching device and method for fabricating same
A memory cell and a method of fabricating the memory cell having a small active area. By forming a spacer in a window that is sized at the photolithographic...
US-7,101,815 Method for improving thickness uniformity of deposited ozone-TEOS silicate glass layers
A method for depositing highly conformal silicate glass layers via chemical vapor deposition through the reaction of TEOS and O.sub.3 is provided, comprising...
US-7,101,814 Masking without photolithography during the formation of a semiconductor device
A method for forming a semiconductor device comprises forming a dielectric layer over a semiconductor wafer substrate assembly having closely-spaced regions,...
US-7,101,813 Atomic layer deposited Zr-Sn-Ti-O films
A dielectric film containing atomic layer deposited Zr--Sn--Ti--O and a method of fabricating such a dielectric film produce a reliable dielectric layer having...
US-7,101,792 Methods of plating via interconnects
Methods for filling high aspect ratio vias with conductive material. At least one high aspect ratio via is formed in the backside of a semiconductor substrate....
US-7,101,779 Method of forming barrier layers
Mixed metal aluminum nitride and boride diffusion barriers and electrodes for integrated circuits, particularly for DRAM cell capacitors. Also provided are...
US-7,101,778 Transmission lines for CMOS integrated circuits
Improved methods and structures are provided for impedance-controlled low-loss lines in CMOS integrated circuits. The present invention offers a reduction in...
US-7,101,771 Spin coating for maximum fill characteristic yielding a planarized thin film surface
A method for spinning a material onto a semiconductor device structure so as to substantially fill recesses formed in a surface of the semiconductor device...
US-7,101,770 Capacitive techniques to reduce noise in high speed interconnections
Improved methods and structures are provided using capacitive techniques to reduce noise in high speed interconnections, such as in CMOS integrated circuits. The...
US-7,101,767 Methods of forming capacitors
In one implementation, an opening within a capacitor electrode forming layer is formed over a substrate. A spacing layer is deposited over the capacitor...
US-7,101,756 Methods for enhancing capacitors having roughened features to increase charge-storage capacity
Structures and methods for making a semiconductor structure are discussed. The semiconductor structure includes a rough surface having protrusions formed from an...
US-7,101,747 Dual work function metal gates and methods of forming
Complementary transistors and methods of forming the complementary transistors on a semiconductor assembly are described. The transistors can be formed from a...
US-7,101,738 Gate dielectric antifuse circuit to protect a high-voltage transistor
According to embodiments of the present invention, circuits have elements to protect a high-voltage transistor in a gate dielectric antifuse circuit. An antifuse...
US-7,101,737 Method of encapsulating interconnecting units in packaged microelectronic devices
Methods and apparatuses for encapsulating a microelectronic die or other components in the fabrication of packaged microelectronic devices. In one aspect of the...
US-7,101,730 Method of manufacturing a stackable ball grid array
A method of manufacturing a stackable package to create a 3-dimensional memory array using ball grid array technology. Specifically, memory chips are coupled to...
US-7,101,727 Passivation planarization
A pixel cell is formed by locating a first passivation layer over the final layer of metal lines. Subsequently, the uneven, non-uniform passivation layer is...
US-7,101,594 Methods of forming capacitor constructions
The invention includes a method of treating a predominantly inorganic dielectric material on a semiconductor wafer. A laser is utilized to generate activated...
US-7,101,586 Method to increase the emission current in FED displays through the surface modification of the emitters
A system and method for fabricating a FED device is disclosed. The system and method provide for use of PECVD hydrogenation followed by nitrogen plasma treatment...
US-7,101,435 Methods for epitaxial silicon growth
Methods of cleaning substrates and growing epitaxial silicon thereon are provided. Wafers are exposed to a plasma for a sufficient time prior to epitaxial...
US-7,099,992 Distributed programmable priority encoder capable of finding the longest match in a single operation
A distributed, hierarchically-structured, programmable priority encoder for a content addressable memory (CAM) device including at least one section, the section...
US-7,099,989 System and technique to reduce cycle time by performing column redundancy checks during a delay to accommodate...
A memory device includes a memory cell array, an addressing circuit, a data communication circuit and a control circuit. The addressing circuit receives first...
US-7,099,221 Memory controller method and system compensating for memory cell data losses
A computer system includes a memory controller coupled to a memory module containing several DRAMs. The memory module also includes a non-volatile memory storing...
US-7,099,220 Methods for erasing flash memory
Methods for erasing flash memory using a decrease in magnitude of a source voltage of a first polarity to increase the magnitude of a control gate voltage of a...
US-7,099,212 Embedded ROM device using substrate leakage
A ROM embedded DRAM provides ROM cells that can be programmed to a single state. The ROM cells include capacitors having a storage node. The storage node is...
US-7,099,195 Methods for neutralizing holes in tunnel oxides of floating-gate memory cells and devices
Methods for neutralizing holes in tunnel oxides of floating-gate memory cells and devices using a decrease in magnitude of a source voltage of a first polarity...
US-7,099,174 Metal wiring pattern for memory devices
A memory integrated circuit having three layers of metallic traces disposed over a substrate assembly including various active devices. The traces are arranged...
US-7,099,172 Static content addressable memory cell
A static content addressable memory (CAM) cell. The CAM cell includes a latch having complementary data nodes capacitively coupled to ground, first and second...
US-7,098,724 Forward biasing protection circuit
A forward biasing protection circuit is provided. More specifically, there is provided a device comprising a transistor, a resistive element coupled to the body...
US-7,098,714 Centralizing the lock point of a synchronous circuit
A system and method to establish the lock point of a digital synchronous circuit (e.g., a DLL) at the center of or close to the center of its delay line is...
US-7,098,587 Preventing junction leakage in field emission devices
An apparatus and a method for stabilizing the threshold voltage in an active matrix field emission device are disclosed. The method includes the formation of...
US-7,098,527 Integrated circuit package electrical enhancement with improved lead frame design
A configuration for a conventional lead frame for conserving limited leads and for allowing the location of bond pads anywhere on the periphery of the...
US-7,098,503 Circuitry and capacitors comprising roughened platinum layers
In one aspect, the invention includes a method of forming a roughened layer of platinum, comprising: a) providing a substrate within a reaction chamber; b)...
US-7,098,475 Apparatuses configured to engage a conductive pad
A method of engaging electrically conductive test pads on a semiconductor substrate having integrated circuitry for operability testing thereof includes: a)...
US-7,098,128 Method for filling electrically different features
Methods of electroless filling electrically different features such as contact openings to form interconnects and conductive contacts, and semiconductor devices,...
US-7,098,122 Method of fabricating a vertically integrated memory cell
A unique cell structure for use in flash memory cell and a method of fabricating the memory cell. More particularly, a vertically integrated transistor having a...
US-7,098,105 Methods for forming semiconductor structures
The invention includes a semiconductor structure having a gateline lattice surrounding vertical source/drain regions. In some aspects, the source/drain regions...
US-7,098,068 Method of forming a chalcogenide material containing device
Embodiments of the invention provide a method of forming a chalcogenide material containing device, and particularly resistance variable memory elements. A stack...
US-7,097,782 Method of exposing a substrate to a surface microwave plasma, etching method, deposition method, surface...
In certain implementations, methods and apparatus include an antenna assembly having at least two overlapping and movable surface microwave plasma antennas. The...
US-7,097,546 System and method for reducing surface defects in integrated circuits
The fabrication of integrated circuits entails the repeated application of many basic processing steps, for instance, planarization--the process of making a...
US-7,097,526 Method of forming nitrogen and phosphorus doped amorphous silicon as resistor for field emission display device...
Described herein is a resistor layer for use in field emission display devices and the like, and its method of manufacture. The resistor layer is an amorphous...
US-7,097,373 Printer
A printer including a cutting portion including a plate-shaped fixed blade, a plate-shaped movable blade and a driving unit, which drives the movable blade back...
US-7,096,452 Method and device for checking lithography data
Devices and methods are provided that include advantages such as the ability to identify sizes, shapes and locations of frequently unwanted additional features...
US-7,096,446 Hierarchical semiconductor design
Hierarchical semiconductor structure design is disclosed. One aspect of the invention is a computerized system that includes a semiconductor structure (such as a...
US-7,096,370 Data security for digital data storage
A computer system encrypts user generated data with an encryption process, wherein the encryption process is defined at least in part with information assigned...
US-7,096,304 Apparatus and method for managing voltage buses
The present technique relates to a method and apparatus for managing voltage buses. In a memory device, such as SRAM or DRAM, a periphery voltage bus may supply...
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