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Patent # Description
US-7,186,664 Methods and structures for metal interconnections in integrated circuits
A typical integrated-circuit fabrication requires interconnecting millions of microscopic transistors and resistors with metal wires. Making the metal wires...
US-7,186,643 Barrier-metal-free copper damascene technology using atomic hydrogen enhanced reflow
A method for forming conductive contacts and interconnects in a semiconductor structure, and the resulting conductive components are provided. In particular, the...
US-7,186,642 Low temperature nitride used as Cu barrier layer
A method of depositing a non-conductive barrier layer onto a metal surface wherein the resistance of the metal remains substantially unchanged before and after...
US-7,186,638 Passivation processes for use with metallization techniques
A method for passivating a substrate, such as a semiconductor substrate, that is to be "metallized," or on which a metal film or structure is to be formed,...
US-7,186,636 Nickel bonding cap over copper metalized bondpads
A method for forming a nickel cap layer over copper metalized bond pad is disclosed in which the phosphorous content of the nickel cap, and particularly the...
US-7,186,608 Masked nitrogen enhanced gate oxide
A method for fabricating improved integrated circuit devices. The method enables selective hardening of gate oxide layers and includes providing a semiconductor...
US-7,186,589 Method for fabricating semiconductor components using mold cavities having runners configured to minimize venting
A system for fabricating semiconductor components includes mating mold cavity plates having mold cavities configured to mold body segments of the semiconductor...
US-7,186,576 Stacked die module and techniques for forming a stacked die module
Embodiments of the present technique relate to forming die stacks. Specifically, embodiments of the present technique include a method of forming and testing...
US-7,186,486 Method to pattern a substrate
An aspect of the present invention includes a method of lithography to enhance uniformity of critical dimensions of features patterned onto a workpiece. Said...
US-7,186,480 Method for adjusting dimensions of photomask features
A method for adjusting one or more dimensions of a photomask subsequent to etching of a defective pattern in the chrome-containing layer thereof is provided. The...
US-7,186,168 Chemical mechanical polishing apparatus and methods for chemical mechanical polishing
The present invention provides a deformable pad useful for chemical mechanical polishing ("CMP"), a CMP apparatus incorporating the deformable pad of the present...
US-7,185,601 Chemically sensitive warning apparatus and method
A chemically sensitive warning apparatus capable of changing colors upon contact with a chemical is disclosed. The apparatus preferably comprises an elongated...
US-7,185,173 Column address path circuit and method for memory devices having a burst access mode
Column addresses are generated by a burst controller that includes respective latches for the three low-order bits of a column address. The two higher order bits...
US-7,185,154 Single segment data object management
A single segment data structure and method for storing data objects employing a single segment data object having a header and a data record. The header includes...
US-7,184,551 Public key cryptography using matrices
The invention provides techniques for secure messages transmission using a public key system to exchange secret keys. A first entity creates public and private...
US-7,184,352 Memory system and method using ECC to achieve low power refresh
Rows of DRAM memory cells are refreshed at either a relatively high rate during normal operation or a relatively slow rate in a reduced power refresh mode. Prior...
US-7,184,329 Alignment of memory read data and clocking
Circuits and methods are provided for aligning data read from a memory with an output clock signal when the memory is operated at very high clock frequencies. To...
US-7,184,327 System and method for enhanced mode register definitions
Apparatus and methods for increasing a number of selectable options for an operating mode. A number of selectable options for an operating mode is increased by...
US-7,184,315 NROM flash memory with self-aligned structural charge separation
A nitride read only memory (NROM) cell has a nitride layer that is not located under the center of the transistor. The gate insulator layer, with the nitride...
US-7,184,312 One transistor SOI non-volatile random access memory cell
One aspect of the present subject matter relates to a memory cell, or more specifically, to a one-transistor SOI non-volatile memory cell. In various...
US-7,184,292 High speed data bus
The invention comprises data processing systems and components thereof. Such systems may include a memory controller, a plurality of memory devices, a data bus...
US-7,184,284 Closed-loop high voltage booster
A voltage boosting circuit with a closed-loop control mechanism and a controllable slew rate. A tracking capacitor and a control current form the closed-loop and...
US-7,184,192 Pattern generator diffractive mirror methods and systems
The present invention relates to an apparatus for creating a pattern on a workpiece sensitive to radiation, such as a photomask a display panel or a microoptical...
US-7,183,792 Method and system for detecting a mode of operation of an integrated circuit, and a memory device including same
A threshold detection circuit for developing a mode trigger signal includes an input that receives an input signal. In response to the input signal having...
US-7,183,790 System and method for testing devices utilizing capacitively coupled signaling
An apparatus and method for testing a semiconductor device in an AC test regime. The test apparatus includes a test plate capacitively couple to the signal...
US-7,183,621 MRAM memory cell having an electroplated bottom layer
The present invention provides a method of forming an MRAM cell which minimizes the occurrence of electrical shorts during fabrication. A first conductor in a...
US-7,183,611 SRAM constructions, and electronic systems comprising SRAM constructions
The invention includes SRAM constructions comprising at least one transistor device having an active region extending into a crystalline layer comprising Si/Ge....
US-7,183,531 Amplification with feedback capacitance for photodetector signals
Signals from an imager pixel photodetector are received by an amplifier having capacitive feedback, such as a capacitive transimpedance amplifier (CTIA). The...
US-7,183,485 Microelectronic component assemblies having lead frames adapted to reduce package bow
The present disclosure suggests various microelectronic component assembly designs and methods for manufacturing microelectronic component assemblies. In one...
US-7,183,220 Plasma etching methods
A plasma etching method includes forming a polymer comprising carbon and a halogen over at least some internal surfaces of a plasma etch chamber. After forming...
US-7,183,208 Methods for treating pluralities of discrete semiconductor substrates
The invention includes a method for treating a plurality of discrete semiconductor substrates. The discrete semiconductor substrates are placed within a reactor...
US-7,183,194 Method of forming socket contacts
In a socket used to house semiconductor die during testing, a recessed socket contact and methods of making the same are provided that avoid pinching the die's...
US-7,183,191 Method for fabricating a chip scale package using wafer level processing
Channels are formed that pass through an active surface of a semiconductor substrate to provide isolation between adjacent active surface regions defining...
US-7,183,185 Methods of forming transistor gates; and methods of forming programmable read-only memory constructions
The invention includes a method of forming a transistor gate. One or more conductive materials are formed over a semiconductor substrate, and a block is formed...
US-7,183,164 Methods of reducing floating body effect
Methods of reducing the floating body effect in vertical transistors are disclosed. The floating body effect occurs when an active region in a pillar is cut off...
US-7,183,138 Method and apparatus for decoupling conductive portions of a microelectronic device package
A method and apparatus for decoupling conductive portions of a microelectronic device package. In one embodiment, the package can include a microelectronic...
US-7,183,134 Ultrathin leadframe BGA circuit package
A circuit package is formed using a leadframe. The leadframe is formed or etched to align a plurality of bond pad structures above a reference plane while...
US-7,183,133 Microelectronic devices with improved heat dissipation and methods for cooling microelectronic devices
Microelectronic devices with improved heat dissipation, methods of making microelectronic devices, and methods of cooling microelectronic devices are disclosed...
US-7,182,979 High efficiency method for performing a chemical vapordeposition utilizing a nonvolatile precursor
A method directed to the use of a nonvolatile precursor, either a solid or liquid precursor, suitable for CVD, including liquid source CVD (LSCVD). Using the...
US-7,182,669 Methods and systems for planarizing workpieces, e.g., microelectronic workpieces
Planarizing workpieces, e.g., microelectronic workpieces, can employ a process indicator that is adapted to change an optical property in response to a...
US-7,182,668 Methods for analyzing and controlling performance parameters in mechanical and chemical-mechanical...
Methods and apparatuses for analyzing and controlling performance parameters in planarization of microelectronic substrates. In one embodiment, a planarizing...
US-7,182,241 Multi-functional solder and articles made therewith, such as microelectronic components
Aspects of the invention provide solder compositions which include two different fluxing agents. One of the fluxing agents promotes melting of a metal of the...
US-7,181,837 Plating buss and a method of use thereof
The present invention relates generally to a plating buss design and method for minimizing short circuit problems in PCB panel singulation. More particularly,...
US-7,181,593 Active memory command engine and method
A command engine for an active memory receives high level tasks from a host and generates corresponding sets of either DCU commands to a DRAM control unit or ACU...
US-7,181,584 Dynamic command and/or address mirroring system and method for memory modules
A memory module includes a memory hub that couples signals to memory devices mounted on opposite first and second surfaces of a memory module substrate. The...
US-7,181,566 Scratch control memory array in a flash memory device
A memory device has a scratch control array of non-volatile memory cells that is separate from the primary array of memory cells. The scratch control array...
US-7,180,803 Data compression read mode for memory testing
Memory devices having a normal mode of operation and a test mode of operation are useful in quality programs. The test mode of operation includes a data...
US-7,180,802 Method of stress-testing an isolation gate in a dynamic random access memory
The present invention includes a DRAM array. The DRAM array includes a first memory cell, a second memory cell and an isolation gate formed between the first and...
US-7,180,797 Reduced power registered memory module and method
A registered memory module includes a plurality of flip-flops having respective data terminals, respective clock terminals receiving a clock signal and output...
US-7,180,791 Flash with consistent latency for read operations
A synchronous flash memory includes an array of non-volatile memory cells. The memory device has a package configuration that is compatible with an SDRAM. The...
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