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Dual conversion gain imagers
An imager with dual conversion gain floating diffusion regions. The dual conversion gain regions yield (1) high conversion gain and sensitivity to achieve...
Etchant and method of use
A method of anisotropiocally etching a semiconductive substrate uses a hydrofluorocarbon etch gas with an etch selectivity fluorocarbon gas. The fluorocarbon gas...
Damascene processes for forming conductive structures
A method and apparatus for providing a conductive structure adjacent to a damascene conductive structure in a semiconductor device structure. The semiconductor...
Service programmable logic arrays with low tunnel barrier interpoly
Structures and methods for in service programmable logic arrays with low tunnel barrier interpoly insulators are provided. The in-service programmable logic...
Method for packaging flip-chip semiconductor assemblies
Flip-chip semiconductor assemblies, each including integrated circuit (IC) dice and an associated substrate, are electrically tested before encapsulation using...
Carrier assemblies, polishing machines including carrier assemblies, and
methods for polishing micro-device...
Carrier assemblies, polishing machines with carrier assemblies, and methods for mechanical and/or chemical-mechanical polishing of micro-device workpieces are...
Methods and apparatus for removing conductive material from a
A method and apparatus for removing conductive material from a microelectronic substrate. In one embodiment, a support member supports a microelectronic...
Methods of forming patterned reticles
The invention includes methods of forming patterned reticles. Design features can be introduced into a layout for a reticle prior to optical proximity...
Providing a register file memory with local addressing in a SIMD parallel
A degree of local addressing is provided for a processing element array by partitioning a register file memory (e.g., data columns, data rows), and adding a...
System and method for encoding processing element commands in an active
A command engine for an active memory receives high level tasks from a host and generates corresponding sets of either DRAM control unit ("DCU") commands to a...
Random access interface in a serial memory device
A random access interface is provided to a non-volatile, serial memory array. An address multiplexer has an external address connection and a serial address...
Synchronous non-volatile memory system
A computer system comprises a memory controller and a synchronous non-volatile memory device coupled to the memory controller via a main memory bus. The...
Method and apparatus for generating deterministic, non-repeating,
A system and method for rapidly generating a series of non-repeating, deterministic, pseudo-random addresses is disclosed. A deterministic, pseudo-random number...
Interpolation error minimization for data reduction
Systems and methods are provided for reducing a set of data points into a subset of best fit data points. According to one aspect, a method of adjusting a series...
Delay locked loop fine tune
A digital delay locked loop (DLL) includes a coarse delay segment and fine delay segment. The coarse delay segment includes a coarse delay range. The fine delay...
Method and system for low power refresh of dynamic random access memories
A method and system for operating a DRAM device in either a high power, full density mode or a low power, half density mode. In the full density mode, each data...
Bias sensing in DRAM sense amplifiers through coupling and decoupling
Voltage coupling/decoupling devices are provided within DRAM devices for improving the bias sensing of sense amplifiers and thus the refresh performance. The...
Reduced power registered memory module and method
A registered memory module includes a plurality of flip-flops having respective data terminals, respective clock terminals receiving a clock signal and output...
Method and apparatus for standby power reduction in semiconductor devices
A word line driver circuit for a semiconductor memory device. One or more transistors in the driver circuit are fabricated such that they are susceptible, under...
Asymmetric band-gap engineered nonvolatile memory device
Systems and methods are provided for nonvolatile memory devices that incorporate a band-gap engineered gate stack with asymmetric tunnel barriers. One embodiment...
Multi-state memory cell with asymmetric charge trapping
A multi-state NAND memory cell is comprised of two drain/source areas in a substrate. An oxide-nitride-oxide structure is formed above the substrate between the...
NROM flash memory cell with integrated DRAM
A memory device that is comprised of a dynamic random access memory (DRAM) capacitor and a nitride read only memory (NROM) transistor. The memory device provides...
Magnetic memory having synthetic antiferromagnetic pinned layer
A magnetic memory element includes a sense structure, a tunnel barrier adjacent the sense structure, and a synthetic antiferromagnet (SAF) adjacent the tunnel...
Addressing of an SLM
The present invention relates to a method to reduce charging effects affecting a degree of movement of at least one movable micro mirror in a spatial light...
Accelerated graphics port for a multiple memory controller computer system
An architecture for storing, addressing and retrieving graphics data from one of multiple memory controllers. In a first embodiment of the invention, one of the...
Radio frequency identification devices, remote communication devices,
identification systems, communication...
The present invention provides radio frequency identification devices, remote communication devices, identification systems, communication methods, and...
Low supply voltage bias circuit, semiconductor device, wafer and system
including same, and method of...
A bias generator and a method of generating a bias reference are disclosed. A reference transistor is connected in a diode configuration. An n-channel transistor...
Voltage level translator circuitry
Circuitry and methods for implementing voltage level translators at relatively low source voltages are provided. The circuitry and methods utilize voltage...
Agglomeration control using early transition metal alloys
Structures and methods of fabricating portions of integrated circuit devices to reduce agglomeration tendencies of high surface-energy metals used in...
Metallization structures for semiconductor device interconnects, methods
for making same, and semiconductor...
The present invention provides a metallization structure for semiconductor device interconnects such as a conductive line, and methods for making the same,...
Lead frame decoupling capacitor, semiconductor device packages including
the same and methods
A lead frame includes at least two layers, each of which includes an electrically conductive bus and a group of leads that extend substantially unidirectionally...
Antifuse structure and method of use
An antifuse structure and method of use are disclosed. According to one embodiment of the present invention a first programming voltage is coupled to a well of a...
Trench isolation for semiconductor devices
A method of fabricating an integrated circuit includes forming an isolation trench in a semiconductor substrate and partially filling the trench with a...
Capacitor constructions, semiconductor constructions, and methods of
forming electrical contacts and...
The invention includes a method of forming a semiconductor construction. A semiconductor substrate is provided, and a conductive node is formed to be supported...
Method and apparatus for reducing imager floating diffusion leakage
An imager having reduced floating diffusion leakage and a mechanism for improving the storing of collected charge is described. A polysilicon contact is provided...
Stacked microfeature devices and associated methods
Stacked microfeature devices and associated methods of manufacture are disclosed. A package in accordance with one embodiment includes first and second...
Methods and apparatus for a flexible circuit interposer
A flexible circuit interposer includes a flexible circuit substrate which allows in-situ probing of an attached device during, for example, circuit debugging,...
Method for producing water for use in manufacturing semiconductors
Disclosed is a process of treating semiconductor substrates, including the production of pure water, a method of producing the pure water for semiconductor...
Semiconductor devices and methods for depositing a dielectric film
Embodiments provide methods and apparatuses for chemical vapor depositing a dielectric film, and various structures, devices, and systems, which incorporate...
Methods of fabricating interconnects for semiconductor components
including a through hole entirely through the...
In one aspect, the invention encompasses a method of fabricating an interconnect for a semiconductor component. A semiconductor substrate is provided, and an...
Methods for securing components of semiconductor device assemblies to each
other with hybrid adhesive materials
A method for securing two or more semiconductor device components to one another is provided. A hybrid adhesive material, including a pressure-sensitive...
Fabrication of integrated devices using nitrogen implantation
A process is provided for forming an isolating nitride film to isolate gate polysilicon of a gate structure. Specifically, the process comprises providing a...
Methods of forming capacitors, and methods of forming DRAM circuitry
Capacitors, DRAM circuitry, and methods of forming the same are described. In one embodiment, a capacitor comprises a first container which is joined with a...
Method of forming a dual-sided capacitor
A dual-sided HSG capacitor and a method of fabrication are disclosed. A thin native oxide layer is formed between a doped polycrystalline layer and a layer of...
Method of forming a contact structure including a vertical barrier
structure and two barrier layers
This invention relates to contact structures for use in integrated circuits and methods of fabricating contact structures. In one embodiment, a contact structure...
Silicon rich barrier layers for integrated circuit devices
Semiconductor devices and memory cells are formed using silicon rich barrier layers to prevent diffusion of dopants from differently doped polysilicon films to...
Methods of forming a field effect transistor having source/drain material
over insulative material
In one implementation, a method of forming a field effect transistor includes etching an opening into source/drain area of a semiconductor substrate. The opening...
Method of making a flexible substrate with a filler material
A method of adding a thermally conductive, electrically nonconductive filler to a flexible substrate such as a polyimide core. The substrate may be used, for...
PCRAM memory cell and method of making same
An inverted PCRAM cell is formed by plating the bottom electrode, made of copper for example, with a conductive material, such as silver. Chalcogenide material...
Method of forming an elevated photodiode in an image sensor
The invention provides an elevated photodiode for image sensors and methods of formation of the photodiode. Elevated photodiodes permit a decrease in size...