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Patent # Description
US-7,084,429 Strained semiconductor by wafer bonding with misorientation
One aspect of the present invention relates to a method for forming a strained semiconductor structure. In various embodiments, at least two strong bonding...
US-7,084,413 Photolithographic techniques for producing angled lines
The present subject matter allows non-orthogonal lines to be formed at the same thickness as the orthogonal lines so as to promote compact designs, to be formed...
US-7,084,351 Electrical device allowing for increased device densities
A device comprising a circuit, a lead having a first end connected to the circuit and having a second end, and a deformable structure connected to the second end...
US-7,084,078 Atomic layer deposited lanthanide doped TiOx dielectric films
A dielectric film containing atomic layer deposited lanthanide doped TiO.sub.x and a method of fabricating such a dielectric film produce a reliable dielectric...
US-7,084,067 Removal of copper oxides from integrated interconnects
An apparatus and a method for photoreducing copper oxide layers from semiconductor wafers during the processes of forming interconnects in advanced IC...
US-7,084,058 Method of forming low-loss coplanar waveguides
Coplanar waveguides having a deep trench between a signal line and a ground plane and methods of their fabrication are disclosed. An oxide layer is provided over...
US-7,084,015 Semiconductor constructions
The invention includes methods of forming implant regions between and/or under transistor gates. In one aspect, a pair of transistor gates is partially formed,...
US-7,084,013 Methods for forming protective layers on semiconductor device substrates
Methods for forming protective layers on semiconductor devices, including semiconductor devices that are carried by fabrication substrates, that are parts of...
US-7,084,012 Programmed material consolidation processes for protecting intermediate conductive structures
A method for protecting intermediate conductive elements, such as bond wires, of semiconductor device assemblies includes selectively altering a state of...
US-7,084,004 MEMS heat pumps for integrated circuit heat dissipation
A cooling mechanism within an integrated circuit includes an internal pump for circulating thermally conductive fluid within closed loop channels. The cooling...
US-7,083,988 Magnetic annealing sequences for patterned MRAM synthetic antiferromagnetic pinned layers
A method is provided for fabricating a fixed layer for a MRAM device. The method includes providing the fixed layer. The fixed layer includes an ...
US-7,083,700 Methods and apparatuses for planarizing microelectronic substrate assemblies
Methods and apparatuses for planarizing microelectronic substrate assemblies on fixed-abrasive polishing pads with non-abrasive lubricating planarizing...
US-7,083,425 Slanted vias for electrical circuits on circuit boards and other substrates
Circuit boards, microelectronic devices, and other apparatuses having slanted vias are disclosed herein. In one embodiment, an apparatus for interconnecting...
US-7,082,681 Methods for modifying a vertical surface mount package
A vertically mountable semiconductor device including a plurality of stub contacts extending perpendicularly from a bottom edge thereof. The stub contacts may be...
US-7,082,678 Method of fabricating an integrated circuit package
A method of forming a semiconductor package is provided. The method includes forming a leadframe wherein the conductors or leads of the leadframe extend from a...
US-7,082,581 Integrated circuit with layout matched high speed lines
A set of high speed interconnect lines for an integrated circuit has an improved line-to-line capacitance and overall RC time constant. The high speed...
US-7,082,491 Memory device having different burst order addressing for read and write operations
An apparatus enables the reordering of a block of n-bit words output from a plurality of memory cells according to information in certain address bits before...
US-7,082,075 Memory device and method having banks of different sizes
A memory device, such as a synchronous random access memory device, includes four banks of memory cells arranged in rows and columns. Different numbers of...
US-7,082,073 System and method for reducing power consumption during extended refresh periods of dynamic random access...
A dynamic random access memory ("DRAM") device is operable in either a normal refresh mode or a static refresh mode, such as a self-refresh mode. A cell plate...
US-7,082,064 Individual I/O modulation in memory devices
A DRAM circuit with reduced power consumption and in some circumstances faster memory array access speed. Input/output lines connected to a memory array are...
US-7,082,060 Soft programming for recovery of overerasure
A method of erasing a memory cell includes the step of erasing a memory cell. The current in the memory cell is measured. If the measured memory cell current...
US-7,082,059 Position based erase verification levels in a flash memory device
The location of a cell to be erase verified is determined. The erase verification threshold voltage is then set. The threshold voltage is changed in response to...
US-7,082,045 Offset compensated sensing for magnetic random access memory
An offset compensated memory element voltage supply including a differential amplifier with a compensation circuit, and a transistor with a gate connected to the...
US-7,082,033 Removing heat from integrated circuit devices mounted on a support structure
A cover, acting as a heat sink for integrated circuit devices, encloses one or more devices mounted on a support structure. The thermally conductive cover is...
US-7,081,665 Semiconductor component having thinned substrate, backside pin contacts and circuit side contacts
A semiconductor component includes back side pin contacts fabricated using a circuit side fabrication method. The component also includes a thinned semiconductor...
US-7,081,656 CMOS constructions
The invention includes methods of forming circuit devices. A metal-containing material comprising a thickness of no more than 20 .ANG. (or alternatively...
US-7,081,608 Pixel with differential readout
An imager in which two adjacent pixels share row and reset lines and a row selection circuitry while the output transistors of the two pixels are configured as a...
US-7,081,421 Lanthanide oxide dielectric layer
A ruthenium gate for a lanthanide oxide dielectric layer and a method of fabricating such a combination gate and dielectric layer produce a reliable structure...
US-7,081,416 Methods of forming field effect transistor gates
The invention includes methods of forming field effect transistor gates. In one implementation, a series of layers is formed proximate a semiconductive material...
US-7,081,398 Methods of forming a conductive line
A method of forming a local interconnect includes forming an isolation trench within a semiconductor substrate. A first trench isolation material is deposited to...
US-7,081,385 Nanotube semiconductor devices and methods for making the same
Provided herein are vertical nanotube semiconductor devices and methods for making the same. An embodiment of the semiconductor devices comprises a vertical...
US-7,080,275 Method and apparatus using parasitic capacitance for synchronizing signals a device
A method and apparatus for compensating address and control lines to account for clock delays within a memory device is disclosed. Latches are located directly...
US-7,080,193 Flash memory with accessible page during write
A synchronous flash memory includes an array of non-volatile memory cells. The memory array is arranged in rows and columns, and can be further arranged in...
US-7,079,439 Low power auto-refresh circuit and method for dynamic random access memories
A power saving circuit disables input buffers for command and address signals during an auto-refresh of a DRAM. The input buffers are re-enabled at the end of...
US-7,079,434 Noise suppression in memory device sensing
Methods of sensing a programmed state of a nonvolatile memory cell, as well as apparatus for carrying out the methods, are useful in memory devices. Latches in...
US-7,079,419 NAND flash memory with read and verification for threshold uniformity
A plurality of cells in a flash memory device are coupled together in a series configuration, as in a NAND flash memory. A position of a first accessed cell is...
US-7,079,043 Radio frequency data communications device
A radio frequency identification device comprises an integrated circuit including a receiver, a transmitter, and a microprocessor. The receiver and transmitter...
US-7,078,951 System and method for reduced power open-loop synthesis of output clock signals having a selected phase...
A signal generating circuit includes a pulse generator generating a pulse responsive to a periodic clock reference signal. The pulse propagates through a...
US-7,078,950 Delay-locked loop with feedback compensation
A delay-locked loop (DLL) with feedback compensation is provided to increase the speed and accuracy of the DLL. After the variable delay line of the DLL is...
US-7,078,823 Semiconductor die configured for use with interposer substrates having reinforced interconnect slots
A board-on-chip (BOC) semiconductor package includes a multisegmented, longitudinally slotted interposer substrate through which an elongate row of die bond pads...
US-7,078,770 Fully depleted silicon-on-insulator CMOS logic
A extractor implanted region is used in a silicon-on-insulator CMOS memory device. The extractor region is reversed biased to remove minority carriers from the...
US-7,078,760 Intermediate semiconductor device structure including multiple photoresist layers
The present invention prevents cross-linking between multiple resists that are used in the fabrication of a semiconductor device. In order to prevent resists in...
US-7,078,757 Capacitor constructions, semiconductor constructions, and methods of forming electrical contacts and...
The invention includes a method of forming a semiconductor construction. A semiconductor substrate is provided, and a conductive node is formed to be supported...
US-7,078,755 Memory cell with selective deposition of refractory metals
Methods are provided for selective formation of oxidation-resistant caps for conductive plugs in semiconductor device fabrication. One embodiment of the present...
US-7,078,746 Image sensor with floating diffusion gate capacitor
Pixel cells are provided which employ a gate capacitor associated with the floating diffusion node to selectively increase the storage capacity of the floating...
US-7,078,745 CMOS imager with enhanced transfer of charge and low voltage operation
A dopant gradient region of a first conductivity type and a corresponding channel impurity gradient below a transfer gate and adjacent a charge collection region...
US-7,078,356 Low K interlevel dielectric layer fabrication methods
A low k interlevel dielectric layer fabrication method includes providing a substrate having integrated circuitry at least partially formed thereon. An oxide...
US-7,078,342 Method of forming a gate stack
A method for forming a gate stack which minimizes or eliminates damage to the gate dielectric layer and/or silicon substrate during the gate stack formation by...
US-7,078,328 Semiconductor processing methods of transferring patterns from patterned photoresists to materials, and...
The invention includes a semiconductor processing method. A first material comprising silicon and nitrogen is formed. A second material is formed over the first...
US-7,078,327 Self-aligned poly-metal structures
A semiconductor structure is provided comprising a self-aligned poly-metal stack formed over a semiconductor substrate where the interface between an oxidation...
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