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Patent # Description
US-7,105,899 Transistor structure having reduced transistor leakage attributes
Undesirable transistor leakage in transistor structures becomes greatly reduced in substrates having a doped implant region formed via pulling back first and...
US-7,105,884 Memory circuitry with plurality of capacitors received within an insulative layer well
A method of forming memory circuitry having a memory array having a plurality of memory capacitors and having peripheral memory circuitry operatively configured...
US-7,105,881 DRAMS constructions and DRAM devices
The invention includes a DRAM device. The device has an access transistor construction, and the access transistor construction has a pair of source/drain...
US-7,105,864 Non-volatile zero field splitting resonance memory
A low-volatility or non-volatility memory device utilizing zero field splitting properties to store data. In response to an electrical pulse or a light pulse, in...
US-7,105,841 Photolithographic techniques for producing angled lines
The present subject matter allows non-orthogonal lines to be formed at the same thickness as the orthogonal lines so as to promote compact designs, to be formed...
US-7,105,793 CMOS pixels for ALC and CDS and methods of forming the same
Embodiments of the invention provide pixel cells that allow both automatic light control and correlated double sampling operations. The pixel cell includes first...
US-7,105,461 Composite dielectric forming methods and composite dielectrics
A composite dielectric forming method includes atomic layer depositing alternate layers of hafnium oxide and lanthanum oxide over a substrate. The hafnium oxide...
US-7,105,441 Preheating of chemical vapor deposition precursors
Chemical vapor deposition systems include elements to preheat reactant gases prior to reacting the gases to form layers of a material on a substrate, which...
US-7,105,437 Methods for creating electrophoretically insulated vias in semiconductive substrates
Methods are provided for creating lined vias in semiconductor substrates. Using electrophoretic deposition techniques, micelles of a lining material are...
US-7,105,432 Method of locating conductive spheres utilizing screen and hopper of solder balls
Methods for placing conductive spheres on prefluxed bond pads of a substrate using a stencil plate with a pattern of through-holes positioned over the bond pads....
US-7,105,431 Masking methods
The invention includes masking methods. In one implementation, a masking material comprising boron doped amorphous carbon is formed over a feature formed on a...
US-7,105,411 Methods of forming a transistor gate
A method of forming a transistor gate includes forming a gate oxide layer over a semiconductive substrate. Chlorine is provided within the gate oxide layer. A...
US-7,105,405 Rugged metal electrodes for metal-insulator-metal capacitors
Thin film metal-insulator-metal capacitors having enhanced surface area are formed by a substituting metal for silicon in a preformed electrode geometry. The...
US-7,105,403 Double sided container capacitor for a semiconductor device and method for forming same
A method for forming a double sided container capacitor comprises forming a first capacitor top plate layer within a recess in a dielectric layer, then forming a...
US-7,105,402 Semiconductor constructions, and methods of forming semiconductor constructions
The invention includes a DRAM array having a structure therein which includes a first material separated from a second material by an intervening insulative...
US-7,105,388 Method of forming at least one interconnection to a source/drain region in silicon-on-insulator integrated...
In one aspect, the invention provides a method of forming an electrical connection in an integrated circuitry device. According to one preferred implementation,...
US-7,105,386 High density SRAM cell with latched vertical transistors
High density static memory cells and arrays containing gated lateral bipolar transistors which can be latched in a bistable on state. Each transistor memory cell...
US-7,105,380 Method of temporarily securing a die to a burn-in carrier
A method of using adhesive tape to temporarily retain a die being temporarily held in a fixture during testing and burn-in. The method of the present invention...
US-7,105,366 Method for in-line testing of flip-chip semiconductor assemblies
Flip-chip semiconductor assemblies, each including integrated circuit (IC) dice and an associated substrate, are electrically tested before encapsulation using...
US-7,105,278 Pattern mask with features to minimize the effect of aberrations
A semiconductor pattern mask that might otherwise exhibit three-fold symmetry, which could give rise to distorted semiconductor features in the presence of...
US-7,105,208 Methods and processes utilizing microwave excitation
The invention includes methods and processes in which microwave radiation is utilized to activate at least one component within a reaction chamber during...
US-7,105,065 Metal layer forming methods and capacitor electrode forming methods
A capacitor electrode forming method includes chemisorbing a layer of at least one metal precursor at least one monolayer thick on a substrate, the layer...
US-7,104,748 Methods for use with tray-based integrated circuit device handling systems
A stack processing tray for use with tray-based integrated circuit device handling systems. The stack processing tray has a plurality of cells, each cell being...
US-7,103,791 Interleaved delay line for phase locked and delay locked loops
An interleaved delay line for use in phase locked and delay locked loops is comprised of a first portion providing a variable amount of delay substantially...
US-7,103,742 Burst/pipelined edo memory device
An integrated circuit memory device is designed for high speed data access and for compatibility with existing memory systems. An address strobe signal is used...
US-7,103,719 System and method for managing a cache memory
A processing system optimized for data string manipulations includes data string execution circuitry associated with a bus interface unit or memory controller....
US-7,103,682 Apparatus and methods for transmitting data to a device having distributed configuration storage
Systems and methods, for providing distributed configuration storage are presented. The configuration storage is divided into distributed configuration target...
US-7,103,598 Software distribution method and apparatus
The present invention provides for a method and apparatus for distributing digital information, such as software applications, to application users. By providing...
US-7,103,126 Method and circuit for adjusting the timing of output data based on the current and future states of the output...
A clock synchronization circuit receives an input clock signal along with current and future data signals. The clock synchronization circuit generates a phase...
US-7,102,957 Reduction of fusible links and associated circuitry on memory dies
The number of fusible links and other circuit components required to provide memory cell redundancy are reduced by sharing physical memory locations among...
US-7,102,956 Reduction of fusible links and associated circuitry on memory dies
The number of fusible links and other circuit components required to provide memory cell redundancy are reduced by sharing physical memory locations among...
US-7,102,955 Reduction of fusible links and associated circuitry on memory dies
The number of fusible links and other circuit components required to provide memory cell redundancy are reduced by sharing physical memory locations among...
US-7,102,937 Solution to DQS postamble ringing problem in memory chips
The disclosed system and method significantly reduce or eliminate DQS postamble ringing problem in modern high-speed memory chips, allowing the memory chips to...
US-7,102,932 Input and output buffers having symmetrical operating characteristics and immunity from voltage variations
A pair of self-biased differential amplifiers having a non-symmetrical topology are combined to provide a self-biased differential amplifier having a symmetrical...
US-7,102,913 Sensing scheme for programmable resistance memory using voltage coefficient characteristics
A method and apparatus for sensing the resistance state of data in a resistance memory cell by using the voltage coefficient of the cell instead of only its...
US-7,102,907 Wavelength division multiplexed memory module, memory system and method
A computer system includes a controller linked to a plurality of memory modules each of which has an optical memory hub and several memory devices coupled to the...
US-7,102,906 Logic and memory device integration
Memory devices are adapted for direct interface or virtual integration with a processor or other logic device through a local bus and isolated from a system bus....
US-7,102,737 Method and apparatus for automated, in situ material detection using filtered fluoresced, reflected, or...
A method and apparatus for detection of a particular material, such as photo-resist material, on a sample surface are disclosed. A narrow beam of light is...
US-7,102,450 Method and apparatus for providing clock signals at different locations with minimal clock skew
A tapped phase shift ring oscillator may be used to provide multiple clock signals having variable phase delays. Phase delays may be selected to compensate for...
US-7,102,361 Delay lock circuit having self-calibrating loop
A delay lock circuit includes a measuring path, a forward path, and a feedback path. The measuring path samples a pulse with a reference signal in a measurement...
US-7,102,217 Interposer substrates with reinforced interconnect slots, and semiconductor die packages including same
A board-on-chip (BOC) semiconductor package includes a multisegmented, longitudinally slotted interposer substrate through which an elongate row of die bond pads...
US-7,102,191 Memory device with high dielectric constant gate dielectrics and metal floating gates
A memory cell transistor includes a high dielectric constant tunnel insulator, a metal floating gate, and a high dielectric constant inter-gate insulator...
US-7,102,184 Image device and photodiode structure
The invention provides a photodiode with an increased charge collection area, laterally spaced from an adjacent isolation region. Dopant ions of a first...
US-7,102,180 CMOS imager pixel designs
A charge storage capacitor which is connected to various light sensitive and/or electrical elements of a CMOS imager, as well as methods of formation, are...
US-7,102,151 Small electrode for a chalcogenide switching device and method for fabricating same
A memory cell and a method of fabricating the memory cell having a small active area. By forming a spacer in a window that is sized at the photolithographic...
US-7,101,815 Method for improving thickness uniformity of deposited ozone-TEOS silicate glass layers
A method for depositing highly conformal silicate glass layers via chemical vapor deposition through the reaction of TEOS and O.sub.3 is provided, comprising...
US-7,101,814 Masking without photolithography during the formation of a semiconductor device
A method for forming a semiconductor device comprises forming a dielectric layer over a semiconductor wafer substrate assembly having closely-spaced regions,...
US-7,101,813 Atomic layer deposited Zr-Sn-Ti-O films
A dielectric film containing atomic layer deposited Zr--Sn--Ti--O and a method of fabricating such a dielectric film produce a reliable dielectric layer having...
US-7,101,792 Methods of plating via interconnects
Methods for filling high aspect ratio vias with conductive material. At least one high aspect ratio via is formed in the backside of a semiconductor substrate....
US-7,101,779 Method of forming barrier layers
Mixed metal aluminum nitride and boride diffusion barriers and electrodes for integrated circuits, particularly for DRAM cell capacitors. Also provided are...
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