Easy To Use Patents Search & Patent Lawyer Directory

At Patents you can conduct a Patent Search, File a Patent Application, find a Patent Attorney, or search available technology through our Patent Exchange. Patents are available using simple keyword or date criteria. If you are looking to hire a patent attorney, you've come to the right place. Protect your idea and hire a patent lawyer.

Searching: micron





Search by keyword, patent number, inventor, assignee, city or state:




Patent # Description
US-7,075,831 Method for erasing an NROM cell
An operation to erase a nitride read only memory (NROM) memory block starts by erasing the memory block. An erase verify operation can then be performed to...
US-7,075,829 Programmable memory address and decode circuits with low tunnel barrier interpoly insulators
Structures and methods for programmable memory address and decode circuits with low tunnel barrier interpoly insulators are provided. The decoder for a memory...
US-7,075,819 Closed flux magnetic memory
A closed flux magnetic memory cell has a ferromagnetic pinned structure and a ferromagnetic free structure. Data is stored by controlling the relative...
US-7,075,816 Quad flat no-lead (QFN) grid array package, method of making and memory module and computer system including same
A quad flat no-lead (QFN) grid array semiconductor package and method for making the same is disclosed. The package includes a semiconductor die and a lead frame...
US-7,075,808 Method for bus capacitance reduction
Data bus capacitance is reduced by decoupling unaccessed memory circuits from a data bus during data transfers to or from other memory circuits.
US-7,075,763 Methods, circuits, and applications using a resistor and a Schottky diode
A combination of a current limiting resistor and a clamping Schottky diode prevent substantial forward biasing of a pn junction associated with a pad in a...
US-7,075,693 Addressing method of movable elements in a spatial light modulator (SLM)
The present invention relates to a method for modulating at least one pulse of electromagnetic radiation with a spatial light modulator. At least one...
US-7,075,470 Ramp generators for imager analog-to-digital converters
An imager with an analog-to-digital converter having at least one ramp generator that precisely and efficiently produces the desired ramp voltages required by...
US-7,075,330 System and method for balancing capacitively coupled signal lines
A signal balancing circuit for capacitively coupled signaling between transmitting and receiving devices over a plurality of capacitively coupled signal lines on...
US-7,075,173 Interposer including adhesive tape
Two dice may be provided within a single package so that one pin and associated leadfinger may be coupled to bond pads on different dice. This may mean that two...
US-7,075,166 Coating of copper and silver air bridge structures to improve electromigration resistance and other applications
An improved electrical interconnect for an integrated circuit and methods for providing the same are disclosed. The electrical interconnect includes an air...
US-7,075,146 4F.sup.2 EEPROM NROM memory arrays with vertical devices
NROM EEPROM memory devices and arrays are described that facilitate the use of vertical NROM memory cells and select gates in NOR or NAND high density memory...
US-7,075,049 Dual conversion gain imagers
An imager with dual conversion gain floating diffusion regions. The dual conversion gain regions yield (1) high conversion gain and sensitivity to achieve...
US-7,074,724 Etchant and method of use
A method of anisotropiocally etching a semiconductive substrate uses a hydrofluorocarbon etch gas with an etch selectivity fluorocarbon gas. The fluorocarbon gas...
US-7,074,717 Damascene processes for forming conductive structures
A method and apparatus for providing a conductive structure adjacent to a damascene conductive structure in a semiconductor device structure. The semiconductor...
US-7,074,673 Service programmable logic arrays with low tunnel barrier interpoly insulators
Structures and methods for in service programmable logic arrays with low tunnel barrier interpoly insulators are provided. The in-service programmable logic...
US-7,074,648 Method for packaging flip-chip semiconductor assemblies
Flip-chip semiconductor assemblies, each including integrated circuit (IC) dice and an associated substrate, are electrically tested before encapsulation using...
US-7,074,114 Carrier assemblies, polishing machines including carrier assemblies, and methods for polishing micro-device...
Carrier assemblies, polishing machines with carrier assemblies, and methods for mechanical and/or chemical-mechanical polishing of micro-device workpieces are...
US-7,074,113 Methods and apparatus for removing conductive material from a microelectronic substrate
A method and apparatus for removing conductive material from a microelectronic substrate. In one embodiment, a support member supports a microelectronic...
US-7,073,161 Methods of forming patterned reticles
The invention includes methods of forming patterned reticles. Design features can be introduced into a layout for a reticle prior to optical proximity...
US-7,073,039 Providing a register file memory with local addressing in a SIMD parallel processor
A degree of local addressing is provided for a processing element array by partitioning a register file memory (e.g., data columns, data rows), and adding a...
US-7,073,034 System and method for encoding processing element commands in an active memory device
A command engine for an active memory receives high level tasks from a host and generates corresponding sets of either DRAM control unit ("DCU") commands to a...
US-7,073,016 Random access interface in a serial memory device
A random access interface is provided to a non-volatile, serial memory array. An address multiplexer has an external address connection and a serial address...
US-7,073,014 Synchronous non-volatile memory system
A computer system comprises a memory controller and a synchronous non-volatile memory device coupled to the memory controller via a main memory bus. The...
US-7,072,923 Method and apparatus for generating deterministic, non-repeating, pseudo-random addresses
A system and method for rapidly generating a series of non-repeating, deterministic, pseudo-random addresses is disclosed. A deterministic, pseudo-random number...
US-7,072,812 Interpolation error minimization for data reduction
Systems and methods are provided for reducing a set of data points into a subset of best fit data points. According to one aspect, a method of adjusting a series...
US-7,072,433 Delay locked loop fine tune
A digital delay locked loop (DLL) includes a coarse delay segment and fine delay segment. The coarse delay segment includes a coarse delay range. The fine delay...
US-7,072,237 Method and system for low power refresh of dynamic random access memories
A method and system for operating a DRAM device in either a high power, full density mode or a low power, half density mode. In the full density mode, each data...
US-7,072,235 Bias sensing in DRAM sense amplifiers through coupling and decoupling device
Voltage coupling/decoupling devices are provided within DRAM devices for improving the bias sensing of sense amplifiers and thus the refresh performance. The...
US-7,072,231 Reduced power registered memory module and method
A registered memory module includes a plurality of flip-flops having respective data terminals, respective clock terminals receiving a clock signal and output...
US-7,072,230 Method and apparatus for standby power reduction in semiconductor devices
A word line driver circuit for a semiconductor memory device. One or more transistors in the driver circuit are fabricated such that they are susceptible, under...
US-7,072,223 Asymmetric band-gap engineered nonvolatile memory device
Systems and methods are provided for nonvolatile memory devices that incorporate a band-gap engineered gate stack with asymmetric tunnel barriers. One embodiment...
US-7,072,217 Multi-state memory cell with asymmetric charge trapping
A multi-state NAND memory cell is comprised of two drain/source areas in a substrate. An oxide-nitride-oxide structure is formed above the substrate between the...
US-7,072,213 NROM flash memory cell with integrated DRAM
A memory device that is comprised of a dynamic random access memory (DRAM) capacitor and a nitride read only memory (NROM) transistor. The memory device provides...
US-7,072,209 Magnetic memory having synthetic antiferromagnetic pinned layer
A magnetic memory element includes a sense structure, a tunnel barrier adjacent the sense structure, and a synthetic antiferromagnet (SAF) adjacent the tunnel...
US-7,072,090 Addressing of an SLM
The present invention relates to a method to reduce charging effects affecting a degree of movement of at least one movable micro mirror in a spatial light...
US-7,071,946 Accelerated graphics port for a multiple memory controller computer system
An architecture for storing, addressing and retrieving graphics data from one of multiple memory controllers. In a first embodiment of the invention, one of the...
US-7,071,824 Radio frequency identification devices, remote communication devices, identification systems, communication...
The present invention provides radio frequency identification devices, remote communication devices, identification systems, communication methods, and...
US-7,071,770 Low supply voltage bias circuit, semiconductor device, wafer and system including same, and method of...
A bias generator and a method of generating a bias reference are disclosed. A reference transistor is connected in a diode configuration. An n-channel transistor...
US-7,071,730 Voltage level translator circuitry
Circuitry and methods for implementing voltage level translators at relatively low source voltages are provided. The circuitry and methods utilize voltage...
US-7,071,558 Agglomeration control using early transition metal alloys
Structures and methods of fabricating portions of integrated circuit devices to reduce agglomeration tendencies of high surface-energy metals used in...
US-7,071,557 Metallization structures for semiconductor device interconnects, methods for making same, and semiconductor...
The present invention provides a metallization structure for semiconductor device interconnects such as a conductive line, and methods for making the same,...
US-7,071,542 Lead frame decoupling capacitor, semiconductor device packages including the same and methods
A lead frame includes at least two layers, each of which includes an electrically conductive bus and a group of leads that extend substantially unidirectionally...
US-7,071,534 Antifuse structure and method of use
An antifuse structure and method of use are disclosed. According to one embodiment of the present invention a first programming voltage is coupled to a well of a...
US-7,071,531 Trench isolation for semiconductor devices
A method of fabricating an integrated circuit includes forming an isolation trench in a semiconductor substrate and partially filling the trench with a...
US-7,071,508 Capacitor constructions, semiconductor constructions, and methods of forming electrical contacts and...
The invention includes a method of forming a semiconductor construction. A semiconductor substrate is provided, and a conductive node is formed to be supported...
US-7,071,505 Method and apparatus for reducing imager floating diffusion leakage
An imager having reduced floating diffusion leakage and a mechanism for improving the storing of collected charge is described. A polysilicon contact is provided...
US-7,071,421 Stacked microfeature devices and associated methods
Stacked microfeature devices and associated methods of manufacture are disclosed. A package in accordance with one embodiment includes first and second...
US-7,071,420 Methods and apparatus for a flexible circuit interposer
A flexible circuit interposer includes a flexible circuit substrate which allows in-situ probing of an attached device during, for example, circuit debugging,...
US-7,071,120 Method for producing water for use in manufacturing semiconductors
Disclosed is a process of treating semiconductor substrates, including the production of pure water, a method of producing the pure water for semiconductor...
← Previous | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 | Next →

File A Patent Application

  • Protect your idea -- Don't let someone else file first. Learn more.

  • 3 Easy Steps -- Complete Form, application Review, and File. See our process.

  • Attorney Review -- Have your application reviewed by a Patent Attorney. See what's included.