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Patent # Description
US-7,071,012 Methods relating to the reconstruction of semiconductor wafers for wafer-level processing
Methods relating to the reconstruction of semiconductor wafers for wafer-level processing are disclosed. Selected semiconductor dice having alignment cavities...
US-7,070,659 System for filling openings in semiconductor products
Explosive forces are used to fill interconnect material into trenches, via holes and other openings in semiconductor products. The interconnect material may be...
US-7,070,478 Systems and methods for monitoring characteristics of a polishing pad used in polishing micro-device workpieces
Systems and methods for monitoring characteristics of a polishing pad used in polishing a micro-device workpiece are disclosed herein. In one embodiment, a...
US-7,069,638 Air socket for testing integrated circuits
An electrical component testing device comprising a housing having at least one recess covered by a flexible membrane so as to form a chamber. A fluid passage...
US-7,069,484 System for optimizing anti-fuse repair time using fuse id
A method and apparatus for testing semiconductor memory chips, such as DRAMs, having a plurality of memory cells or bits. Each memory chip has a unique...
US-7,069,416 Method for forming a single instruction multiple data massively parallel processor system on a chip
A single chip active memory includes a plurality of memory stripes, each coupled to a full word interface and one of a plurality of processing element (PE)...
US-7,069,377 Scratch control memory array in a flash memory device
A memory device has a scratch control array of non-volatile memory cells that is separate from the primary array of memory cells. The scratch control array...
US-7,068,563 Compact decode and multiplexing circuitry for a multi-port memory having a common memory interface
A memory array for a multi-port memory having a common memory interface and a plurality of memory ports through which the memory array is accessed is provided....
US-7,068,560 High speed low voltage driver
A high speed high and low voltage driver provides an output voltage without taxing a pumped voltage. The pumped voltage is used only when the output node has...
US-7,068,544 Flash memory with low tunnel barrier interpoly insulators
Structures and methods for Flash memory with low tunnel barrier intergate insulators are provided. The non-volatile memory includes a first source/drain region...
US-7,068,543 Flash memory
Flash memory supporting methods for erasing memory cells using a decrease in magnitude of a source voltage of a first polarity to increase the magnitude of a...
US-7,068,527 Match line sensing amplifier for content addressable memory
A method and apparatus for sensing a state of a memory circuit, in particular a content address memory (CAM) device are described. The method includes receiving...
US-7,068,432 Controlling lens shape in a microlens array
A semi-conductor based imager includes a microlens array having microlenses with modified focal characteristics. The microlenses are made of a microlens...
US-7,068,319 CMOS image sensor with a low-power architecture
A system of reducing power consumption in and active pixels sensor. The sensor is broken into different blocks, and each of the blocks is individually optimized....
US-7,068,085 Method and apparatus for characterizing a delay locked loop
A delay locked loop includes a forward path, a feedback path, a phase detector, logic, and a dither circuit. The forward path includes a delay line configured to...
US-7,067,984 Method and apparatuses for providing uniform electron beams from field emission displays
The invention includes field emitters, field emission displays (FEDs), monitors, computer systems and methods employing the same for providing uniform electron...
US-7,067,924 Nickel bonding cap over copper metalized bondpads
A method for forming a nickel cap layer over copper metalized bond pad is disclosed in which the phosphorous content of the nickel cap, and particularly the...
US-7,067,905 Packaged microelectronic devices including first and second casings
The present invention is directed toward methods and apparatuses for encapsulating a microelectronic die or another type of microelectronic device. One aspect of...
US-7,067,901 Semiconductor devices including protective layers on active surfaces thereof
A stereolithographic method of applying material to form a protective layer on a preformed semiconductor die with a high degree of precision, either in the wafer...
US-7,067,894 Semiconductor devices using anti-reflective coatings
Techniques are disclosed for fabricating a device using a photolithographic process. The method includes providing a first anti-reflective coating over a surface...
US-7,067,880 Transistor gate structure
The present invention teaches a method of forming a MOSFET transistor having a silicide gate which is not subject to problems produced by etching a metal...
US-7,067,861 Device and method for protecting against oxidation of a conductive layer in said device
In a semiconductor device including a first conductive layer, the first conductive layer is treated with a nitrogen/hydrogen plasma before an additional layer is...
US-7,067,466 Cleaning composition useful in semiconductor integrated circuit fabrication
A composition for use in semiconductor processing wherein the composition comprises water, phosphoric acid, and an organic acid; wherein the organic acid is...
US-7,067,465 Cleaning composition useful in semiconductor integrated circuit fabricating
A composition for use in semiconductor processing wherein the composition comprises water, phosphoric acid, and an organic acid; wherein the organic acid is...
US-7,067,442 Method to avoid threshold voltage shift in thicker dielectric films
A method of fabricating an integrated circuit having reduced threshold voltage shift is provided. A nonconducting region is formed on the semiconductor substrate...
US-7,067,438 Atomic layer deposition method of forming an oxide comprising layer on a substrate
This invention includes atomic layer deposition methods of depositing oxide comprising layers on substrates. In one implementation, a substrate is positioned...
US-7,067,429 Processing method of forming MRAM circuitry
A method of forming integrated circuitry includes chemical vapor depositing a silicon carbide comprising layer over a substrate at a temperature of no greater...
US-7,067,426 Semiconductor processing methods
The invention includes methods of forming patterns in low-k dielectric materials by contact lithography. In a particular application, a mold having a first...
US-7,067,421 Multilevel copper interconnect with double passivation
Structures and methods provide multilevel wiring interconnects in an integrated circuit assembly which alleviate problems associated with integrated circuit size...
US-7,067,416 Method of forming a conductive contact
Conductive contacts in a semiconductor structure, and methods for forming the conductive components are provided. The method comprises depositing a conductive...
US-7,067,415 Low k interlevel dielectric layer fabrication methods
A low k interlevel dielectric layer fabrication method includes providing a substrate having integrated circuitry at least partially formed thereon. An oxide...
US-7,067,414 Low k interlevel dielectric layer fabrication methods
A low k inter-level dielectric layer fabrication method includes providing a substrate having integrated circuitry at least partially formed thereon. An...
US-7,067,411 Method to prevent metal oxide formation during polycide reoxidation
A selective spacer to prevent metal oxide formation during polycide reoxidation of a feature such as an electrode and a method for forming the selective spacer...
US-7,067,385 Support for vertically oriented capacitors during the formation of a semiconductor device
A method for forming double-sided capacitors for a semiconductor device includes forming a dielectric structure which supports capacitor bottom plates during...
US-7,067,378 Methods of fabricating multiple sets of field effect transistors
The invention includes methods of fabricating multiple sets of field effect transistors. In one implementation, an etch stop layer is formed over an insulative...
US-7,067,348 Method of forming a programmable memory cell and chalcogenide structure
A first conductive electrode material is formed on a substrate. Chalcogenide comprising material is formed thereover. The chalcogenide material comprises...
US-7,066,792 Shaped polishing pads for beveling microfeature workpiece edges, and associate system and methods
Systems and methods for beveling microfeature workpiece edges are disclosed. A system in accordance with one embodiment is configured to remove material from a...
US-7,066,791 Method and apparatus for chemical-mechanical planarization of microelectronic substrates with a carrier and...
A method and apparatus for planarizing a microelectronic substrate. In one embodiment, the apparatus can include a membrane formed from a compressible, flexible...
US-7,066,790 Chemical-mechanical polishing methods
A chemical-mechanical polishing (CMP) method includes applying a solid abrasive material to a substrate, polishing the substrate, flocculating at least a portion...
US-7,066,708 Methods and apparatus for retaining a tray stack having a plurality of trays for carrying microelectric devices
Devices and methods for holding a tray stack having a plurality of trays configured to carry and store microelectronic devices. Several devices in accordance...
US-7,065,868 Methods for installing a circuit device
A method is provided for installing circuit components, such as memory devices, in a support, such as a socket. The device to be installed is supported in a...
US-7,065,682 Method for monitoring tests run on a personal computer
The invention comprises, in various embodiments, a method for monitoring an internal test on a remote computer. The method includes reading a line from the...
US-7,065,666 Apparatus and method for generating a delayed clock signal
An apparatus and method for generating a delayed clock signal is provided. The clock signal generator includes a synchronizing circuit for generating an output...
US-7,065,600 Method of providing an interface to a plurality of peripheral devices using bus adapter chips
A method of electrically coupling a central processing unit (CPU) of a network server to a plurality of network interface modules. The method comprises providing...
US-7,065,001 Method and apparatus for initialization of read latency tracking circuit in high-speed DRAM
A method of synchronizing counters in two different clock domains within a memory device is comprised of generating a start signal for initiating production of a...
US-7,064,992 Method and apparatus for saving current in a memory device
A memory device is configured to conserve electrical current by disabling the address lines provided to a memory bank when the address is not needed, such as...
US-7,064,984 Circuit and method for reducing leakage current in a row driver circuit in a flash memory during a standby mode...
A row driver receives an input signal and a test mode signal, and is coupled to first and second voltage sources and has an output coupled to a word line. The...
US-7,064,981 NAND string wordline delay reduction
An improved NAND Flash memory and word line selection method has been described, that takes advantage of the asymmetric nature of the word line to word line...
US-7,064,970 Serial transistor-cell array architecture
A memory array architecture suitable for variable resistance memory that mitigates sneak path and associated problems by limiting the number of memory cells...
US-7,064,582 Output buffer strength trimming
Apparatus and methods for adjusting the buffer strength of an output buffer to match its capacitive load use selectively enabled stages of a multiple stage...
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