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Patent # Description
US-7,072,433 Delay locked loop fine tune
A digital delay locked loop (DLL) includes a coarse delay segment and fine delay segment. The coarse delay segment includes a coarse delay range. The fine delay...
US-7,072,237 Method and system for low power refresh of dynamic random access memories
A method and system for operating a DRAM device in either a high power, full density mode or a low power, half density mode. In the full density mode, each data...
US-7,072,235 Bias sensing in DRAM sense amplifiers through coupling and decoupling device
Voltage coupling/decoupling devices are provided within DRAM devices for improving the bias sensing of sense amplifiers and thus the refresh performance. The...
US-7,072,231 Reduced power registered memory module and method
A registered memory module includes a plurality of flip-flops having respective data terminals, respective clock terminals receiving a clock signal and output...
US-7,072,230 Method and apparatus for standby power reduction in semiconductor devices
A word line driver circuit for a semiconductor memory device. One or more transistors in the driver circuit are fabricated such that they are susceptible, under...
US-7,072,223 Asymmetric band-gap engineered nonvolatile memory device
Systems and methods are provided for nonvolatile memory devices that incorporate a band-gap engineered gate stack with asymmetric tunnel barriers. One embodiment...
US-7,072,217 Multi-state memory cell with asymmetric charge trapping
A multi-state NAND memory cell is comprised of two drain/source areas in a substrate. An oxide-nitride-oxide structure is formed above the substrate between the...
US-7,072,213 NROM flash memory cell with integrated DRAM
A memory device that is comprised of a dynamic random access memory (DRAM) capacitor and a nitride read only memory (NROM) transistor. The memory device provides...
US-7,072,209 Magnetic memory having synthetic antiferromagnetic pinned layer
A magnetic memory element includes a sense structure, a tunnel barrier adjacent the sense structure, and a synthetic antiferromagnet (SAF) adjacent the tunnel...
US-7,072,090 Addressing of an SLM
The present invention relates to a method to reduce charging effects affecting a degree of movement of at least one movable micro mirror in a spatial light...
US-7,071,946 Accelerated graphics port for a multiple memory controller computer system
An architecture for storing, addressing and retrieving graphics data from one of multiple memory controllers. In a first embodiment of the invention, one of the...
US-7,071,824 Radio frequency identification devices, remote communication devices, identification systems, communication...
The present invention provides radio frequency identification devices, remote communication devices, identification systems, communication methods, and...
US-7,071,770 Low supply voltage bias circuit, semiconductor device, wafer and system including same, and method of...
A bias generator and a method of generating a bias reference are disclosed. A reference transistor is connected in a diode configuration. An n-channel transistor...
US-7,071,730 Voltage level translator circuitry
Circuitry and methods for implementing voltage level translators at relatively low source voltages are provided. The circuitry and methods utilize voltage...
US-7,071,558 Agglomeration control using early transition metal alloys
Structures and methods of fabricating portions of integrated circuit devices to reduce agglomeration tendencies of high surface-energy metals used in...
US-7,071,557 Metallization structures for semiconductor device interconnects, methods for making same, and semiconductor...
The present invention provides a metallization structure for semiconductor device interconnects such as a conductive line, and methods for making the same,...
US-7,071,542 Lead frame decoupling capacitor, semiconductor device packages including the same and methods
A lead frame includes at least two layers, each of which includes an electrically conductive bus and a group of leads that extend substantially unidirectionally...
US-7,071,534 Antifuse structure and method of use
An antifuse structure and method of use are disclosed. According to one embodiment of the present invention a first programming voltage is coupled to a well of a...
US-7,071,531 Trench isolation for semiconductor devices
A method of fabricating an integrated circuit includes forming an isolation trench in a semiconductor substrate and partially filling the trench with a...
US-7,071,508 Capacitor constructions, semiconductor constructions, and methods of forming electrical contacts and...
The invention includes a method of forming a semiconductor construction. A semiconductor substrate is provided, and a conductive node is formed to be supported...
US-7,071,505 Method and apparatus for reducing imager floating diffusion leakage
An imager having reduced floating diffusion leakage and a mechanism for improving the storing of collected charge is described. A polysilicon contact is provided...
US-7,071,421 Stacked microfeature devices and associated methods
Stacked microfeature devices and associated methods of manufacture are disclosed. A package in accordance with one embodiment includes first and second...
US-7,071,420 Methods and apparatus for a flexible circuit interposer
A flexible circuit interposer includes a flexible circuit substrate which allows in-situ probing of an attached device during, for example, circuit debugging,...
US-7,071,120 Method for producing water for use in manufacturing semiconductors
Disclosed is a process of treating semiconductor substrates, including the production of pure water, a method of producing the pure water for semiconductor...
US-7,071,117 Semiconductor devices and methods for depositing a dielectric film
Embodiments provide methods and apparatuses for chemical vapor depositing a dielectric film, and various structures, devices, and systems, which incorporate...
US-7,071,098 Methods of fabricating interconnects for semiconductor components including a through hole entirely through the...
In one aspect, the invention encompasses a method of fabricating an interconnect for a semiconductor component. A semiconductor substrate is provided, and an...
US-7,071,078 Methods for securing components of semiconductor device assemblies to each other with hybrid adhesive materials
A method for securing two or more semiconductor device components to one another is provided. A hybrid adhesive material, including a pressure-sensitive...
US-7,071,067 Fabrication of integrated devices using nitrogen implantation
A process is provided for forming an isolating nitride film to isolate gate polysilicon of a gate structure. Specifically, the process comprises providing a...
US-7,071,058 Methods of forming capacitors, and methods of forming DRAM circuitry
Capacitors, DRAM circuitry, and methods of forming the same are described. In one embodiment, a capacitor comprises a first container which is joined with a...
US-7,071,056 Method of forming a dual-sided capacitor
A dual-sided HSG capacitor and a method of fabrication are disclosed. A thin native oxide layer is formed between a doped polycrystalline layer and a layer of...
US-7,071,055 Method of forming a contact structure including a vertical barrier structure and two barrier layers
This invention relates to contact structures for use in integrated circuits and methods of fabricating contact structures. In one embodiment, a contact structure...
US-7,071,049 Silicon rich barrier layers for integrated circuit devices
Semiconductor devices and memory cells are formed using silicon rich barrier layers to prevent diffusion of dopants from differently doped polysilicon films to...
US-7,071,043 Methods of forming a field effect transistor having source/drain material over insulative material
In one implementation, a method of forming a field effect transistor includes etching an opening into source/drain area of a semiconductor substrate. The opening...
US-7,071,030 Method of making a flexible substrate with a filler material
A method of adding a thermally conductive, electrically nonconductive filler to a flexible substrate such as a polyimide core. The substrate may be used, for...
US-7,071,021 PCRAM memory cell and method of making same
An inverted PCRAM cell is formed by plating the bottom electrode, made of copper for example, with a conductive material, such as silver. Chalcogenide material...
US-7,071,020 Method of forming an elevated photodiode in an image sensor
The invention provides an elevated photodiode for image sensors and methods of formation of the photodiode. Elevated photodiodes permit a decrease in size...
US-7,071,012 Methods relating to the reconstruction of semiconductor wafers for wafer-level processing
Methods relating to the reconstruction of semiconductor wafers for wafer-level processing are disclosed. Selected semiconductor dice having alignment cavities...
US-7,070,659 System for filling openings in semiconductor products
Explosive forces are used to fill interconnect material into trenches, via holes and other openings in semiconductor products. The interconnect material may be...
US-7,070,478 Systems and methods for monitoring characteristics of a polishing pad used in polishing micro-device workpieces
Systems and methods for monitoring characteristics of a polishing pad used in polishing a micro-device workpiece are disclosed herein. In one embodiment, a...
US-7,069,638 Air socket for testing integrated circuits
An electrical component testing device comprising a housing having at least one recess covered by a flexible membrane so as to form a chamber. A fluid passage...
US-7,069,484 System for optimizing anti-fuse repair time using fuse id
A method and apparatus for testing semiconductor memory chips, such as DRAMs, having a plurality of memory cells or bits. Each memory chip has a unique...
US-7,069,416 Method for forming a single instruction multiple data massively parallel processor system on a chip
A single chip active memory includes a plurality of memory stripes, each coupled to a full word interface and one of a plurality of processing element (PE)...
US-7,069,377 Scratch control memory array in a flash memory device
A memory device has a scratch control array of non-volatile memory cells that is separate from the primary array of memory cells. The scratch control array...
US-7,068,563 Compact decode and multiplexing circuitry for a multi-port memory having a common memory interface
A memory array for a multi-port memory having a common memory interface and a plurality of memory ports through which the memory array is accessed is provided....
US-7,068,560 High speed low voltage driver
A high speed high and low voltage driver provides an output voltage without taxing a pumped voltage. The pumped voltage is used only when the output node has...
US-7,068,544 Flash memory with low tunnel barrier interpoly insulators
Structures and methods for Flash memory with low tunnel barrier intergate insulators are provided. The non-volatile memory includes a first source/drain region...
US-7,068,543 Flash memory
Flash memory supporting methods for erasing memory cells using a decrease in magnitude of a source voltage of a first polarity to increase the magnitude of a...
US-7,068,527 Match line sensing amplifier for content addressable memory
A method and apparatus for sensing a state of a memory circuit, in particular a content address memory (CAM) device are described. The method includes receiving...
US-7,068,432 Controlling lens shape in a microlens array
A semi-conductor based imager includes a microlens array having microlenses with modified focal characteristics. The microlenses are made of a microlens...
US-7,068,319 CMOS image sensor with a low-power architecture
A system of reducing power consumption in and active pixels sensor. The sensor is broken into different blocks, and each of the blocks is individually optimized....
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