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Patent # Description
US-7,093,227 Methods of forming patterned reticles
The invention includes methods of forming patterned reticles. Design features can be introduced into a layout for a reticle prior to optical proximity...
US-7,093,173 Synchronous flash memory with test code input
A synchronous non-volatile memory device has address input connections and data input/output connections. A test operation can be initiated that use signals...
US-7,093,098 Multi-drive virtual mass storage device and method of operating same
A virtual mass storage device implements a data manager for storing information on multiple physical mass storage devices. The virtual mass storage device is...
US-7,093,095 Double data rate scheme for data output
Systems, devices, and methods for a double data rate memory device includes a storage element, a first pipeline, and a second pipeline. The pipelines are...
US-7,093,093 Cache management system
A processing system optimized for data string manipulations includes data string execution circuitry associated with a bus interface unit or memory controller....
US-7,093,066 Method for bus capacitance reduction
Data bus capacitance is reduced by decoupling unaccessed memory circuits from a data bus during data transfers to or from other memory circuits.
US-7,093,062 Flash memory data bus for synchronous burst read page
Memory device is described that utilizes a reduced number of sense amplifiers to sense the data bits of a selected column page. The sense amplifiers are...
US-7,092,312 Pre-emphasis for strobe signals in memory device
A memory device has a number of data terminals for transferring data signals and a number of strobe terminals for transferring strobe signals representing timing...
US-7,092,285 State save-on-power-down using GMR non-volatile elements
The semiconductor industry seeks to reduce the risk of traditional volatile storage devices with improved non-volatile storage devices. The increased demand for...
US-7,092,271 CAM memory architecture and a method of forming and operating a device according to a CAM memory architecture
A method for operating a content addressable memory that includes receiving a first data value for evaluation at a first memory block during a first time...
US-7,092,234 DRAM cells and electronic systems
The invention includes capacitor constructions which have a layer of aluminum oxide between a high-k dielectric material and a layer containing titanium and...
US-7,092,233 Capacitor electrode having an interface layer of different chemical composition formed on a bulk layer
An improved capacitor that is less susceptible to the depletion effect and methods for providing the same. The capacitor comprises a first and second electrode...
US-7,092,021 Frame shuttering scheme for increased frame rate
A frame shutter apparatus comprising a controller for controlling multiple groups of pixels and for reading out values corresponding to the charge collected by...
US-7,091,828 Interrogators, methods of operating a coherent interrogator, backscatter communication methods, interrogation...
The present invention includes phase shifters, interrogators, methods of shifting a phase angle of a signal, and methods of operating an interrogator. One aspect...
US-7,091,654 Field emission tips, arrays, and devices
A method for fabricating field emitters from a conductive or semiconductive substrate. A layer of low work function material may be formed on the substrate....
US-7,091,622 Semiconductor device, ball grid array connection system, and method of making
A semiconductor device is provided with a metal stiffening layer between the die and a multilayer structure comprising at least two insulating layers each having...
US-7,091,611 Multilevel copper interconnects with low-k dielectrics and air gaps
Structures and methods are provided for an improved multilevel wiring interconnect in an integrated circuit assembly. The present invention provides for a...
US-7,091,584 Semiconductor package assembly and method for electrically isolating modules
A semiconductor package assembly and method for electrically isolating modules, having a capacitor within the semiconductor package assembly. The package...
US-7,091,575 Open pattern inductor
The invention includes a stacked open pattern inductor fabricated above a semiconductor substrate. The stacked open pattern inductor includes a plurality of...
US-7,091,549 Programmable memory devices supported by semiconductor substrates
The invention includes a memory device supported by a semiconductor substrate and comprising in ascending order from the substrate: a floating gate, a dielectric...
US-7,091,536 Isolation process and structure for CMOS imagers
A barrier implanted region of a first conductivity type located below an isolation region of a pixel sensor cell and spaced from a doped region of a second...
US-7,091,531 High dynamic range pixel amplifier
A pixel cell with increased dynamic range is formed by providing a floating diffusion region having a variable capacitance, controlled by at least one gate...
US-7,091,513 Cathode assemblies
In one aspect, the invention encompasses a method of treating the end portions of an array of substantially upright silicon-comprising structures. A substrate...
US-7,091,466 Apparatus and method for pixel binning in an image sensor
Embodiments provide structures and methods for binning pixel signals of a pixel array. Pixel signals for pixels in an element of the array are binned...
US-7,091,131 Method of forming integrated circuit structures in silicone ladder polymer
A method of forming integrated circuit structures, such as capacitors and conductive plugs, within contact openings formed in a photosensitive silicone ladder...
US-7,091,124 Methods for forming vias in microelectronic devices, and methods for packaging microelectronic devices
Microelectronic devices, methods for packaging microelectronic devices, and methods for forming vias and conductive interconnects in microfeature workpieces and...
US-7,091,113 Methods of forming semiconductor constructions
The invention includes a semiconductor construction having a pair of channel regions that have sub-regions doped with indium and surrounded by boron. A pair of...
US-7,091,101 Method of forming a device
A method of forming a device is disclosed. The method includes forming a capacitor, and forming the capacitor includes forming a first electrode. The first...
US-7,091,087 Optimized flash memory cell
A flash memory comprising floating gate devices being connected to one-another through their source electrodes being self-aligned to their respective gate...
US-7,091,085 Reduced cell-to-cell shorting for memory arrays
Bottom electrodes of memory cell capacitors are recessed to prevent electrical shorts between neighboring memory cells. A partially fabricated memory cell...
US-7,091,067 Current limiting antifuse programming path
Method and apparatus are disclosed for regulating an antifuse programming current by lightly doping an electrically connected region so that the resistance of...
US-7,091,065 Method of making a center bond flip chip semiconductor carrier
A center bond flip chip device carrier and a method for making and using it are described. The carrier includes a flexible substrate supporting a plurality of...
US-7,091,064 Method and apparatus for attaching microelectronic substrates and support members
A microelectronic package and method for forming such packages. In one embodiment, the package can be formed by providing a support member having a first...
US-7,091,061 Method of forming a stack of packaged memory dice
A stacked assembly of integrated circuit semiconductor devices includes a stack of integrated circuit semiconductor devices supported by a printed circuit board...
US-7,091,060 Circuit and substrate encapsulation methods
A ball grid array assembly includes a package cover that encapsulates a die and a portion of a substrate to which the die is attached, including an edge of the...
US-7,091,059 Method of forming a photosensor comprising a plurality of trenches
A method of forming a multiple-trench photosensor for use in a CMOS imager having an improved charge capacity. The multi-trench photosensor may be either a...
US-7,090,815 Nanometer engineering of metal-support catalysts
A method of forming a catalyst body by forming a first layer of hemispherical grain polysilicon over a substrate, and oxidizing at least a portion of the first...
US-7,090,750 Plating
An apparatus and method for treating a substrate to deposit, clean or etch material on a substrate using a first horizontal chuck to which a plurality of...
US-7,090,727 Heated gas line body feedthrough for vapor and gas delivery systems and methods for employing same
A feedthrough device for use in deposition chambers such as chemical vapor deposition chambers and atomic layer deposition chambers and methods using the same in...
US-7,089,449 Recovering a system that has experienced a fault
A method and system of recovering a system that has experienced a fault includes a backup device to enable access of a network through the interface in response...
US-7,089,438 Circuit, system and method for selectively turning off internal clock drivers
The present invention includes a circuit, system and method for selectively turning off internal clock drivers to reduce operating current. The present invention...
US-7,089,375 Device and method for configuring a cache tag in accordance with burst length
In a cache tag integrated on an SRAM with a memory cache, laser fuses are programmed to indicate which, if any, tag subarrays in the cache tag are not...
US-7,089,352 CAM modified to be used for statistic calculation in network switches and routers
A content addressable memory (CAM) device includes a plurality of entries each having an associated counter. When a CAM entry matches a search word stored in the...
US-7,088,625 Distributed write data drivers for burst access memories
An address strobe latches a first address. A burst cycle increments the address internally with additional address strobes. A new memory address is only required...
US-7,088,619 Method for programming and erasing an NROM cell
A nitride read only memory (NROM) cell can be programmed by applying a ramp voltage to the gate input, a constant voltage to one of the two source/drain regions,...
US-7,088,604 Multi-bank memory
A multi-bank memory device includes rows and columns of memory cores. Each row includes memory cores from one bank interleaved with memory cores from another...
US-7,088,603 DRAM CAM memory
A CAM device combines a folded bit line architecture with a standard six transistor DRAM based CAM cell and includes a sensing scheme where the active and...
US-7,088,590 Soldermask opening to prevent delamination
A multilayer circuit board includes a base layer, a conductive layer and a soldermask. The soldermask layer has two sets of openings. One of the openings are...
US-7,088,468 Data-conversion method for a multibeam laser writer for very complex microlithographic patterns
The invention relates to microlithography, in particular to the writing of photomasks for computer displays, microelectronic devices, and precision photoetching....
US-7,088,394 Charge mode active pixel sensor read-out circuit
An apparatus such as an imager includes groups of sensors each of which includes subgroups of sensors. Subgroup select circuits are coupled to outputs from...
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