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Patent # Description
US-7,059,491 Apparatus and method for observing chemical substances
An apparatus and method for observing a chemical substance. In one embodiment, the apparatus includes a vessel having a base portion and an at least partially...
US-7,059,267 Use of pulsed grounding source in a plasma reactor
A method for grounding a semiconductor substrate pedestal during a portion of a high voltage power bias oscillation cycle to reduce or eliminate the detrimental...
US-RE39,126 Two-step chemical mechanical polishing process for producing flush and protruding tungsten plugs
A method for forming conductive plugs within an insulation material is described. The inventive process results in a plug of a material such as tungsten which is...
US-7,058,849 Use of non-volatile memory to perform rollback function
A mechanism and method for maintaining a consistent state in a non-volatile random access memory system without constraining normal computer operation is...
US-7,058,799 Apparatus and method for clock domain crossing with integrated decode
An apparatus and method for transferring signals between timing domains. The apparatus includes a receiver for receiving signals operative in a first timing...
US-7,058,778 Memory controllers having pins with selectable functionality
Systems and methods for selecting pin functionality in memory controllers are provided. These memory controllers have pins that can be used to drive different...
US-7,058,533 Calibration of memory circuits
Memory circuits are calibrated by adjusting memory circuit output parameters based on data eye measurements. Data eye patterns of memory circuit outputs are...
US-7,057,945 Non-volatile memory erase circuitry
A non-volatile memory device includes floating gate memory cells, a pulse counter and voltage pump control circuitry. The control circuitry selectively activates...
US-7,057,935 Erase verify for non-volatile memory
A memory device verify system determines a state of memory cells in a memory. The memory includes a memory array having a plurality of memory cells coupled to...
US-7,057,933 Non-volatile memory device with erase address register
A non-volatile memory device includes an array of non-volatile memory cells. The memory has control circuitry to erase the non-volatile memory cells and perform...
US-7,057,932 Flash memory
Flash memory supporting methods for erasing memory cells using a decrease in magnitude of a source voltage of a first polarity to increase the magnitude of a...
US-7,057,623 Texture addressing circuit and method
A texture addressing circuit and method for calculating texture coordinates according to various texture addressing modes for texture maps having arbitrary...
US-7,057,429 Method and apparatus for digital phase generation at high frequencies
An apparatus and method for generating phase related clocks, includes delaying a clock input by a cycle delay magnitude to generate a cycle delay signal and N...
US-7,057,416 Enhanced protection for input buffers of low-voltage flash memories
An input buffer is discussed that inhibits semiconductor breakdown of thin gate-oxide transistors in low-voltage integrated circuits. One aspect of the input...
US-7,057,373 Battery-powered electronic device with spaced contact extensions
Battery mounting and testing apparatuses and methods of forming the same are described. In one implementation, a substrate includes a surface area over which a...
US-7,057,297 Tape substrates with mold gate support structures that are coplanar with conductive traces thereof and...
A mold gate of a tape substrate includes an aperture formed in the flexible dielectric film of the tape substrate and a support element which is carried by a...
US-7,057,291 Methods for securing vertically mountable semiconductor devices in back-to back relation
A method for assembling vertically mountable semiconductor devices includes positioning the semiconductor devices so that backsides thereof face one another and...
US-7,057,289 Etch stop in damascene interconnect structure and method of making
An interconnect structure with a plurality of low dielectric constant insulating layers acting as etch stops is disclosed. The low dielectric constant materials...
US-7,057,285 Aluminum interconnects with metal silicide diffusion barriers
An aluminum interconnect which extends adjacent to and is insulated from a stacked capacitor structure to facilitate electrical communication between an active...
US-7,057,281 Microelectronic component assemblies employing lead frames having reduced-thickness inner lengths
The present disclosure suggests various microelectronic component assembly designs and methods for manufacturing microelectronic component assemblies. In one...
US-7,057,263 Semiconductor wafer assemblies comprising photoresist over silicon nitride materials
In one aspect, the invention includes a semiconductor processing method, comprising: a) providing a silicon nitride material having a surface; b) forming a...
US-7,057,257 Semiconductor processing methods of forming transistors, semiconductor processing methods of forming dynamic...
Semiconductor processing methods of forming transistors, semiconductor processing methods of forming dynamic random access memory circuitry, and related...
US-7,057,225 Semiconductor memory circuitry
Processes are disclosed which facilitate improved high-density memory circuitry, most preferably dynamic random access memory (DRAM) circuitry. An integrated...
US-7,057,223 Circuit and method for a folded bit line memory cell with vertical transistor and trench capacitor
A memory cell for a memory array in a folded bit line configuration. The memory cell includes an access transistor formed in a pillar of single crystal...
US-7,057,220 Ultrashallow photodiode using indium
The invention provides an imager having a p-n-p photodiode with an ultrashallow junction depth. A p+ junction layer of the photodiode is doped with indium to...
US-7,057,218 Edge intensive antifuse
An antifuse including a bottom plate having a plurality of longitudinal members arranged substantially parallel to a first axis, a dielectric layer formed on the...
US-7,056,833 Methods of filling gaps and methods of depositing materials using high density plasma chemical vapor deposition
The invention includes a method of filling gaps in a semiconductor substrate. A substrate and a gas mixture containing at least one heavy-hydrogen compound are...
US-7,056,823 Backend metallization method and device obtained therefrom
A semiconductor device and a method of making it are described. During the formation of the semiconductor device, a hard mask is formed of an etch-resistant...
US-7,056,812 Process for strengthening semiconductor substrates following thinning
A semiconductor wafer having a high degree of thinness and exhibiting an enhanced strength state. A layer of tenacious reinforcement material is disposed over a...
US-7,056,806 Microfeature workpiece processing apparatus and methods for controlling deposition of materials on microfeature...
The present disclosure provides methods and apparatus useful in depositing materials on batches of microfeature workpieces. One implementation provides a method...
US-7,056,784 Methods of forming capacitors by ALD to prevent oxidation of the lower electrode
A method of forming a capacitor includes forming a conductive metal first electrode layer over a substrate, with the conductive metal being oxidizable to a...
US-7,056,771 Method of forming an array of semiconductor packages
A semiconductor package is provided which includes a substrate having a plurality of semiconductor dice mounted thereon. The substrate is divided into segments...
US-7,056,762 Methods to form a memory cell with metal-rich metal chalcogenide
The invention relates to the fabrication of a resistance variable material cell or programmable metallization cell. The processes described herein can form a...
US-7,056,447 Semiconductor processing methods
Embodiments in accordance with the present invention provide for removing organic materials from substrates, for example substrates employed in the fabrication...
US-7,056,194 Semiconductor processing methods of removing conductive material
The invention includes a semiconductive processing method of electrochemical-mechanical removing at least some of a conductive material from over a surface of a...
US-7,055,241 Method of fabricating an integrated circuit package
A method of forming a semiconductor package is provided. The method includes forming a leadframe wherein the conductors or leads of the leadframe extend from a...
US-7,055,115 Line width check in layout database
A method of performing a design rule check on an integrated circuit includes tagging at least one line in a schematic with a width marker and an associated width...
US-7,055,076 Output data compression scheme using tri-state
A memory device uses data compression to read data from an array of the memory during testing. The compressed data is either a logic one, logic zero or...
US-7,055,012 Latency reduction using negative clock edge and read flags
A method of selecting CAS latencies in a system. Specifically, a system which includes a plurality of memory devices and a memory controller is provided. Because...
US-7,054,992 Synchronous flash memory with non-volatile mode register
A synchronous flash memory includes an array of non-volatile memory cells. The memory device has a package configuration that is compatible with an SDRAM. The...
US-7,054,532 Three-dimensional photonic crystal waveguide structure and method
A waveguide structure formed with a three-dimensional (3D) photonic crystal is disclosed. The 3D photonic crystal comprises a periodic array of voids formed in a...
US-7,054,458 Holder used in the microphone unit
In a microphone having a microphone body stored in a substantially cylindrical metal casing, the casing per se is formed as a ground terminal while a plus...
US-7,054,222 Write address synchronization useful for a DDR prefetch SDRAM
Disclosed herein are exemplary embodiments of an improved write address shift register structure useful for example in a DDR3 DRAM having read/write latency. The...
US-7,054,208 Method and device for testing a sense amp
As part of a memory array, a circuit is provided for altering the drive applied to an access transistor that regulates electrical communication within the memory...
US-7,054,207 Method and system for selecting redundant rows and columns of memory cells
A system and method for selecting redundant rows and columns of memory devices includes a column select steering circuit to couple column select signals from a...
US-7,054,198 Flash memory with fast boot block access
A flash memory device and system include a boot block voltage pump for providing a word line voltage to the boot block of the flash memory. At least one...
US-7,053,987 Methods and systems for controlling radiation beam characteristics for microlithographic processing
Methods and apparatuses for controlling characteristics of radiation directed to a microlithographic workpiece are disclosed. An apparatus in accordance with one...
US-7,053,945 Image sensor having boosted reset
A power supply reset boosting element which boosts a level of the reset voltage to a level higher than the level of the power supply. The boosted voltage is...
US-7,053,899 Animation packager for an on-line book
A system for creating an on-line book with an animated cover. The system includes an animation program for inserting an animation sequence at the beginning of an...
US-7,053,896 Resampling system and method for graphics data including sine-wave components
A method and system for calculating resample output values from input samples and their associated sample values. A resampling circuit calculates a frequency...
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