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Patent # Description
US-7,067,385 Support for vertically oriented capacitors during the formation of a semiconductor device
A method for forming double-sided capacitors for a semiconductor device includes forming a dielectric structure which supports capacitor bottom plates during...
US-7,067,378 Methods of fabricating multiple sets of field effect transistors
The invention includes methods of fabricating multiple sets of field effect transistors. In one implementation, an etch stop layer is formed over an insulative...
US-7,067,348 Method of forming a programmable memory cell and chalcogenide structure
A first conductive electrode material is formed on a substrate. Chalcogenide comprising material is formed thereover. The chalcogenide material comprises...
US-7,066,792 Shaped polishing pads for beveling microfeature workpiece edges, and associate system and methods
Systems and methods for beveling microfeature workpiece edges are disclosed. A system in accordance with one embodiment is configured to remove material from a...
US-7,066,791 Method and apparatus for chemical-mechanical planarization of microelectronic substrates with a carrier and...
A method and apparatus for planarizing a microelectronic substrate. In one embodiment, the apparatus can include a membrane formed from a compressible, flexible...
US-7,066,790 Chemical-mechanical polishing methods
A chemical-mechanical polishing (CMP) method includes applying a solid abrasive material to a substrate, polishing the substrate, flocculating at least a portion...
US-7,066,708 Methods and apparatus for retaining a tray stack having a plurality of trays for carrying microelectric devices
Devices and methods for holding a tray stack having a plurality of trays configured to carry and store microelectronic devices. Several devices in accordance...
US-7,065,868 Methods for installing a circuit device
A method is provided for installing circuit components, such as memory devices, in a support, such as a socket. The device to be installed is supported in a...
US-7,065,682 Method for monitoring tests run on a personal computer
The invention comprises, in various embodiments, a method for monitoring an internal test on a remote computer. The method includes reading a line from the...
US-7,065,666 Apparatus and method for generating a delayed clock signal
An apparatus and method for generating a delayed clock signal is provided. The clock signal generator includes a synchronizing circuit for generating an output...
US-7,065,600 Method of providing an interface to a plurality of peripheral devices using bus adapter chips
A method of electrically coupling a central processing unit (CPU) of a network server to a plurality of network interface modules. The method comprises providing...
US-7,065,001 Method and apparatus for initialization of read latency tracking circuit in high-speed DRAM
A method of synchronizing counters in two different clock domains within a memory device is comprised of generating a start signal for initiating production of a...
US-7,064,992 Method and apparatus for saving current in a memory device
A memory device is configured to conserve electrical current by disabling the address lines provided to a memory bank when the address is not needed, such as...
US-7,064,984 Circuit and method for reducing leakage current in a row driver circuit in a flash memory during a standby mode...
A row driver receives an input signal and a test mode signal, and is coupled to first and second voltage sources and has an output coupled to a word line. The...
US-7,064,981 NAND string wordline delay reduction
An improved NAND Flash memory and word line selection method has been described, that takes advantage of the asymmetric nature of the word line to word line...
US-7,064,970 Serial transistor-cell array architecture
A memory array architecture suitable for variable resistance memory that mitigates sneak path and associated problems by limiting the number of memory cells...
US-7,064,582 Output buffer strength trimming
Apparatus and methods for adjusting the buffer strength of an output buffer to match its capacitive load use selectively enabled stages of a multiple stage...
US-7,064,476 Emitter
Electron emitters and a method of fabricating emitters are disclosed, having a concentration gradient of impurities, such that the highest concentration of...
US-7,064,447 Bond pad structure comprising multiple bond pads with metal overlap
A bond pad structure comprising two bond pads, methods of forming the bond pad structure, an integrated circuit die incorporating the bond pad structure, and...
US-7,064,438 Low-loss coplanar waveguides
Coplanar waveguides having a deep trench between a signal line and a ground plane and methods of their fabrication are disclosed. An oxide layer is provided over...
US-7,064,406 Supression of dark current in a photosensor for imaging
A pixel cell having a halogen-rich region localized between an oxide isolation region and a photosensor. The halogen-rich region prevents leakage from the...
US-7,064,390 Metal gate engineering for surface p-channel devices
A semiconductor device, such as a CMOS device, having gates with a high work function in PMOS regions and low work functions in NMOS regions and a method of...
US-7,064,080 Semiconductor processing method using photoresist and an antireflective coating
A semiconductor processing method includes forming an antireflective coating comprising Ge and Se over a substrate to be patterned. Photoresist is formed over...
US-7,064,069 Substrate thinning including planarization
A method and intermediate structure for improving the thinning and planarity of a wafer back side utilizing planarization material applied to the back side prior...
US-7,064,058 Low-temperature growth high-quality ultra-thin praseodymium gate dieletrics
A praseodymium (Pr) gate oxide and method of fabricating same that produces a high-quality and ultra-thin equivalent oxide thickness as compared to conventional...
US-7,064,052 Method of processing a transistor gate dielectric film with stem
A method of fabricating a semiconductor device includes depositing a dielectric film and subjecting the dielectric film to a wet oxidation in a rapid thermal...
US-7,064,036 Dual-gate transistor device and method of forming a dual-gate transistor device
Embodiments in accordance with the present invention provide methods of forming a dual gated semiconductor-on-insulator (SOI) device. Such methods encompass...
US-7,064,010 Methods of coating and singulating wafers
Separating and coating semiconductor dice at the wafer level to form individual chip-scale packages. In one embodiment, channels are formed in the active surface...
US-7,064,007 Method of using foamed insulators in three dimensional multichip structures
A multichip cube structure having a foamed insulating material disposed between adjacent integrated circuit chips. The foamed insulating material has lower...
US-7,064,006 Multiple die stack apparatus employing T-shaped interposer elements
Multiple integrated circuit devices in a stacked configuration that use a spacing element for allowing increased device density and increased thermal conduction...
US-7,064,002 Method for fabricating interposers including upwardly protruding dams, semiconductor device assemblies...
A dam for substantially laterally confining a quantity of encapsulant material over a region of a substrate, such as an interposer. The dam is configured to...
US-7,063,985 Method for fabricating sensor devices having improved switching properties
The invention provides an magnetic memory element having improved switching properties and zero field offset, and a manufacturing method thereof. The element...
US-7,063,603 Method and apparatus for cleaning a web-based chemical mechanical planarization system
A method and apparatus for cleaning a web-based chemical-mechanical planarization (CMP) system. Specifically, a fluid spray bar is coupled to a frame assembly...
US-7,063,599 Apparatus, systems, and methods for conditioning chemical-mechanical polishing pads
A conditioner includes abrasive elements for conditioning a polishing pad to be used in abrasive semiconductor substrate treatment processes, such as...
US-7,063,595 Method and apparatus for planarizing a microelectronic substrate with a tilted planarizing surface
A method and apparatus for planarizing a microelectronic substrate. In one embodiment, the apparatus can include an elongated, non-continuous polishing pad...
US-7,063,524 Apparatus for increased dimensional accuracy of 3-D object creation
A stereolithographic (STL) apparatus for forming structures such as semiconductor die packages is described which uses a laser beam focused to a generally...
US-7,063,466 Selectable and tunable ferrule holder for a fiber Fabry-Perot filter
The invention relates generally to optical interference filters and interferometers. Methods, devices and device components for fiber Fabry-Perot (FFP) filters...
US-7,062,761 Dynamic arrays and overlays with bounds policies
Systems and methods are provided for writing code to access data arrays. One aspect provides a method of accessing a memory array. Data is provided within a...
US-7,062,599 Flash memory programming
The various embodiments provide for programming floating-gate, or flash, memory devices by writing a block of data words to a volatile storage media from an...
US-7,061,817 Data path having grounded precharge operation and test compression capability
A data path for coupling data between a memory cell and an input/output (IO) line sense amplifier. An IO line coupling circuit is coupled to a pair of global...
US-7,061,811 Faster method of erasing flash memory
An erase operation in a flash memory device includes applying an erase pulse to memory cells of the flash memory device to convert the contents of the memory...
US-7,061,810 Erasing flash memory without pre-programming the flash memory before erasing
An erase operation in a flash memory device includes applying an erase pulse to memory cells of the flash memory device to convert the contents of the memory...
US-7,061,789 Sensing scheme for programmable resistance memory using voltage coefficient characteristics
A method and apparatus for sensing the resistance state of data in a resistance memory cell by using the voltage coefficient of the cell instead of only its...
US-7,061,413 Analog to digital conversion with offset cancellation
An analog to digital conversion circuit includes a voltage-to-charge converter coupled to a charge integrator and a comparator. The voltage-to-charge converter...
US-7,061,306 Voltage booster
Voltage boosters or pass circuits for generating a boosted voltage are advantageous in the decoding and programming of memory devices and, in particular, NAND...
US-7,061,226 Method to detect a defective element
The present invention relates to a method to detect at least one defective pixel in a spatial light modulator comprising numerous pixel elements. The spatial...
US-7,061,124 Solder masks including dams for at least partially surrounding terminals of a carrier substrate and recessed...
A solder mask for use on a carrier substrate includes a device-securing region positionable over at least a portion of a die-support location of the carrier...
US-7,061,119 Tape attachment chip-on-board assemblies
An apparatus and method for preventing damage to tape attachment semiconductor assemblies due to encapsulation filler particles causing damage to a semiconductor...
US-7,061,115 Interconnect line selectively isolated from an underlying contact plug
The present invention relates to selectively electrically connecting an electrical interconnect line, such as a bit line of a memory cell, with an associated...
US-7,061,111 Interconnect structure for use in an integrated circuit
A copper interconnect structure is disclosed as comprising a copper layer and an aluminum nitride layer formed over the copper layer. The aluminum nitride layer...
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