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Patent # Description
US-7,053,775 RFID material tracking method and apparatus
A method and apparatus for tracking items automatically is described. A passive RFID (Radio Frequency IDentification) tag is used with a material tracking system...
US-7,053,650 Communication device for a logic circuit
A circuit is provided to isolate a contact pad from a logic circuit of a die once the contact pad is no longer needed. This circuit can take many forms including...
US-7,053,641 Interconnect having spring contacts
An interconnect for testing a semiconductor component includes a substrate, and interconnect contacts on the substrate configured to electrically engage...
US-7,053,467 Leadframe alteration to direct compound flow into package
A leadframe comprising a downset formed adjacent to an edge of the leadframe so as to direct the molding compound to flow evenly inside the mold cavity. The...
US-7,053,462 Planarization of metal container structures
A conductive material is provided in an opening formed in an insulative material. The process involves first forming a conductive material over at least a...
US-7,053,444 Method and apparatus for a flash memory device comprising a source local interconnect
A method for forming a flash memory device having a local interconnect connecting source regions of a plurality of transistors within a sector allows for a...
US-7,053,432 Enhanced surface area capacitor fabrication methods
A capacitor fabrication method may include forming a first capacitor electrode over a substrate and atomic layer depositing an insulative barrier layer to oxygen...
US-7,053,010 Methods of depositing silicon dioxide comprising layers in the fabrication of integrated circuitry, methods of...
This invention includes methods of depositing silicon dioxide comprising layers in the fabrication of integrated circuitry, methods of forming trench isolation,...
US-7,052,997 Method to form etch and/or CMP stop layers
In a DRAM fabrication process, a first oxide is provided over a transistor gate and over a substrate extending from under the gate. The deposition is...
US-7,052,987 Method for fabricating a low capacitance wiring layout
Integrated circuits having multi-level wiring layouts designed to inhibit the capacitive-resistance effect, and a method for fabricating such integrated...
US-7,052,972 Method for forming sublithographic features during the manufacture of a semiconductor device and a resulting...
A method for forming a semiconductor device comprises forming a layer to be etched, then forming a hard mask layer over the layer to be etched. The hard mask is...
US-7,052,957 Methods of fabricating double-sided hemispherical silicon grain electrodes and capacitor modules
The invention provides robust and cost effective techniques to fabricate a semiconductor device having double-sided hemispherical silicon grain (HSG) electrodes...
US-7,052,953 Dielectric material forming methods and enhanced dielectric materials
A dielectric material forming method includes forming a first monolayer and forming a second monolayer on the first monolayer, one of the first and second...
US-7,052,923 Field emission display with smooth aluminum film
This invention provides a conductive aluminum film and method of forming the same, wherein a non-conductive impurity is incorporated into the aluminum film. In...
US-7,052,922 Stable electroless fine pitch interconnect plating
A method and apparatus for plating facilitates the plating of a small contact feature of a wafer die while providing a relatively stable plating bath. The method...
US-7,052,617 Simplified etching technique for producing multiple undercut profiles
A process for producing multiple undercut profiles in a single material. A resist pattern is applied over a work piece and a wet etch is performed to produce an...
US-7,052,584 Method of forming a capacitor
A method of forming a capacitor having a capacitor dielectric layer comprising ABO.sub.3, where "A" is selected from the group consisting of Sn and Group IIA...
US-7,052,375 Method of making carrier head backing plate having low-friction coating
Planarizing machines, carrier heads for planarizing machines and methods for planarizing microelectronic-device substrate assemblies in mechanical or...
US-7,052,352 Anode screen for a phosphor display and method of making the same
An anode screen for a field-emission-display is formed by layering light-permeable conductive material and phosphor respectively over a transparent substrate. A...
US-7,052,350 Field emission device having insulated column lines and method manufacture
An FED and a method of manufacture are provided. The FED includes a cathode assembly containing an improved column line structure. The column line structure...
US-7,051,741 Reduction/oxidation material removal method
A method of resist stripping for use during fabrication of semiconductor devices. A semiconductor substrate with a resist material formed thereon, such as a...
US-7,051,729 Apparatus and methods for aligning a center of mass with a rotational axis of a shaft or spindle
Centering elements effectively reduce the clearance between a shaft and a rotatable element, such as a blade-fixing flange of a dicing saw for use with...
US-7,051,178 Burst write in a non-volatile memory device
A synchronous flash memory has been described that includes an array of non-volatile memory cells. The memory device has a package configuration that is...
US-7,050,708 Delivery of solid chemical precursors
Systems and methods are provided for delivering solid precursors. In certain embodiments of the present application, a flow monitor is used to measure and...
US-7,050,649 Suppression of ringing artifacts during image resizing
An economical method of detecting and suppressing ringing artifacts during digital image resizing is presented. The economical method substitutes costly division...
US-7,050,425 Apparatus for multiple media digital communication
Apparatus for media communication in a communication system. In one embodiment, the apparatus comprises: a processor; and a routine running on the processor for...
US-7,050,342 Testmode to increase acceleration in burn-in
A method and apparatus for simultaneously accessing multiple array blocks in a static random access memory (SRAM) device. During testing of the SRAM device, each...
US-7,050,330 Multi-state NROM device
An array of NROM flash memory cells configured to store at least two bits per four F.sup.2. Split vertical channels are generated along each side of adjacent...
US-7,050,327 Differential negative resistance memory
The invention relates to a DNR (differential negative resistance) exhibiting device that can be programmed to store information as readable current amplitudes...
US-7,050,319 Memory architecture and method of manufacture and operation thereof
An architecture, and its method of formation and operation, containing a high density memory array of semi-volatile or non-volatile memory elements, including,...
US-7,050,094 Wide dynamic range operation for CMOS sensor with freeze-frame shutter
Wide dynamic range operation is used to write a signal in a freeze-frame pixel into the memory twice, first after short integration and then after long...
US-7,049,861 Reduced current input buffer circuit
There is provided an input buffer circuit that, in one embodiment, includes an input buffer adapted to draw an operating current, a first buffer enabling...
US-7,049,840 Hybrid interconnect and system for testing semiconductor dice
An interconnect is provided for making electrical connections with a semiconductor die. The interconnect includes a substrate having integrally formed contact...
US-7,049,753 Method and apparatuses for providing uniform electron beams from field emission displays
The invention includes field emitters, field emission displays (FEDs), monitors, computer systems and methods employing the same for providing uniform electron...
US-7,049,700 Semiconductor test board having laser patterned conductors
A method for fabricating semiconductor components is performed using a laser scanner and a laser imaging process. A substrate, such as a semiconductor wafer,...
US-7,049,693 Electrical contact array for substrate assemblies
A substrate assembly is disclosed including a substrate and a plurality of spring-biased electrical contacts formed thereon for establishing electrical contact...
US-7,049,685 Packaged microelectronic devices with pressure release elements and methods for manufacturing and using such...
Packaged microelectronic devices, interconnecting units for packaged microelectronic devices, and methods and apparatuses for packaging microelectronic devices...
US-7,049,664 Semiconductor device structures formed by ion-assisted oxidation
Oxidation methods, and resulting structures, comprising providing an oxide layer on a substrate and then re-oxidizing the oxide layer by vertical ion bombardment...
US-7,049,244 Method for enhancing silicon dioxide to silicon nitride selectivity
A process for controlling the plasma etch of a silicon dioxide layer at a high etch rate and high selectivity with respect to silicon nitride, particularly in a...
US-7,049,238 Method for fabricating semiconductor device having recess
A method for forming a floating gate semiconductor device such as an electrically erasable programmable read only memory is provided. The device includes a...
US-7,049,237 Methods for planarization of Group VIII metal-containing surfaces using oxidizing gases
A planarization method includes providing a second and/or third Group VIII metal-containing surface (preferably, a platinum-containing surface) and positioning...
US-7,049,231 Methods of forming capacitors
In but one aspect of the invention, a method of depositing polysilicon comprises providing a substrate within a chemical vapor deposition reactor, with the...
US-7,049,219 Coating of copper and silver air bridge structures to improve electromigration resistance and other applications
An improved electrical interconnect for an integrated circuit and methods for providing the same are disclosed. The electrical interconnect includes an air...
US-7,049,206 Device isolation for semiconductor devices
Exemplary embodiments of the present invention disclose a semiconductor assembly having at least one isolation structure formed. The semiconductor assembly...
US-7,049,196 Vertical gain cell and array for a dynamic random access memory and method for forming the same
A vertical gain memory cell including an n-channel metal-oxide semiconductor field-effect transistor (MOSFET) and p-channel junction field-effect transistor...
US-7,049,192 Lanthanide oxide / hafnium oxide dielectrics
Dielectric layers containing a chemical vapor deposited hafnium oxide and an electron beam evaporated lanthanide oxide and a method of fabricating such a...
US-7,049,191 Method for protecting against oxidation of a conductive layer in said device
In a semiconductor device including a first conductive layer, the first conductive layer is treated with a nitrogen/hydrogen plasma before an additional layer is...
US-7,049,173 Method for fabricating semiconductor component with chip on board leadframe
A semiconductor component includes a chip on board leadframe, a semiconductor die back bonded and wire bonded to the leadframe, an encapsulant on the die and an...
US-7,049,153 Polymer-based ferroelectric memory
Integrated memory circuits, key components in thousands of electronic and computer products, have been made using ferroelectric materials, which offer faster...
US-7,049,009 Silver selenide film stoichiometry and morphology control in sputter deposition
A method of sputter depositing silver selenide and controlling the stoichiometry and nodular defect formations of a sputter deposited silver-selenide film. The...
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