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Patent # Description
US-7,048,968 Methods of depositing materials over substrates, and methods of forming layers over substrates
The invention includes methods of utilizing supercritical fluids to introduce precursors into reaction chambers. In some aspects, a supercritical fluid is...
US-7,047,455 Memory with element redundancy
A memory device to perform an erase operation algorithm that specifically deals with different types of defects in a memory array. The memory array of one...
US-7,047,351 Memory hub bypass circuit and method
A computer system and a method used to access data from a plurality of memory devices with a memory hub. The computer system includes a plurality of memory...
US-7,047,265 System and method for a single-pass multiple tap filter
A system and method for calculating an output value from a plurality of input sample values contributing to the output value in accordance with a respective...
US-7,046,578 Method and apparatus for memory device wordline
A method and apparatus for improving the speed of a wordline in a memory device. A wordline structure includes a main wordline for selectively distributing a...
US-7,046,562 Integrated circuit reset circuitry
An integrated circuit includes a reset connection to reset the device in response to an externally provided signal. The reset connection is used during test...
US-7,046,560 Reduction of fusible links and associated circuitry on memory dies
The number of fusible links and other circuit components required to provide memory cell redundancy are reduced by sharing physical memory locations among...
US-7,046,557 Flash memory
Flash memory devices having control circuitry to decrease the magnitude of a source voltage of a first polarity during an erase period to increase the magnitude...
US-7,046,547 Magnetic non-volatile memory coil layout architecture and process integration scheme
The invention relates to methods and apparatus that allow data to be stored in a magnetic memory cell, such as a giant magneto-resistance (GMR) cell, of a...
US-7,046,538 Memory stacking system and method
A method of forming a stacked memory module from a plurality of memory devices is provided. Each of the plurality of memory devices is modified to include a...
US-7,046,537 Reduced signal swing in bit lines in a CAM
A Content Addressable Memory device with a bit line that is driven between first and second voltage levels depending on the state of a logic signal applied...
US-7,046,536 Programable identification circuitry
An integrated circuit has been described that includes a user programmable identification code register. The register can be programmed by the user to emulate...
US-7,046,340 Method and apparatus for controlling radiation beam intensity directed to microlithographic substrates
A method and apparatus for controlling an intensity distribution of a radiation beam directed to a microlithographic substrate. The method can include directing...
US-7,046,339 Optimized optical lithography illumination source for use during the manufacture of a semiconductor device
A method and structure for optimizing an optical lithography illumination source comprises a shaped diffractive optical element (DOE) interposed between the...
US-7,046,038 Upward and downward pulse stretcher circuits and modules
The invention includes digital logic devices with extremely skewed trip points and reset circuitry for rapidly propagating signal edges. Embodiments of skewed...
US-7,046,029 Conductive material for integrated circuit fabrication
A conductive composition of titanium boronitride (TiB.sub.xN.sub.y) is disclosed for use as a conductive material. The titanium boronitride is used as conductive...
US-7,045,889 Device for establishing non-permanent electrical connection between an integrated circuit device lead element...
A spring contact for establishing electrical contact between a lead element of an IC device and a substrate. The spring contact generally comprises a contact...
US-7,045,880 Method and apparatus on (110) surfaces of silicon structures with conduction in the <110> direction
Improved methods and structures are provided that are lateral to surfaces with a (110) crystal plane orientation such that an electrical current of such...
US-7,045,874 Micromechanical strained semiconductor by wafer bonding
One aspect disclosed herein relates to a method for forming a strained semiconductor structure. In various embodiments of the method, a number of recesses are...
US-7,045,844 Memory cell and method for forming the same
A semiconductor memory cell structure having 4F.sup.2 dimensions and method for forming the same. The memory cell is formed on a surface of a substrate and...
US-7,045,834 Memory cell arrays
A memory device includes memory cells, bit lines, active area lines running generally in parallel to the bit lines, and transistors formed in each active area...
US-7,045,454 Chemical mechanical planarization of conductive material
A process of removing excess conductive material from the exposed surface of a dielectric layer, the process comprising the steps of forming a shield layer on...
US-7,045,449 Methods of forming semiconductor constructions
The invention includes a semiconductor construction having a pair of channel regions that have sub-regions doped with indium and surrounded by boron. A pair of...
US-7,045,439 Methods of forming semiconductor constructions
The invention includes a method of forming a semiconductor construction. A first substrate is provided which comprises silicon-containing structures separated...
US-7,045,430 Atomic layer-deposited LaAlO3 films for gate dielectrics
A dielectric film containing LaAlO.sub.3 and method of fabricating a dielectric film contained LaAlO.sub.3 produce a reliable gate dielectric having a thinner...
US-7,045,405 Semiconductor processing methods of forming integrated circuitry
Semiconductor processing methods of forming integrated circuitry are described. In one embodiment, memory circuitry and peripheral circuitry are formed over a...
US-7,045,277 Semiconductor processing methods of transferring patterns from patterned photoresists to materials, and...
The invention includes a semiconductor processing method. A first material comprising silicon and nitrogen is formed. A second material is formed over the first...
US-7,045,017 Method for post chemical-mechanical planarization cleaning of semiconductor wafers
The inventive method cleans residual titanium accumulations and other undesirable materials from a planarized surface of a wafer to produce a planarized surface...
US-7,044,997 Process byproduct trap, methods of use, and system including same
A trap device including at least one substance delivery element for introducing a substance therein is disclosed. The delivered substance may influence the...
US-7,043,831 Method for fabricating a test interconnect for bumped semiconductor components by forming recesses and...
A method for fabricating an interconnect for semiconductor components includes the steps of: providing a substrate; forming a metal layer on the substrate;...
US-7,043,830 Method of forming conductive bumps
A sealing layer is provided on the surface of a substrate such as a semiconductor wafer. The sealing layer includes apertures which expose external contact...
US-7,043,672 Layout for a semiconductor memory device having redundant elements
The present invention reduces the area on a die required for rows and columns of redundant memory cells by sharing compare circuitry with banks of redundant...
US-7,043,617 System supporting multiple memory modes including a burst extended data out mode
A system is capable of receiving Fast Page mode, Extended Data Out mode, Burst Extended Data Out mode, or a combination of these memory devices. A method of...
US-7,043,388 System and apparatus for testing packaged devices and related methods
A testing system is disclosed for testing a packaged device having a body with a package profile and an array of contacts coupled to the body. In one embodiment,...
US-7,042,778 Flash array implementation with local and global bit lines
A flash memory device that can detect short circuits in local and global bit lines. The flash memory device has a plurality of sets of adjacent local bit lines,...
US-7,042,775 Semiconductor memory with wordline timing
A semiconductor memory with wordline timing, which links activating a wordline to an isolation signal. The isolation signal is applied to a memory section...
US-7,042,768 Flash memory architecture for optimizing performance of memory having multi-level memory cells
A flash memory device having a pipelined RAS/CAS architecture is logically organized as an array of rows and columns of multi-bit flash memory cells each capable...
US-7,042,749 Stacked 1T-nmemory cell structure
This invention relates to memory technology and new variations on memory array architecture to incorporate certain advantages from both cross-point and 1T-1Cell...
US-7,042,358 RFID material tracking method and apparatus
A method and apparatus for tracking items automatically is described. A passive RFID (Radio Frequency IDentification) tag is used with a material tracking system...
US-7,042,265 Interlaced delay-locked loops for controlling memory-circuit timing
For control, some memory circuits use a delay-locked loop to generate a set of signals, each delayed a different amount relative a reference signal. However, as...
US-7,042,260 Low power and low timing jitter phase-lock loop and method
A phase-lock loop generates an output clock signal from an input clock signal. The output clock signal is coupled through a clock tree and is fed back to a phase...
US-7,042,148 Field emission display having reduced power requirements and method
A field emission display includes a substrate and a plurality of emitters formed on columns on the substrate. The display also includes a porous dielectric layer...
US-7,042,080 Semiconductor interconnect having compliant conductive contacts
An interconnect for testing a semiconductor component includes a substrate, and interconnect contacts on the substrate configured to electrically engage...
US-7,042,052 Transistor constructions and electronic devices
The invention includes a non-volatile memory cell comprising a field effect transistor construction having a body region within a crystalline material. The body...
US-7,042,047 Memory cell, array, device and system with overlapping buried digit line and active area and method for forming...
A memory cell, array and device include an active area formed in the substrate with a vertical transistor including a first end disposed over a first portion of...
US-7,042,043 Programmable array logic or memory devices with asymmetrical tunnel barriers
Structures and methods for programmable array type logic and/or memory devices with asymmetrical low tunnel barrier intergate insulators are provided. The...
US-7,042,027 Gated lateral thyristor-based random access memory cell (GLTRAM)
One aspect of the present subject matter relates to a memory cell, or more specifically, to a scalable GLTRAM cell that provides DRAM-like density and SRAM-like...
US-7,042,010 Intermediate semiconductor device having activated oxide-based layer for electroless plating
An intermediate semiconductor device that includes a semiconductor substrate and an oxide-based layer over the substrate. The oxide-based layer has an activated...
US-7,041,609 Systems and methods for forming metal oxides using alcohols
A method of forming (and an apparatus for forming) a metal oxide layer on a substrate, particularly a semiconductor substrate or substrate assembly, using a...
US-7,041,606 Electroless deposition of doped noble metals and noble metal alloys
A method for forming an oxidation barrier including at least partially immersing a semiconductor device structure in an electroless plating bath that includes at...
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