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Patent # Description
US-7,055,012 Latency reduction using negative clock edge and read flags
A method of selecting CAS latencies in a system. Specifically, a system which includes a plurality of memory devices and a memory controller is provided. Because...
US-7,054,992 Synchronous flash memory with non-volatile mode register
A synchronous flash memory includes an array of non-volatile memory cells. The memory device has a package configuration that is compatible with an SDRAM. The...
US-7,054,532 Three-dimensional photonic crystal waveguide structure and method
A waveguide structure formed with a three-dimensional (3D) photonic crystal is disclosed. The 3D photonic crystal comprises a periodic array of voids formed in a...
US-7,054,458 Holder used in the microphone unit
In a microphone having a microphone body stored in a substantially cylindrical metal casing, the casing per se is formed as a ground terminal while a plus...
US-7,054,222 Write address synchronization useful for a DDR prefetch SDRAM
Disclosed herein are exemplary embodiments of an improved write address shift register structure useful for example in a DDR3 DRAM having read/write latency. The...
US-7,054,208 Method and device for testing a sense amp
As part of a memory array, a circuit is provided for altering the drive applied to an access transistor that regulates electrical communication within the memory...
US-7,054,207 Method and system for selecting redundant rows and columns of memory cells
A system and method for selecting redundant rows and columns of memory devices includes a column select steering circuit to couple column select signals from a...
US-7,054,198 Flash memory with fast boot block access
A flash memory device and system include a boot block voltage pump for providing a word line voltage to the boot block of the flash memory. At least one...
US-7,053,987 Methods and systems for controlling radiation beam characteristics for microlithographic processing
Methods and apparatuses for controlling characteristics of radiation directed to a microlithographic workpiece are disclosed. An apparatus in accordance with one...
US-7,053,945 Image sensor having boosted reset
A power supply reset boosting element which boosts a level of the reset voltage to a level higher than the level of the power supply. The boosted voltage is...
US-7,053,899 Animation packager for an on-line book
A system for creating an on-line book with an animated cover. The system includes an animation program for inserting an animation sequence at the beginning of an...
US-7,053,896 Resampling system and method for graphics data including sine-wave components
A method and system for calculating resample output values from input samples and their associated sample values. A resampling circuit calculates a frequency...
US-7,053,775 RFID material tracking method and apparatus
A method and apparatus for tracking items automatically is described. A passive RFID (Radio Frequency IDentification) tag is used with a material tracking system...
US-7,053,650 Communication device for a logic circuit
A circuit is provided to isolate a contact pad from a logic circuit of a die once the contact pad is no longer needed. This circuit can take many forms including...
US-7,053,641 Interconnect having spring contacts
An interconnect for testing a semiconductor component includes a substrate, and interconnect contacts on the substrate configured to electrically engage...
US-7,053,467 Leadframe alteration to direct compound flow into package
A leadframe comprising a downset formed adjacent to an edge of the leadframe so as to direct the molding compound to flow evenly inside the mold cavity. The...
US-7,053,462 Planarization of metal container structures
A conductive material is provided in an opening formed in an insulative material. The process involves first forming a conductive material over at least a...
US-7,053,444 Method and apparatus for a flash memory device comprising a source local interconnect
A method for forming a flash memory device having a local interconnect connecting source regions of a plurality of transistors within a sector allows for a...
US-7,053,432 Enhanced surface area capacitor fabrication methods
A capacitor fabrication method may include forming a first capacitor electrode over a substrate and atomic layer depositing an insulative barrier layer to oxygen...
US-7,053,010 Methods of depositing silicon dioxide comprising layers in the fabrication of integrated circuitry, methods of...
This invention includes methods of depositing silicon dioxide comprising layers in the fabrication of integrated circuitry, methods of forming trench isolation,...
US-7,052,997 Method to form etch and/or CMP stop layers
In a DRAM fabrication process, a first oxide is provided over a transistor gate and over a substrate extending from under the gate. The deposition is...
US-7,052,987 Method for fabricating a low capacitance wiring layout
Integrated circuits having multi-level wiring layouts designed to inhibit the capacitive-resistance effect, and a method for fabricating such integrated...
US-7,052,972 Method for forming sublithographic features during the manufacture of a semiconductor device and a resulting...
A method for forming a semiconductor device comprises forming a layer to be etched, then forming a hard mask layer over the layer to be etched. The hard mask is...
US-7,052,957 Methods of fabricating double-sided hemispherical silicon grain electrodes and capacitor modules
The invention provides robust and cost effective techniques to fabricate a semiconductor device having double-sided hemispherical silicon grain (HSG) electrodes...
US-7,052,953 Dielectric material forming methods and enhanced dielectric materials
A dielectric material forming method includes forming a first monolayer and forming a second monolayer on the first monolayer, one of the first and second...
US-7,052,923 Field emission display with smooth aluminum film
This invention provides a conductive aluminum film and method of forming the same, wherein a non-conductive impurity is incorporated into the aluminum film. In...
US-7,052,922 Stable electroless fine pitch interconnect plating
A method and apparatus for plating facilitates the plating of a small contact feature of a wafer die while providing a relatively stable plating bath. The method...
US-7,052,617 Simplified etching technique for producing multiple undercut profiles
A process for producing multiple undercut profiles in a single material. A resist pattern is applied over a work piece and a wet etch is performed to produce an...
US-7,052,584 Method of forming a capacitor
A method of forming a capacitor having a capacitor dielectric layer comprising ABO.sub.3, where "A" is selected from the group consisting of Sn and Group IIA...
US-7,052,375 Method of making carrier head backing plate having low-friction coating
Planarizing machines, carrier heads for planarizing machines and methods for planarizing microelectronic-device substrate assemblies in mechanical or...
US-7,052,352 Anode screen for a phosphor display and method of making the same
An anode screen for a field-emission-display is formed by layering light-permeable conductive material and phosphor respectively over a transparent substrate. A...
US-7,052,350 Field emission device having insulated column lines and method manufacture
An FED and a method of manufacture are provided. The FED includes a cathode assembly containing an improved column line structure. The column line structure...
US-7,051,741 Reduction/oxidation material removal method
A method of resist stripping for use during fabrication of semiconductor devices. A semiconductor substrate with a resist material formed thereon, such as a...
US-7,051,729 Apparatus and methods for aligning a center of mass with a rotational axis of a shaft or spindle
Centering elements effectively reduce the clearance between a shaft and a rotatable element, such as a blade-fixing flange of a dicing saw for use with...
US-7,051,178 Burst write in a non-volatile memory device
A synchronous flash memory has been described that includes an array of non-volatile memory cells. The memory device has a package configuration that is...
US-7,050,708 Delivery of solid chemical precursors
Systems and methods are provided for delivering solid precursors. In certain embodiments of the present application, a flow monitor is used to measure and...
US-7,050,649 Suppression of ringing artifacts during image resizing
An economical method of detecting and suppressing ringing artifacts during digital image resizing is presented. The economical method substitutes costly division...
US-7,050,425 Apparatus for multiple media digital communication
Apparatus for media communication in a communication system. In one embodiment, the apparatus comprises: a processor; and a routine running on the processor for...
US-7,050,342 Testmode to increase acceleration in burn-in
A method and apparatus for simultaneously accessing multiple array blocks in a static random access memory (SRAM) device. During testing of the SRAM device, each...
US-7,050,330 Multi-state NROM device
An array of NROM flash memory cells configured to store at least two bits per four F.sup.2. Split vertical channels are generated along each side of adjacent...
US-7,050,327 Differential negative resistance memory
The invention relates to a DNR (differential negative resistance) exhibiting device that can be programmed to store information as readable current amplitudes...
US-7,050,319 Memory architecture and method of manufacture and operation thereof
An architecture, and its method of formation and operation, containing a high density memory array of semi-volatile or non-volatile memory elements, including,...
US-7,050,094 Wide dynamic range operation for CMOS sensor with freeze-frame shutter
Wide dynamic range operation is used to write a signal in a freeze-frame pixel into the memory twice, first after short integration and then after long...
US-7,049,861 Reduced current input buffer circuit
There is provided an input buffer circuit that, in one embodiment, includes an input buffer adapted to draw an operating current, a first buffer enabling...
US-7,049,840 Hybrid interconnect and system for testing semiconductor dice
An interconnect is provided for making electrical connections with a semiconductor die. The interconnect includes a substrate having integrally formed contact...
US-7,049,753 Method and apparatuses for providing uniform electron beams from field emission displays
The invention includes field emitters, field emission displays (FEDs), monitors, computer systems and methods employing the same for providing uniform electron...
US-7,049,700 Semiconductor test board having laser patterned conductors
A method for fabricating semiconductor components is performed using a laser scanner and a laser imaging process. A substrate, such as a semiconductor wafer,...
US-7,049,693 Electrical contact array for substrate assemblies
A substrate assembly is disclosed including a substrate and a plurality of spring-biased electrical contacts formed thereon for establishing electrical contact...
US-7,049,685 Packaged microelectronic devices with pressure release elements and methods for manufacturing and using such...
Packaged microelectronic devices, interconnecting units for packaged microelectronic devices, and methods and apparatuses for packaging microelectronic devices...
US-7,049,664 Semiconductor device structures formed by ion-assisted oxidation
Oxidation methods, and resulting structures, comprising providing an oxide layer on a substrate and then re-oxidizing the oxide layer by vertical ion bombardment...
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