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Patent # Description
US-7,061,109 Semiconductor substrate-based BGA interconnection for testing semiconductor devices
The present invention relates to a method of forming interconnections for a temporary package, wherein the interconnections are capable of receiving solder balls...
US-7,061,092 High-density modularity for ICS
A high-density multi-chip module and method for construction thereof, wherein a plurality of integrated circuit dice with at least one row of generally central...
US-7,061,085 Semiconductor component and system having stiffener and circuit decal
A semiconductor component includes a stiffener, a circuit decal attached to the stiffener, and a semiconductor die attached to the stiffener. The circuit decal...
US-7,061,082 Semiconductor die with attached heat sink and transfer mold
A semiconductor device includes a heat sink adjacent to a die. A dam is positioned at the peripheral edges of the heat sink. During a transfer molding process,...
US-7,061,071 Non-volatile resistance variable devices and method of forming same, analog memory devices and method of...
In one implementation, a non-volatile resistance variable device includes a body formed of a voltage or current controlled resistance setable material, and at...
US-7,061,004 Resistance variable memory elements and methods of formation
A method and apparatus for providing a resistance variable memory element with improved data retention and switching characteristics have at least one...
US-7,060,637 Methods of forming intermediate semiconductor device structures using spin-on, photopatternable, interlayer...
A cap layer that enables a photopatternable, spin-on material to be used in the formation of semiconductor device structures at wavelengths that were previously...
US-7,060,631 Methods of cleaning surfaces of copper-containing materials, and methods of forming openings to...
The invention encompasses a semiconductor processing method of cleaning a surface of a copper-containing material by exposing the surface to an acidic mixture...
US-7,060,615 Methods of forming roughened layers of platinum
A method of forming a roughened layer of platinum, including: a) providing a substrate within a reaction chamber; b) forming an adhesion layer over the...
US-7,060,608 System and method for filling openings in semiconductor products
Explosive forces are used to fill interconnect material into trenches, via holes and other openings in semiconductor products. The interconnect material may be...
US-7,060,599 Method of forming shallow doped junctions having a variable profile gradation of dopants
Disclosed is an electrical device having, and a process for forming, a shallow junction with a variable concentration profile gradation of dopants. The process...
US-7,060,570 Methods of fabricating multiple sets of field effect transistors
The invention includes methods of fabricating multiple sets of field effect transistors. In one implementation, an etch stop layer is formed over an insulative...
US-7,060,569 Methods of fabricating multiple sets of field effect transistors
The invention includes methods of fabricating multiple sets of field effect transistors. In one implementation, an etch stop layer is formed over an insulative...
US-7,060,526 Wafer level methods for fabricating multi-dice chip scale semiconductor components
A semiconductor component includes a base die and a secondary die stacked on and bonded to the base die. The base die includes conductive vias which form an...
US-7,060,521 Bonding method
The present invention relates to a method to form an integrated device, said device comprising a first substrate and at least one element provided on a second...
US-7,060,514 Process for fabricating films of uniform properties on semiconductor devices
A process for forming a thin layer exhibiting a substantially uniform property on an active surface of a semiconductor substrate includes varying the temperature...
US-7,059,937 Systems including differential pressure application apparatus
A differential pressure application apparatus is configured to apply different amounts of pressure to different locations of a substrate, such as a semiconductor...
US-7,059,491 Apparatus and method for observing chemical substances
An apparatus and method for observing a chemical substance. In one embodiment, the apparatus includes a vessel having a base portion and an at least partially...
US-7,059,267 Use of pulsed grounding source in a plasma reactor
A method for grounding a semiconductor substrate pedestal during a portion of a high voltage power bias oscillation cycle to reduce or eliminate the detrimental...
US-RE39,126 Two-step chemical mechanical polishing process for producing flush and protruding tungsten plugs
A method for forming conductive plugs within an insulation material is described. The inventive process results in a plug of a material such as tungsten which is...
US-7,058,849 Use of non-volatile memory to perform rollback function
A mechanism and method for maintaining a consistent state in a non-volatile random access memory system without constraining normal computer operation is...
US-7,058,799 Apparatus and method for clock domain crossing with integrated decode
An apparatus and method for transferring signals between timing domains. The apparatus includes a receiver for receiving signals operative in a first timing...
US-7,058,778 Memory controllers having pins with selectable functionality
Systems and methods for selecting pin functionality in memory controllers are provided. These memory controllers have pins that can be used to drive different...
US-7,058,533 Calibration of memory circuits
Memory circuits are calibrated by adjusting memory circuit output parameters based on data eye measurements. Data eye patterns of memory circuit outputs are...
US-7,057,945 Non-volatile memory erase circuitry
A non-volatile memory device includes floating gate memory cells, a pulse counter and voltage pump control circuitry. The control circuitry selectively activates...
US-7,057,935 Erase verify for non-volatile memory
A memory device verify system determines a state of memory cells in a memory. The memory includes a memory array having a plurality of memory cells coupled to...
US-7,057,933 Non-volatile memory device with erase address register
A non-volatile memory device includes an array of non-volatile memory cells. The memory has control circuitry to erase the non-volatile memory cells and perform...
US-7,057,932 Flash memory
Flash memory supporting methods for erasing memory cells using a decrease in magnitude of a source voltage of a first polarity to increase the magnitude of a...
US-7,057,623 Texture addressing circuit and method
A texture addressing circuit and method for calculating texture coordinates according to various texture addressing modes for texture maps having arbitrary...
US-7,057,429 Method and apparatus for digital phase generation at high frequencies
An apparatus and method for generating phase related clocks, includes delaying a clock input by a cycle delay magnitude to generate a cycle delay signal and N...
US-7,057,416 Enhanced protection for input buffers of low-voltage flash memories
An input buffer is discussed that inhibits semiconductor breakdown of thin gate-oxide transistors in low-voltage integrated circuits. One aspect of the input...
US-7,057,373 Battery-powered electronic device with spaced contact extensions
Battery mounting and testing apparatuses and methods of forming the same are described. In one implementation, a substrate includes a surface area over which a...
US-7,057,297 Tape substrates with mold gate support structures that are coplanar with conductive traces thereof and...
A mold gate of a tape substrate includes an aperture formed in the flexible dielectric film of the tape substrate and a support element which is carried by a...
US-7,057,291 Methods for securing vertically mountable semiconductor devices in back-to back relation
A method for assembling vertically mountable semiconductor devices includes positioning the semiconductor devices so that backsides thereof face one another and...
US-7,057,289 Etch stop in damascene interconnect structure and method of making
An interconnect structure with a plurality of low dielectric constant insulating layers acting as etch stops is disclosed. The low dielectric constant materials...
US-7,057,285 Aluminum interconnects with metal silicide diffusion barriers
An aluminum interconnect which extends adjacent to and is insulated from a stacked capacitor structure to facilitate electrical communication between an active...
US-7,057,281 Microelectronic component assemblies employing lead frames having reduced-thickness inner lengths
The present disclosure suggests various microelectronic component assembly designs and methods for manufacturing microelectronic component assemblies. In one...
US-7,057,263 Semiconductor wafer assemblies comprising photoresist over silicon nitride materials
In one aspect, the invention includes a semiconductor processing method, comprising: a) providing a silicon nitride material having a surface; b) forming a...
US-7,057,257 Semiconductor processing methods of forming transistors, semiconductor processing methods of forming dynamic...
Semiconductor processing methods of forming transistors, semiconductor processing methods of forming dynamic random access memory circuitry, and related...
US-7,057,225 Semiconductor memory circuitry
Processes are disclosed which facilitate improved high-density memory circuitry, most preferably dynamic random access memory (DRAM) circuitry. An integrated...
US-7,057,223 Circuit and method for a folded bit line memory cell with vertical transistor and trench capacitor
A memory cell for a memory array in a folded bit line configuration. The memory cell includes an access transistor formed in a pillar of single crystal...
US-7,057,220 Ultrashallow photodiode using indium
The invention provides an imager having a p-n-p photodiode with an ultrashallow junction depth. A p+ junction layer of the photodiode is doped with indium to...
US-7,057,218 Edge intensive antifuse
An antifuse including a bottom plate having a plurality of longitudinal members arranged substantially parallel to a first axis, a dielectric layer formed on the...
US-7,056,833 Methods of filling gaps and methods of depositing materials using high density plasma chemical vapor deposition
The invention includes a method of filling gaps in a semiconductor substrate. A substrate and a gas mixture containing at least one heavy-hydrogen compound are...
US-7,056,823 Backend metallization method and device obtained therefrom
A semiconductor device and a method of making it are described. During the formation of the semiconductor device, a hard mask is formed of an etch-resistant...
US-7,056,812 Process for strengthening semiconductor substrates following thinning
A semiconductor wafer having a high degree of thinness and exhibiting an enhanced strength state. A layer of tenacious reinforcement material is disposed over a...
US-7,056,806 Microfeature workpiece processing apparatus and methods for controlling deposition of materials on microfeature...
The present disclosure provides methods and apparatus useful in depositing materials on batches of microfeature workpieces. One implementation provides a method...
US-7,056,784 Methods of forming capacitors by ALD to prevent oxidation of the lower electrode
A method of forming a capacitor includes forming a conductive metal first electrode layer over a substrate, with the conductive metal being oxidizable to a...
US-7,056,771 Method of forming an array of semiconductor packages
A semiconductor package is provided which includes a substrate having a plurality of semiconductor dice mounted thereon. The substrate is divided into segments...
US-7,056,762 Methods to form a memory cell with metal-rich metal chalcogenide
The invention relates to the fabrication of a resistance variable material cell or programmable metallization cell. The processes described herein can form a...
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