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Patent # Description
US-7,078,284 Method for forming a notched gate
Methods for forming notched gates and semiconductor devices utilizing the notched gates are provided. The methods utilize the formation of a dummy gate on a...
US-7,078,267 Methods of fabricating integrated circuitry
A substrate including a plurality of integrated circuitry die is fabricated or otherwise provided. The individual die have bond pads. A passivation layer...
US-7,078,266 Method for fabricating semiconductor components with thinned substrate, back side contacts and circuit side...
A semiconductor component includes back side pin contacts fabricated using a circuit side fabrication method. The component also includes a thinned semiconductor...
US-7,078,264 Stacked semiconductor die
The present invention provides methods and apparatus related to preventing adhesive contamination of the electrical contacts of a semiconductor device in a...
US-7,078,249 Process for forming sharp silicon structures
A method of forming a sharp silicon structure, such as a silicon field emitter, includes oxidizing the silicon structure to form an oxide layer thereon, then...
US-7,078,243 Shielding arrangement to protect a circuit from stray magnetic fields
A shielding arrangement for protecting a circuit containing magnetically sensitive materials from external stray magnetic fields. A shield of a material having a...
US-7,078,239 Integrated circuit structure formed by damascene process
An integrated circuit structure is formed using a damascene process that involves forming a trench or cavity for the structure in a temporary layer of material....
US-7,077,975 Methods and compositions for removing group VIII metal-containing materials from surfaces
A method and composition for removing Group VIII metal-containing materials from a surface (preferably, a platinum-containing, and more preferably, a...
US-7,077,902 Atomic layer deposition methods
An aluminum-containing material deposition method includes depositing a first precursor on a substrate in the substantial absence of a second precursor. The...
US-7,077,733 Subpad support with a releasable subpad securing element and polishing apparatus including the subpad support
A subpad support for use in a web format or belt format polishing apparatus for polishing one or more layers of semiconductor device structures. The subpad...
US-7,077,722 Systems and methods for actuating end effectors to condition polishing pads used for polishing microfeature...
Systems and methods for activating end effectors used to condition microfeature workpiece polishing pads are disclosed. A system in accordance with one...
US-RE39,195 Polishing pad refurbisher for in situ, real-time conditioning and cleaning of a polishing pad used in...
A pad refurbisher that provides in situ, real-time conditioning and/or cleaning of a polishing surface on a polishing pad used in chemical-mechanical polishing...
US-RE39,194 Method and apparatus for controlling planarizing characteristics in mechanical and chemical-mechanical...
A method and apparatus for mechanical and/or chemical-mechanical planarization of microelectronic substrates. In one embodiment, an apparatus for controlling the...
US-7,076,702 Memory with element redundancy
A memory device to perform an erase operation algorithm that specifically deals with different types of defects in a memory array. The memory array of one...
US-7,076,697 Method and apparatus for monitoring component latency drifts
A method and apparatus for monitoring the response times of computer system components in order to improve computer system reliability and performance are...
US-7,076,678 Method and apparatus for data transfer
A memory system and method according to various aspects of the present invention comprises a memory and an adaptive timing system for controlling access to the...
US-7,076,012 Measure-controlled delay circuit with reduced playback error
A timing control circuit for synchronizing an output clock signal with an input clock signal includes a pulse generator, a measure delay array, a measure...
US-7,075,924 Methods for multiple media digital communication
Methods for media communication in a digital communication system. In one embodiment, the media comprises a plurality of media types (including for example...
US-7,075,901 Communication systems, communication apparatuses, radio frequency communication methods, methods of...
The present invention provides communication devices, communication systems and methods of communicating. According to one embodiment of the invention, a...
US-7,075,857 Distributed write data drivers for burst access memories
An integrated circuit memory device is designed to perform high speed data write cycles. An address strobe signal is used to latch a first address. During a...
US-7,075,856 Apparatus for latency specific duty cycle correction
The illustrated embodiments relate to a control circuit that is adapted to use a latency signal to generate an output signal. The latency is adapted to be used...
US-7,075,850 Compact decode and multiplexing circuitry for a multi-port memory having a common memory interface
A memory array for a multi-port memory having a common memory interface and a plurality of memory ports through which the memory array is accessed is provided....
US-7,075,832 Method for erasing an NROM cell
An operation to erase a nitride read only memory (NROM) memory block starts by erasing the memory block. An erase verify operation can then be performed to...
US-7,075,831 Method for erasing an NROM cell
An operation to erase a nitride read only memory (NROM) memory block starts by erasing the memory block. An erase verify operation can then be performed to...
US-7,075,829 Programmable memory address and decode circuits with low tunnel barrier interpoly insulators
Structures and methods for programmable memory address and decode circuits with low tunnel barrier interpoly insulators are provided. The decoder for a memory...
US-7,075,819 Closed flux magnetic memory
A closed flux magnetic memory cell has a ferromagnetic pinned structure and a ferromagnetic free structure. Data is stored by controlling the relative...
US-7,075,816 Quad flat no-lead (QFN) grid array package, method of making and memory module and computer system including same
A quad flat no-lead (QFN) grid array semiconductor package and method for making the same is disclosed. The package includes a semiconductor die and a lead frame...
US-7,075,808 Method for bus capacitance reduction
Data bus capacitance is reduced by decoupling unaccessed memory circuits from a data bus during data transfers to or from other memory circuits.
US-7,075,763 Methods, circuits, and applications using a resistor and a Schottky diode
A combination of a current limiting resistor and a clamping Schottky diode prevent substantial forward biasing of a pn junction associated with a pad in a...
US-7,075,693 Addressing method of movable elements in a spatial light modulator (SLM)
The present invention relates to a method for modulating at least one pulse of electromagnetic radiation with a spatial light modulator. At least one...
US-7,075,470 Ramp generators for imager analog-to-digital converters
An imager with an analog-to-digital converter having at least one ramp generator that precisely and efficiently produces the desired ramp voltages required by...
US-7,075,330 System and method for balancing capacitively coupled signal lines
A signal balancing circuit for capacitively coupled signaling between transmitting and receiving devices over a plurality of capacitively coupled signal lines on...
US-7,075,173 Interposer including adhesive tape
Two dice may be provided within a single package so that one pin and associated leadfinger may be coupled to bond pads on different dice. This may mean that two...
US-7,075,166 Coating of copper and silver air bridge structures to improve electromigration resistance and other applications
An improved electrical interconnect for an integrated circuit and methods for providing the same are disclosed. The electrical interconnect includes an air...
US-7,075,146 4F.sup.2 EEPROM NROM memory arrays with vertical devices
NROM EEPROM memory devices and arrays are described that facilitate the use of vertical NROM memory cells and select gates in NOR or NAND high density memory...
US-7,075,049 Dual conversion gain imagers
An imager with dual conversion gain floating diffusion regions. The dual conversion gain regions yield (1) high conversion gain and sensitivity to achieve...
US-7,074,724 Etchant and method of use
A method of anisotropiocally etching a semiconductive substrate uses a hydrofluorocarbon etch gas with an etch selectivity fluorocarbon gas. The fluorocarbon gas...
US-7,074,717 Damascene processes for forming conductive structures
A method and apparatus for providing a conductive structure adjacent to a damascene conductive structure in a semiconductor device structure. The semiconductor...
US-7,074,673 Service programmable logic arrays with low tunnel barrier interpoly insulators
Structures and methods for in service programmable logic arrays with low tunnel barrier interpoly insulators are provided. The in-service programmable logic...
US-7,074,648 Method for packaging flip-chip semiconductor assemblies
Flip-chip semiconductor assemblies, each including integrated circuit (IC) dice and an associated substrate, are electrically tested before encapsulation using...
US-7,074,114 Carrier assemblies, polishing machines including carrier assemblies, and methods for polishing micro-device...
Carrier assemblies, polishing machines with carrier assemblies, and methods for mechanical and/or chemical-mechanical polishing of micro-device workpieces are...
US-7,074,113 Methods and apparatus for removing conductive material from a microelectronic substrate
A method and apparatus for removing conductive material from a microelectronic substrate. In one embodiment, a support member supports a microelectronic...
US-7,073,161 Methods of forming patterned reticles
The invention includes methods of forming patterned reticles. Design features can be introduced into a layout for a reticle prior to optical proximity...
US-7,073,039 Providing a register file memory with local addressing in a SIMD parallel processor
A degree of local addressing is provided for a processing element array by partitioning a register file memory (e.g., data columns, data rows), and adding a...
US-7,073,034 System and method for encoding processing element commands in an active memory device
A command engine for an active memory receives high level tasks from a host and generates corresponding sets of either DRAM control unit ("DCU") commands to a...
US-7,073,016 Random access interface in a serial memory device
A random access interface is provided to a non-volatile, serial memory array. An address multiplexer has an external address connection and a serial address...
US-7,073,014 Synchronous non-volatile memory system
A computer system comprises a memory controller and a synchronous non-volatile memory device coupled to the memory controller via a main memory bus. The...
US-7,072,923 Method and apparatus for generating deterministic, non-repeating, pseudo-random addresses
A system and method for rapidly generating a series of non-repeating, deterministic, pseudo-random addresses is disclosed. A deterministic, pseudo-random number...
US-7,072,812 Interpolation error minimization for data reduction
Systems and methods are provided for reducing a set of data points into a subset of best fit data points. According to one aspect, a method of adjusting a series...
US-7,072,433 Delay locked loop fine tune
A digital delay locked loop (DLL) includes a coarse delay segment and fine delay segment. The coarse delay segment includes a coarse delay range. The fine delay...
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