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Patent # Description
US-7,041,595 Method of forming a barrier seed layer with graded nitrogen composition
A barrier layer material and method of forming the same is disclosed. The method includes depositing a graded metal nitride layer in a single deposition chamber,...
US-7,041,575 Localized strained semiconductor on insulator
One aspect of this disclosure relates to a method for straining a transistor body region. In various embodiments, oxygen ions are implanted to a predetermined...
US-7,041,570 Method of forming a capacitor
A method of forming a capacitor is disclosed. The method includes forming a first substrate layer, and forming a first electrode on the first substrate layer....
US-7,041,556 Vertical transistor and method of making
The invention relates to a vertical transistor and an oxidation process that achieves a substantially curvilinear recess bottom. The recess serves as the gate...
US-7,041,550 Device and method for protecting against oxidation of a conductive layer in said device
In a semiconductor device including a first conductive layer, the first conductive layer is treated with a nitrogen/hydrogen plasma before an additional layer is...
US-7,041,548 Methods of forming a gate stack that is void of silicon clusters within a metallic silicide film thereof
A method for forming a gate stack which minimizes or eliminates damage to the gate dielectric layer and/or silicon substrate during the gate stack formation by...
US-7,041,547 Methods of forming polished material and methods of forming isolation regions
In one aspect, the invention encompasses a method of forming a polished material. A substrate is provided and an elevational step is provided relative to the...
US-7,041,537 Method for fabricating semiconductor component with on board capacitor
A semiconductor component includes a semiconductor die, and an on board capacitor on the die for filtering transient voltages, spurious signals and power supply...
US-7,041,533 Stereolithographic method for fabricating stabilizers for semiconductor devices
One or more stabilizers are disposed on the surface of a semiconductor device component prior to bonding the same to a higher-level substrate. Upon assembly of...
US-7,041,532 Methods for fabricating interposers including upwardly protruding dams
A method for fabricating an interposer includes providing an interposer substrate with at least one slot or aperture therethrough and forming at least one...
US-7,041,513 Methods for forming semiconductor devices so as to stabilize the same when positioned face-down over test...
One or more of stabilizers are disposed on the surface of a semiconductor device or test substrate that includes bond pads or contact pads located at or...
US-7,041,341 Process for the fabrication of oxide films
The present invention is related to methods and apparatus for processing weak ferroelectric films on semiconductor substrates, including relatively large...
US-7,040,965 Methods for removing doped silicon material from microfeature workpieces
Methods for removing material from microfeature workpieces are disclosed. A method in accordance with one embodiment of the invention includes disposing a...
US-7,040,930 Modular sockets using flexible interconnects
A modular bare die socket assembly is provided for attaching a plurality of miniature semiconductor die to a substrate. The socket assembly is comprised of a...
US-7,039,751 Programmable cache system
A plurality of cache addressing functions are stored in main memory. A processor which executes a program selects one of the stored cache addressing functions...
US-7,039,492 Numerical control apparatus for machine tool and numerical control method for machine tool
A numerical control apparatus for machine tool, includes: an NC program storage portion for storing an NC program; a block skip command detection portion for...
US-7,038,970 Programming and evaluating through PMOS injection
A PMOS transistor includes a gate, drain, and source in a substrate and is isolated from adjacent transistors in the substrate by shallow trench isolation. The...
US-7,038,966 Memory device and method having data path with multiple prefetch I/O configurations
A memory device is operable in either a high mode or a low speed mode. In either mode 32 bits of data from each of two memory arrays are prefetched into...
US-7,038,958 Dual stage DRAM memory equalization
A memory device equilibrates voltages in a bit line pair to a reduced voltage level. The reduced equilibrate voltage level can be achieved by separating the...
US-7,038,954 Apparatus with equalizing voltage generation circuit and methods of use
A memory device includes an equalization voltage generator. The equalization voltage generator includes an oscillator and a charge pump to produce a first...
US-7,038,945 Flash memory device with improved programming performance
A selected wordline that is coupled to a cell to be programmed is biased during a program operation. The unselected wordlines are biased with a negative...
US-7,038,940 Pulsed write techniques for magneto-resistive memories
A magneto-resistive memory that has a shared word line and sense line is disclosed. By providing the shared word line and sense line, the number of relatively...
US-7,038,927 High speed data bus
The invention comprises data processing systems and components thereof. Such systems may include a memory controller, a plurality of memory devices, a data bus...
US-7,038,762 Method and apparatus for irradiating a microlithographic substrate
A method and apparatus for exposing a radiation-sensitive material of a microlithographic substrate to a selected radiation. The method can include directing the...
US-7,038,679 Three dimensional rendering including motion sorting
The present invention determines that an object is moving within a scene. At run time, the number of primitives used to represent the moving object is reduced....
US-7,038,521 Voltage level shifting circuit with improved switching speed
Voltage level shifting circuits have circuit devices coupled across sourcing output transistors to improve the switching speed of the low voltage to high voltage...
US-7,038,511 System and method for comparison and compensation of delay variations between fine delay and coarse delay circuits
A compensation circuit and method for compensating for variations in time delay adjustments of synchronizing circuits that synchronize an external clock signal...
US-7,038,481 Method and apparatus for determining burn-in reliability from wafer level burn-in
A method and apparatus for determining burn-in reliability from wafer level burn-in are disclosed. The method according to the present invention includes...
US-7,038,475 Test method for semiconductor components using conductive polymer contact system
A contact system for electrically engaging semiconductor components includes an interface board mountable to an automated test handler, and a floating substrate...
US-7,038,318 Compound structure for reduced contact resistance
Various embodiments of the invention described herein reduce contact resistance to a silicon-containing material using a first refractory metal material...
US-7,038,315 Semiconductor chip package
A semiconductor chip package that includes discrete conductive leads in electrical contact with bond pads on a semiconductor chip. This chip/lead assembly is...
US-7,038,286 Magnetoresistive memory device assemblies
The invention includes a construction comprising an MRAM device between a pair of conductive lines. Each of the conductive lines can generate a magnetic field...
US-7,038,265 Capacitor having tantalum oxynitride film and method for making same
A capacitor has a tantalum oxynitride film. One method for making the film comprises forming a bottom plate electrode and then forming a tantalum oxide film on...
US-7,038,263 Integrated circuits with rhodium-rich structures
A structure and method are disclosed for forming a capacitor for an integrated circuit. The capacitor includes a rhodium-rich structure, a rhodium oxide layer in...
US-7,038,259 Dual capacitor structure for imagers and method of formation
CMOS and CCD imaging devices comprising different in-pixel capacitors and peripheral capacitors and methods of formation are disclosed. The capacitors used in...
US-7,037,862 Dielectric layer forming method and devices formed therewith
Embodiments in accordance with the present invention provide alternative materials, and methods of forming such materials, that are effective as dielectric...
US-7,037,860 Modified source/drain re-oxidation method and system
Methods and devices are disclosed utilizing a phosphorous-doped oxide layer that is added prior to re-oxidation. This allows greater control of the re-oxidation...
US-7,037,848 Methods of etching insulative materials, of forming electrical devices, and of forming capacitors
In one aspect, the invention encompasses a method of etching insulative materials which comprise complexes of metal and oxygen. The insulative materials are...
US-7,037,840 Methods of forming planarized surfaces over semiconductor substrates
The invention includes a method of forming a planarized surface over a semiconductor substrate. A substrate is provided which includes a memory array region and...
US-7,037,829 Compound structure for reduced contact resistance
Various embodiments of the invention described herein reduce contact resistance to a silicon-containing material using a first refractory metal material...
US-7,037,808 Method of forming semiconductor constructions
The invention includes a semiconductor construction. The construction has a semiconductor material die with a front surface, a back surface in opposing relation...
US-7,037,775 Applying epitaxial silicon in disposable spacer flow
A process for forming active transistors for a semiconductor memory device by the steps of: forming transistor gates having generally vertical sidewalls in a...
US-7,037,771 CMOS imager with a self-aligned buried contact
An imaging device formed as a CMOS semiconductor integrated circuit includes a buried contact line between the floating diffusion region and the gate of a source...
US-7,037,764 Method of forming a contact in a pixel cell
A method of implanting, for example, a phosphorous plug over a charge collection region and a method of forming a contact over the phosphorous plug implant and...
US-7,037,756 Stacked microelectronic devices and methods of fabricating same
Certain methods of the invention permit spacerless manufacture of stacked microelectronic devices by mechanically supporting a second microelectronic component...
US-7,037,751 Fabrication of stacked microelectronic devices
Manufacture of stacked microelectronic devices is facilitated by producing subassemblies wherein adhesive pads are applied to the back surfaces of a plurality of...
US-7,037,730 Capacitor with high dielectric constant materials and method of making
Stabilized capacitors and DRAM cells using high dielectric constant oxide dielectric materials such as Ta.sub.2O.sub.5 and Ba.sub.xSr.sub.(1-x)TiO.sub.3, and...
US-7,037,179 Methods and apparatuses for making and using planarizing pads for mechanical and chemical-mechanical...
Methods and apparatuses for planarizing a microelectronic substrate. In one embodiment, a planarizing pad for mechanical or chemical-mechanical planarization...
US-7,037,178 Methods for conditioning surfaces of polishing pads after chemical-mechanical polishing
The invention includes a method for conditioning a surface of a polishing pad after chemical-mechanical polishing of a semiconductor substrate with the pad...
US-7,037,177 Method and apparatus for conditioning a chemical-mechanical polishing pad
A conditioner including abrasive elements for conditioning a polishing pad to be used in abrasive semiconductor substrate treatment processes, such as...
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